JPH0638648B2 - Dual screen tv receiver - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual-screen television receiver in which a part of an image on a television screen is reduced and a screen of another image is inserted.

2. Description of the Related Art A conceptual diagram of a dual-screen television receiver is shown in FIG. this is,
A combined screen (hereinafter, referred to as a child screen) 302 is inserted into a combined screen (hereinafter, referred to as a parent screen) 301. There are various possible reduction ratios for the small screen, but for the following two reasons, a reduction ratio of 1/3 is often used both vertically and horizontally.

(1) It does not disturb the main screen so much, and the size of the sub screen is appropriate.

(2) The vertical 1 / n reduction method of the sub-screen is to create image data for one horizontal synchronization period from image data for n horizontal synchronization periods. However, since the TV signal is interlaced, it is an odd number. If it is 1, it can be thinned out evenly in the vertical direction. Explaining this point with reference to FIG. 4, (a)
Shows the case of 1/3 thinning in the vertical direction, and (b) shows the case of thinning 1/4 in the vertical direction. E _{1 to} E ₉ are even field lines (horizontal synchronization), and O _{1 to} O ₉ are odd field lines. First, in (a), E ₁ , E in odd fields
_{, 4} , E ₇ , ... In the even field, O ₃ , O ₆ ,.
Are sampled at a ratio of 1 line to 3 lines, so that they are evenly spaced in the vertical direction. On the other hand, in (b),
In the even field, if E ₁ , E ₅ , E ₉ ... Are sampled at a ratio of 1 line to 4 lines, in the odd field, if 1 line is simply sampled to 4 lines, the vertical direction cannot be evenly spaced. so 'a, _{O 7} from _{O 7} and _{O 8} Metropolitan' _{O 3} from _{O 3} and _{O 4} Metropolitan and it is necessary to synthesize each taking vertical correlation. In this way, when the vertical direction is reduced to an even number, the circuit scale becomes larger than when it is reduced to an odd number (a memory for vertical correlation and an adder are required), It is a disadvantage.

As a conventional technology that realizes such a function, `` Monitor-in-TV '' Television Society Technical Report TEBS99-2 S.59.
Some are listed in 9.20. FIG. 2 shows an overall block diagram thereof. The sub-picture video signal input 1 is written in the field memory 2 according to the write address generation circuit 4 controlled by the sub-picture synchronization signal input 3 in order to synchronize vertical and horizontal synchronizations. CR of data in field memory 2
If reading is performed according to the read address generation circuit unit 7 controlled by the parent screen synchronization signal 6 that deflects T5, synchronization between the parent screen and the child screen is realized. While reading the field memory 2, the output data is displayed on the CRT.
5 and when the switch 9 is switched so that the parent screen video signal 8 is output to the CRT 5 when not being read,
The child screen 302 can be inserted into the parent screen 301.

The write address generation circuit section 4 and the read address generation circuit 7 have the same configuration although the operation speeds are different.
The internal block diagram is shown in FIG. The horizontal sync signal input 801 and the vertical sync signal input 802 determine from which address of the field memory 2 the image data is read and written. The vertical address output 808 specifies the line number, and the horizontal address output 807 specifies the pixel position within the horizontal sync. Reference numerals 805 and 806 are binary counters, which count the clocks from the respective control circuit units 803 and 804 from 0 to the larger one, and all become 0 by the clear input.

In this conventional example, the vertical address output 808 is 6 bits and ranges from "000000" to "111111", and the child screen 302 is composed of 64 lines per field.
This is for the following reason. There are 262.5 lines per field for NTSC TV video signals, of which 2
One line is a vertical blanking period. Further, due to the performance of the television receiver, about 90% of them are actually displayed on the parent screen 301. As for the child screen 302, if the number of lines is 1/3 of that, the child screen 302 and the parent screen 301 are displayed. The information display ranges of and become equal. That is, (26
2.5-21) x 0.9 / 3 ≈ 72. Therefore, 72 is suitable for the number of lines of the child screen 302 in calculation.

However, in order to use the memory efficiently, the vertical address is generally set to 2 ^m . ²⁶ is 64,
2 ⁷ is 128, above 72 is an intermediate value, than was 128 it means to use Amashi large memory, the vertical address outputs 6 bits, 1
It has been common practice to configure the child screen 302 with 64 lines of fields.

Problems to be Solved by the Invention As is clear from the above, the parent screen 301 and the child screen 3 are clear.
The number of sub-screen lines required to make the information display range of 02 equal is 72, but actually it is 64, so the information display range in the vertical direction is narrowed by 10% or more. In particular, it is inconvenient when the character information is lost due to this.

In the dual-screen television receiver of the present invention, the horizontal address generation circuit of the field memory for synchronizing the parent-child screen is a circuit for counting up to 7 in octal, and the vertical address generation circuit is a 7-bit circuit. Use a binary counter to count the horizontal sync signal or the octal count output of the horizontal address generation circuit, and which of the two is to be counted is automatically switched by the most significant bit of the vertical address generation circuit. Thus, the sub-picture is reduced to 1/3 in the vertical direction without information loss in the vertical direction.

Function As described above, the number of pixels in the horizontal direction is set to 7/8, and a new line is added to the vacant place, so that the number of lines per field of the sub-screen can be increased and the information in the vertical direction is lost. It is something that can be eliminated.

Embodiment Hereinafter, a two-screen television receiver according to an embodiment of the present invention will be described with reference to the drawings. The overall block diagram is the same as the conventional example and is FIG. The inside of the address generating circuit sections 4 and 7 is formed as shown in FIG. 1 in one embodiment of the present invention.
The horizontal synchronizing signal input 101 and the vertical synchronizing input 102 combine the horizontal address output 103 and the vertical address output 104. Reference numeral 105 is a horizontal address generation circuit, and 106 is a vertical address generation circuit. Reference numeral 107 denotes a binary counter, which counts the clock 109 from the horizontal address control circuit unit 108 from 0 to the larger one, and a clear input 110 causes all the outputs of the binary counter 107 to become zero. Reference numeral 111 denotes a 3-input NAND gate, which outputs an output once every eight clocks 109. 112
Is a counter, which sends the output to the horizontal address control circuit unit 108 when the output of the NAND gate 111 is counted 7 times. The output of the NAND gate 111 is 2 in the vertical address generation circuit unit 106.
It is input to one side of the input 1 output switch 113. The horizontal sync signal input 10 is applied to the other input of the switch 113.
1 is input, and the switch 113 is controlled by the most significant bit output of the binary counter 114. The output of the most significant bit is three O's in the horizontal address generation circuit 105.
It is also input to the R gate 115. Binary counter 114
Counts the output of the switch 113 in the larger direction from "0", and all the outputs become "0" by the clear output of the vertical address control circuit unit 116.

FIG. 5 shows the relationship between the horizontal and vertical addresses of the field memory 2 which the address generating circuit intends to control. In the figure, ~ are line numbers of the child screen 302. A 6-bit horizontal address of H5 to H0 is assigned to the horizontal axis, and a 6-bit vertical address of V5 to V0 is assigned to the vertical axis. The data of the corresponding line number is read and written from the location of the corresponding address.

Next, the operation of the horizontal address generation circuit section 105 will be described with reference to the waveform chart of FIG. (b) is a clear signal 110
Then, the binary counter 107 counts the clock signal 109 when it is at a high potential. The output H0-H5 'is (C)
~ (H). A value obtained by converting these 6-bit binary signals into a decimal number with H5 'as the most significant bit is also shown at HO (c).

When HO (c), H1 (d) and H2 (e) are all high potential, NAN
The output of the D gate 111 has a low potential as shown in (i). This rising is counted by the counter 112, and when it becomes “7”,
Output a pulse as in (j). This output is transmitted to the horizontal address control circuit unit 108 to set the clear signal 110 to a low potential and set the binary counter 107 to all "0".
That is, the horizontal address generation circuit unit 105 counts the clock signal 109 in octal up to "7". This 8 × 7 = 56
It corresponds to the number of pixels per horizontal period.

Next, regarding the operation of the vertical address generation circuit unit 106,
This will be described with reference to the waveform chart of FIG. The switch 113 is connected to the horizontal simultaneous signal 101 side when the output V6 of the binary counter 114 is "0", and to the output side of the NAND 111 when it is "1". The binary counter 114 starts counting when the clear signal input changes from 0 to 1. At this time, since V6 is 0, the horizontal synchronizing signal input 101 (k) is counted. Line numbers ~ are also shown in (k). Line numbers V0 (n) to V5 (s) are all "1",
At the next horizontal sync signal input 101, V6 (t) becomes "1". That is, the output of the switch 113 is the NAND gate 1
11 outputs are connected. After that, the binary counter 114
Is counted seven times in the horizontal period. V after 9 lines
0 to V6 all become "1". At this time, the vertical address control circuit unit 116 next clears the binary address counter 114 with the horizontal synchronizing signal, and all outputs become "0".

The operation during this period will be described with reference to memory address allocation in FIG. One line consists of 56 pixels. From the line number to, V5 to V0 correspond to the line number as they are. For pixels, H5 to H0 are "00000" to "11011
The number of 1 "is 56. Next, every time the H address of each line changes 8 times, the V address changes once. Then, when the V address changes 7 times, the next horizontal address changes. The number of pixels during this period is 8 × 7,
56, the same as. Since V6 is "1" during the period of to, all the outputs of the OR gate 115 are fixed to "1", so that H5 to H0 are "111000".
It changes repeatedly between "111111".

After all, in the field memory 2, the address generating circuit of FIG.
Pixels corresponding to each line 56 are assigned. However,
The lower right eight pixels corresponding to FIG. 5 remain unused.

EFFECTS OF THE INVENTION As described above, according to the field memory address generation circuit of the dual-screen television receiver of the present invention, the number of lines of the sub-screen can be up to 73 by using the same memory as the conventional one. . This is sufficient for the 72 lines in which the vertical information display ranges of the parent screen and the child screen are equal to each other. Note that the pixel equivalent to the horizontal period is 6
It decreased from 4 to 56. The actual pixels on the screen are these two
It is generally doubled to 128 and 112. In the main screen, the number of lines in one field is 262.5 and the number of pixels in one line is about 350. Therefore, if the child screen is also proportional to that, there are 72 lines in one field, so 350 × 72.
÷ 262.5 = 96 (pixels / line) is enough. Therefore, 112 pixels / line is sufficient in the present invention.

As described above, according to the present invention, there is provided a two-screen television receiver in which the vertical direction is reduced without information loss in the vertical direction without increasing the memory capacity, greatly increasing the circuit scale, and degrading the image quality. It can be configured and is extremely advantageous in practical use.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an address generation circuit section of a field memory of a dual-screen television receiver according to an embodiment of the present invention, FIG. 2 is an overall block diagram of the dual-screen television receiver, and FIG.
FIG. 4 is a conceptual diagram of a dual-screen television receiver, FIG. 4 is an explanatory diagram of line samples of interlaced signals, FIG. 5 is an explanatory diagram of address allocation in a field memory, and FIG. 6 is a horizontal diagram in one embodiment of the present invention. FIG. 7 is an operation waveform diagram of the address generating circuit, FIG. 7 is an operation waveform diagram of the vertical address generating circuit in the embodiment of the present invention, and FIG. It is a figure. 101 ... Horizontal sync signal input, 102 ... Vertical sync signal input, 103 ... Horizontal address output, 104 ... Vertical address output, 105 ... Horizontal address generation circuit section, 10
6 ... Vertical address generation circuit section, 107 ... Binary counter, 112 ... Counter, 113 ... Switch, 114 ...
… A binary counter.

Claims (1)

[Claims] 1. An image data for one horizontal synchronizing period is created from image data of a plurality of horizontal synchronizing periods of a synthesized video signal and is inserted into a synthesized video signal.
As a memory address generation circuit that stores image data for fields, a horizontal address generation circuit that counts up to 7 in octal and a vertical address generation circuit using a 7-bit binary counter are provided. 2 counts the horizontal sync signal or the octal count output of the horizontal address generation circuit, and which of the two is counted is automatically switched by the most significant bit output of the vertical address generation circuit. Screen tv receiver.