JP2537812B2 - Video signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device that allows a television broadcast image to be viewed while holding a reproduced image of a video tape by using a memory.

2. Description of the Related Art In recent years, video tape recorders (hereinafter referred to as VTRs) have become widespread, and there is a demand for functions that are easier to use. VTR
If you want to watch TV broadcast while playing
I should switch from play mode to stop mode,
When trying to view the VTR playback image again, the video tape is wrapped around the rotary head cylinder and the playback image is output after the rotation of the rotary head cylinder stabilizes, so the playback image cannot be immediately returned. For this reason, currently
"Picture in Picture" (hereinafter referred to as PinP)
Under the name, a function of simultaneously displaying a reproduced image and a television broadcast image by using a memory is considered. Of the replay image and the television broadcast image, one of them is displayed as the main screen to fill the screen of the television receiver, and the other is used as the child screen to make a reduced screen. A part of the screen of the television receiver (usually four screens). Somewhere near one corner).

Hereinafter, an example of the above-described conventional video signal processing device will be described with reference to the drawings.

FIG. 4 is a block diagram of a conventional video signal processing device. In FIG. 4, reference numeral 30 denotes a video signal input terminal serving as a main screen, 31 denotes a video signal input terminal serving as a sub screen,
32 is an A / D converter that performs analog-to-digital conversion of the input video signal into a digital video signal, 33 is an A / D converter 32
Input data from the buffer memory 35 and memory 36
Is a memory data control circuit that inputs and outputs data to and outputs the data to the D / A converter 34, and 34 is a D / A converter that converts a digital video signal into an analog video signal. Reference numeral 35 is a buffer memory for temporarily storing a video signal, 36 is a memory, and the buffer memory 35 and the memory 36 are, for example, a dynamic random access memory (D-RAM).
It is composed of 37 is a memory address control circuit that controls the addresses of the buffer memory 35 and the memory 36, 38 is a write clock generation circuit that generates a memory writing clock that is synchronized with the video signal of the small screen, 39 is a video signal for the small screen A sync signal separation circuit for writing that detects a sync signal, 40 is a read clock generation circuit that generates a clock for reading the memory synchronized with the video signal of the parent screen, 41 is a read that detects the sync signal from the video signal for the parent screen It is a synchronizing signal separation circuit for. 42 is a switch for switching the video signal of the main screen and the video signal of the sub screen,
43 is a video signal output terminal.

The operation of the conventional video signal processing device configured as described above will be described below.

The PinP function in the conventional video signal processing device is
Since both sub-screens are displayed as moving images, the sub-screen writing is controlled by using the clock and sync signal that are based on the sub-screen video signal, and the sub-screen is read by the main screen video signal. And the synchronization signal must be used for control, and both the clock and the synchronization signal are two-system signals, which complicates the configuration and operation. The operation is that the video signal that is the sub-screen input from the input terminal 31 is A /
It is converted into a digital video signal by the D converter 32 and input to the memory data control circuit 33. The input digital video signal is generated by the write clock generation circuit 38 and the write sync signal separation circuit 39, and the memory address control circuit 37 is based on the clock and vertical / horizontal sync signal synchronized with the video signal serving as the sub-screen. Are written to the buffer memory 35 in accordance with the address signals generated by the memory and signals for controlling the memory such as writing / reading.
After that, the memory generated by the read clock generation circuit 40 and the read sync signal separation circuit 41, and generated by the memory address control circuit 37 on the basis of the clock and vertical / horizontal sync signals which are synchronized with the video signal serving as the main screen. Buffer memory 35 according to the signal that controls the memory
Data is transferred to 36. Then, the memory address control circuit 37 uses the vertical / horizontal sync signal of the video signal which is the parent screen and is sent from the read sync signal separation circuit 41.
The period during which the main screen is displayed and the period during which the sub screen is displayed are detected, the switch 42 is switched accordingly, and control is performed to read data from the memory 36 during the period during which the sub screen is displayed.

Problems to be Solved by the Invention However, in the above-mentioned configuration, a clock generating circuit and a sync signal separating circuit for two systems of a parent screen and a child screen are required, and the memory is continuously operated by two asynchronous clocks. It is difficult to perform a read operation while writing data, and a buffer memory is required, which makes control of the configuration and operation extremely complicated. Also, when watching a television broadcast on the main screen, the tape playback image is displayed on the sub screen because the tape is running continuously, but it is often overlooked, and the playback screen is displayed again. When it is viewed on the screen, it has to be rewound and reviewed again, which causes a problem that the operation is troublesome.

In view of the above problems, in the present invention, when the tape is set to PinP during reproduction, the reproduced image is first memorized as the parent screen, the tape running is stopped, and then the television broadcast signal is continuously written as the child screen. As a result, since the clock and the synchronization signal have one system, it is possible to read and write continuous data in one memory.
(EN) Provided is a video signal processing device whose operation is very easy to control.

Means for Solving the Problems In order to solve the above problems, a video signal processing device of the present invention is a synchronization signal for detecting a synchronization signal from a video signal in a memory having a capacity capable of storing at least one field of the video signal. A separation circuit and a first writing mode for reading data from the memory and writing a video signal in the memory based on the synchronization signal, and a screen written in the first writing mode as a large screen and a small screen as a part thereof. As a memory control circuit having a second write mode for writing a video signal so that the screen becomes a reduced image, a switch for setting a two-screen mode for simultaneously displaying a large screen and a small screen, and a video tape recorder for reproduction. Medium When the switch is pressed, a command to write the reproduced video signal of the video tape to the memory control circuit in the first write mode Is sent and the running of the video tape is stopped, and then a command to write the video signal of the television broadcast in the second writing mode is sent to the memory control circuit, and the output control is performed so that the signal read from the memory becomes the video output signal. And a control circuit for setting the two-screen mode.

According to the present invention, with the above-described structure, the memory is controlled on the basis of the clock / synchronization signal synchronized with the reproduced video signal of the tape before the two-screen mode is set, and the television broadcast video signal is set after the two-screen mode is set. The memory and the synchronization signal are controlled on the basis of the clock and the synchronization signal which are synchronized with each other, so that the clock and the synchronization signal always have one system, which simplifies the configuration and the control method of the memory. Further, since the tape running is stopped in the two-screen mode, a troublesome operation of overlooking the reproduced image and rewinding the tape when watching a television broadcast is unnecessary.

Example Hereinafter, the video signal processing device of the example of the present invention,
This will be described with reference to the drawings.

FIG. 1 is a block diagram of a video signal processing device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a video signal processing device that outputs a composite video signal from a reproduction signal of a video head (not shown) during reproduction, and outputs a composite video signal of television broadcasting at times other than reproduction. An A / D converter for analog-to-digital conversion of the input video signal into a digital video signal, and 3 are serial-parallel (S / S) that store a plurality of input serial data and output as parallel data.
P) converter, 4 is a parallel-serial (P / S) converter that sequentially selects a plurality of input parallel data, and outputs as serial data. 5 is a D / that converts a digital video signal into an analog video signal. The A converter 6 is a memory having a storage capacity capable of accumulating a digital video signal for one field, and is composed of, for example, a dynamic random access memory (D-RAM). Reference numeral 7 is a sync signal separation circuit for detecting vertical and horizontal sync signals from the video signal output from the video signal processing circuit 1, 8 is a clock generation circuit for generating a clock synchronized with the video signal, and 9 is for the memory 6. A memory control circuit for controlling writing / reading, 10 a switch for setting / releasing the PinP mode, 11 a control circuit for controlling each circuit according to the input of the switch 10, 12 a tape drive circuit for controlling tape running, 13
Is an audio signal processing circuit for outputting a tape reproduction audio signal or a television broadcasting audio signal in accordance with a command from the control circuit 11, and 14 is an output signal of the video signal processing circuit 1 and D / A.
A switch for selecting the output signal of the converter 5, 15 is an output terminal for a video signal, and 16 is an output terminal for an audio signal.

The operation of the video signal processing apparatus of the present embodiment configured as described above will be described below with reference to FIG. 1, FIG. 2 and FIG.

FIG. 2 shows control signals and write data for the memory.
It is a figure which shows read data.

The memory control circuit 9 sets the memory 6 alternately in the write mode and the read mode in accordance with the reference clock from the clock generation circuit 8 and outputs the CAS (column address strobe) signal, RAS, required for writing and reading.
A (row address strobe) signal, a WE (write enable) signal, an OE (output enable) signal, etc. are generated and supplied to the memory 6. Figure 2 (a) is RA
S signal waveform, (b) shows the CAS signal waveform,
A write mode and a read mode are set for each time (WE signal and OE signal are not shown).

A data write operation to the memory 6 when the mode is set in this way will be described.

The digital video signal sampled by the A / D converter 2 is converted into, for example, four parallel data by the S / P converter 3. This operation will be described with reference to FIGS. 2 (c) to 2 (f). FIG. 2 (c) is a diagram showing the data (W _{1-0 to} W _2-3 ) sampled by the A / D converter 2, which is four times before writing the next time after writing in the memory once. Data is being sampled. The S / P converter 3 is composed of, for example, four types of shift registers and a latch circuit, and inputs the signal of FIG. 2 (c) according to a command from the memory control circuit 9 to sample the four types of shift registers. The signals shown in FIGS. 2 (c) to 2 (f) are generated by shifting each time, and four types of data immediately before the memory enters the write mode are latched and supplied to the memory 6. In the writing (1) of FIG. 2, the data W _1-0 , W _1-1 , W _1-2 , W _1-3 are latched, and the memory 6
Will be sent to and written to. In this way, the S / P converter 3 operates so as to be able to write continuous data in the memory by accumulating a plurality of high-speed data at the write timing of the memory and supplying the data to the memory. The address signal to the memory 6 in the write cycle is also output from the memory control circuit 9. Then, the memory control circuit 9
By switching the sampling command to the S / P converter 3 and the write address signal to the memory 6 output from two types, the parent screen and the child screen can be written. That is, the write data is sequentially sampled at the timing shown in FIG.
If the address signal to 1 is also sequentially updated, the video signal of 1 field is stored in the full capacity of the memory 6 of 1 field to become the main screen, and the frequency of the sampling command to the S / P converter 3 is reduced to 1/3. When the horizontal scanning line is also stored once every three times and the address signal to the memory 6 is controlled to output only one part of a certain memory address, both the vertical and horizontal directions are 1 with respect to the main screen. The reduced screen with the length of / 3 is stored as a sub screen. The memory control circuit 9 sets the memory address according to the vertical / horizontal sync signals output from the sync signal separation circuit 7 so that the relative positions of the parent screen and the child screen are not displaced, and at the time of writing the child screen. Writes in by thinning out only the effective part of the screen that can be displayed on the television receiver, excluding the vertical and horizontal sync signals.

Next, the operation of reading data from the memory 6 will be described.

In the read cycle of FIG. 2, the memory control circuit 9 outputs the read address to the memory 6. Memory 6
There are four types of data read from the memory because four types of data are written at the same address during writing. P / S
The converter 4 sequentially processes four types of data read from the memory 6 at the same time according to a command from the memory control circuit 9.
It is supplied to the converter 5. This operation will be described with reference to FIGS. 2 (g) and (h). At the timing of reading (1), four types of data R _1-0 , R _1-1 , R _1-2 shown in FIG.
・ R _1-3 is read from the memory 6, and the P / S converter 4 latches the four types of data in response to a command from the memory control circuit 9 and sequentially outputs R _{1- as} shown in FIG. 2 (h). ₀ / R _1-1 / R _1-2 / R
It is supplied to the D / A converter 5 in the order of _1-3 .

As described above, by performing S / P conversion / P / S conversion of data, even if the write mode and read mode are set separately for the memory, the data is not interrupted and continuous data can be read. It is configured.

Next, the PinP operation and the processing of the video signal at that time will be described.

FIG. 3 is a diagram showing the state of the screen of the television receiver, FIG. 3 (a) is the state of the screen during playback, FIG. 3 (b) is the state of the screen immediately after becoming PinP, and FIG. Figure (c)
The screen state of PinP mode is shown. While the tape is being reproduced, the control circuit 11 controls the switch 14 so that the output signal of the video signal processing circuit 1 is output to the video signal output terminal 15.
As a result, the screen of the television receiver becomes a moving image of the tape reproduction signal as shown in FIG. Then switch
When 10 is pressed, the control circuit 11 first sends a command to the memory control circuit 9 to write the video signal as it is without reduction, and switches the switch 14 to the D / A converter 5 side. As a result, the reproduced video signal at that time is written in the memory 6,
The screen of the television receiver is a still image of the reproduced video signal shown in FIG. 3 (b). After that, the control circuit 11 sends a command to stop the tape running to the tape drive circuit 12 and sends a command to output a television broadcast signal to the video signal processing circuit 1 and the audio signal processing circuit 13, and then the memory control circuit. 9 Send the command to reduce the video signal vertically and horizontally to 1/3 and write it continuously at the lower left position of the screen. As a result, the screen is the third
As shown in Fig. (C), the audio is also in PinP mode in which the television broadcast can be heard. When the switch 10 is pressed in the PinP mode, the control circuit 11 sends a command to start the tape running to the tape drive circuit 12, and outputs the tape reproduction signal to the video signal processing circuit 1 and the audio signal processing circuit 13. When a command is sent and the switch 14 is switched, the screen becomes the original screen of FIG. 3 (a).

The size and display position of the reduced screen may be set in any manner.

As described above, according to the present embodiment, even though two types of asynchronous video signals are displayed simultaneously, there is only one clock and synchronization signal for controlling the memory.
The memory can be easily controlled.

As described above, according to the present invention, the reproduced image is first written in the memory and then the television broadcast image is reduced and continuously written on the reproduced image. Therefore, one type of clock and synchronization signal is used. Therefore, the buffer memory becomes unnecessary, and the memory configuration and the circuit configuration for controlling the memory become very simple. Also, while watching a television broadcast on PinP, the tape running is stopped, so Pi
If you release the nP, you can see it from the playback image that you were watching earlier, so you can save the trouble of rewinding the tape and it will be very easy to use.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts of a video signal processing apparatus according to an embodiment of the present invention, and FIG. 2 is a timing diagram showing control signals and write data / read data to a memory in the embodiment of the present invention. FIG. 4 is a display state diagram showing a screen of a television receiver, and FIG. 4 is a block diagram of essential parts of a conventional video signal processing device. 1 ... Video signal processing circuit, 2 ... A / D converter, 3 ... S / P
Converter, 4 ... P / S converter, 5 ... D / A converter, 6 ... Memory, 7 ... Synchronous signal separation circuit, 8 ... Clock generation circuit, 9 ... Memory control circuit, 10 ... … Switch, 11 …… control circuit, 12 …… tape drive circuit, 13 …… audio signal processing circuit.

Claims (3)

(57) [Claims] 1. A memory having a capacity capable of accumulating at least one field of a video signal, a sync signal separation circuit for detecting a sync signal from the video signal, reading data from the memory, and storing the data in the memory on the basis of the sync signal. A first writing mode for writing a video signal and a second writing mode for writing a video signal such that the screen written in the first writing mode is a large screen and a small screen is formed in a part of the screen. And a switch for setting a dual screen mode for displaying a large screen and a small screen at the same time, and a video tape playback video signal to the memory control circuit when the switch is pressed during playback of the video tape recorder. Is sent in the first writing mode, the video tape is stopped from running, and then the memory control is performed. A control circuit for setting a two-screen mode by sending an instruction to write a video signal of a television broadcast in a second writing mode to the channel and controlling output so that the signal read from the memory becomes a video output signal. A video signal processing device characterized by. 2. The video signal processing device according to claim 1, wherein the control circuit controls the output so that the audio signal of the television broadcast becomes an audio output signal in the two-screen mode. . 3. The control circuit is configured to start the running of the video tape when a switch or another specific switch is pressed in the two-screen mode and output the playback signal of the video tape as video / audio output. The video signal processing device according to claim (1) or (2).