JPH0547024B2 - - Google Patents

Description

[Detailed description of the invention] <Technical field> The present invention relates to a television receiver.

<Prior art> Conventionally, for example, picture-in-picture (PIP) television receivers have
The screen that occupies most of the CRT screen is the parent screen,
In contrast, a child screen is a screen smaller than the main screen, and separate images can be displayed on each screen. On the main screen of such a television receiver, a video of a program that the viewer particularly wants to view is generally displayed in a large size, so that the viewer can enjoy the program. Furthermore, it is very convenient to display other videos on the sub-screen, and when a desired video is displayed on the sub-screen, you can enjoy the video without missing the chance to view it.

By the way, in such a television receiver, when displaying television images and images from external video equipment such as a video tape recorder or video disk, it is necessary to display not only images from one external video equipment but also images from multiple external video equipment. There are times when you want to display images from a device. However, conventional television receivers are inconvenient because they cannot simultaneously display television images and images from multiple external video devices on the same CRT screen.

<Object of the Invention> The present invention has been made in view of the above-mentioned points, and provides a method for simultaneously displaying television images and images from multiple external video devices on the same screen as a main screen and multiple child screens. It is an object of the present invention to make a television receiver multi-functional by making it possible to switch between a main screen and a sub-screen at will.

<Structure of the Invention> In order to achieve the above-mentioned object, the present invention includes a main body circuit portion that processes normal television images, and a special image processing circuit that performs special image processing for multiple sub-screen display modes. The main circuit portion includes a tuner, a video amplification circuit that amplifies and outputs a video signal output from the tuner, a first signal processing means having a synchronization signal processing circuit and a video signal processing circuit, and a CRT. , a video output circuit to a CRT, and the special image processing circuit portion includes a second signal processing means having a synchronization signal processing circuit and a video signal processing circuit, and a video amplification circuit of the main circuit portion. One of the video signals and external video signals from a plurality of external video devices is given to the first signal processing means, and the other video signals are given to the second signal processing means at a predetermined period.
a first switching means that sequentially and selectively supplies the signal to the signal processing means; an A/D converter that converts the video signal from the second signal processing means into a digital signal;
A buffer memory that stores the digital video signal from the converter by thinning out the number of scanning lines, a single display memory that stores the digital video signal transferred from the buffer memory, and a digital video signal read from the display memory. a D/A converter that converts the video signal into an analog video signal; a second switching device that selectively switches the video signal from the first signal processing device or the D/A converter and supplies the video signal to the video output circuit; and a control unit that performs switching control of the means and writing/reading control of the buffer memory and the display memory, and in the plurality of small screen display modes, one of the normal images based on the video signal from the first signal processing means is provided. A plurality of sub-screen moving images based on the video signal from the D/A converter are displayed on the screen.

<Examples> Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit block diagram of the entire television receiver according to an embodiment of the present invention.
In this specification, as shown in FIG. 2, television images and images from a plurality of external video devices are displayed on a main screen C and on a plurality of (three in this embodiment) child screens D1,
The case where images are displayed as D2 and D3 is called a child screen display mode.

This television receiver is broadly divided into a main body circuit part A that performs image processing so as to display television images or images from external video equipment in a normal state on a single screen, and a main circuit part A that processes television images or images from external video equipment on a single screen; A special image processing circuit section B performs image processing for a sub-screen display mode in which images from video equipment are displayed as a main screen and three sub-screens.

In the main circuit section A, 1 is a television antenna, 2 is a tuner, 3 is a video amplification circuit, 4 is a first signal processing means having a synchronization signal processing circuit 5 and a video signal processing circuit 6, 7 is a video output circuit, and 8 is a video output circuit. Deflection coil 9 is a CRT. Such a configuration is
Since it is similar to a normal television receiver, we will only list the names and omit the explanation of its operation.

The special image processing circuit section B includes a video input changeover switch 13 as a first switching means to which a video signal from the video amplification circuit 3 and external video signals V1, V2, and V3 from three external video devices are input, and a special A video output changeover switch 18 is provided as a second switching means that selects the image-processed video signal from the D/A converter 17 or the video signal from the first signal processing means 4 and supplies the selected video signal to the video output circuit 7. There is.

The video input changeover switch 13 switches between the video signal from the video amplification circuit 3 and the external video signal V1, based on the switching control signal S1 from the system control unit 19.
One of the four types of video signals V2 and V3 is given to the first signal processing means 4, and the remaining three types of video signals are time-divided every field (vertical synchronization signal period). The signals are sequentially applied to the two signal processing means 12.

FIG. 3 is a detailed diagram of this video input changeover switch 13. The video input changeover switch 13 includes a first switch group 27 for selecting a video signal to be applied to the first signal processing means 4 and a second switch group 28 for selecting a video signal to be applied to the second signal processing means 12. , and a third switch group 29 for sequentially switching three types of video signals from the second switch group 28 for each field and applying the same to the second signal processing means 12. The first switch group 27 is for selecting a video signal to be displayed on a normal display section, and includes a first switch 27a to which a video signal from the video amplification circuit 3 is applied, and an external video signal V1 from an external video device. , V2, and V3, respectively. One of the video signals from the first to fourth switches 27a to 27d is applied to the first signal processing means 4, and the remaining three types of video signals are applied to the second switch group 28. The second switch group 28 includes first to third switches 28a to 28c, and supplies the three types of video signals from the first switch group 27 to the third switch group 29. The third switch group 29 includes the first to
Consisting of third switches 29a to 29c, the video signal from the second switch group 28 is sequentially switched every field (vertical synchronization signal period) and is applied to the second signal processing means 12. That is, in the first one field period, the first switch 29a is closed, in the next one field period, the second switch 29b is closed, and in the next one field period, the third switch 29c is closed, and so on. The video signal from the second switch group 28 is switched and output.

The video output changeover switch 18 has a first individual contact 18a connected to the video signal processing circuit 6 of the first signal processing means 4, a second individual contact 18b connected to the D/A converter 17, and a video output circuit. 7, and a movable contact 18c connected to the system control unit 1.
The switching is controlled as follows by the switching control signal S2 from 9. That is, during normal single screen display, the movable contact 18c is the first individual contact 1.
It is switched to the 8a side. On the other hand, in a plurality of child screen display modes, when a child screen is displayed, the movable contact 18c is switched and moved to the second individual contact 18b side,
When the main screen is displayed, the movable contact 18c is switched and moved to the first individual contact 18a side.

In normal single-screen display, for example, when displaying a television image from the tuner 2, the switching control signal S1 from the system control unit 19 is
As a result, the video signal from the video amplification circuit 3 is supplied from the video input changeover switch 13 to the first signal processing means 4, and the video output changeover switch 18 is activated by the changeover control signal S2 from the system control section 19. The contact 18c is connected to the first individual contact 18a, whereby the video signal from the first signal processing means 4 is applied to the video output circuit 7 and amplified to a required level, similar to a normal television receiver. Only the TV image is displayed on the CRT9.

Next, the configuration of the main part of the present invention will be explained.
The special image processing circuit section B inputs signals from the video input switch 13 every field (vertical synchronization signal period).
The second signal processing means 12 is provided with a second signal processing means 12 for processing three types of video signals, for example, external video signals V1, V2, and V3, which are sequentially switched and outputted at the It has a circuit 10 and a video signal processing circuit 11.

In the description of this embodiment, the video amplification circuit 3
When the video signal from the external video signal V1, V2, V3 is switched field by field and is supplied to the second signal processing means 12, that is, in the small screen display mode,
As shown in the figure, a case will be described in which a television image from tuner 2 is displayed on the main screen and images from external video equipment are displayed on three child screens.

Video signal processing circuit 11 of second signal processing means 12
The processed video signal is converted into a digital signal by the A/D converter 14 and sent to the buffer memory 15.
is stored in The image signal is taken into the buffer memory 15 at a rate of one for every three horizontal scanning lines. That is, the second
The horizontal synchronizing signal SH1 from the synchronizing signal processing circuit 10 of the signal processing means 12 is input as a clock to the ternary counter 20, and the clock from the reference oscillation circuit 30 is given by the output from the ternary counter 20. Column address counter 2
1, and this capture column address counter 2
The video signal is taken into the buffer memory 15 by the address signal from 1.

The video signal taken into the buffer memory 15 in one horizontal scanning period is transferred to and stored in the field memory 16, which is a display memory, in the next two horizontal scanning periods. This import and transfer are performed sequentially,
As will be described later, a sub-screen of the video is displayed. In storing to the field memory 16, the column address of the field memory 16 is specified by the display column address counter 22, and the row address is specified by the input row address counter 23, which is clocked by the output of the ternary counter 20.
is specified via the address switching circuit 24.

The address switching circuit 24 is switched and controlled by the switching control signal S3 from the system control unit 19.
The first individual contact 24a connected to the capture row address counter 21 and the display row address counter 2
5 and a movable contact 24c connected to the field memory 16. In this address switching circuit 24, when transferring the video signal from the buffer memory 15 to the field memory 16, the movable contact 24c is switched to the first individual contact 24a side, and when reading the video signal from the field memory 16, the movable contact 24c is switched to the first individual contact 24a side. 24c is switched and moved to the second individual contact 24b side.

When the first video signal V1 is stored in the field memory 16 for one field period in this way, each counter is cleared by the vertical synchronization signal SV1 from the synchronization signal processing circuit 10 of the second signal processing means 12. Furthermore, the system control unit 19
A switching control signal S is sent from the video input switching switch 13 to the video input switching switch 13.
1 is output and another video signal V2 is given to the second signal processing means 12. Similarly, when this video signal V2 is stored in the field memory 16 for one field period, another video signal V2 is output. V3
is applied to the second signal processing means 12 via the video input changeover switch 13 and processed in the same manner. When the storage of the three types of video signals V1, V2, and V3 is completed, the same process is repeated again.

Field memory 1 that is updated sequentially in this way
6 is read out and displayed during the display period of the child screen display mode. During this display period, the horizontal SH and vertical synchronization signals SV from the synchronization signal processing circuit 5 of the first signal processing means 4 are given to the system control section 19, and in response, the system control section 19 A horizontal synchronizing signal SH is sent to the address counter 22 and the display row address counter 25.
and the display line address counter 25
Give vertical synchronization signal SV to. As a result, the display column address counter 22, which is supplied with the clock from the display reference oscillation circuit 31, generates a column address, and the display row address counter 25, which is supplied with the horizontal synchronization signal SH2 as a clock, generates a row address. , the video signal from the field memory 16 is read out.

The video signal read out from the field memory 16 is aligned in timing by the output latch circuit 26, then converted into an analog signal by the D/A converter 17, and outputted as a video signal via the video output changeover switch 18 when displaying a sub-screen. The signal is amplified by circuit 7 and provided to CRT 9. This video signal changeover switch 18 is connected to the D/A converter 17 when displaying a small screen as described above.
The video signal of the child screen from the video signal processing circuit 6 of the first signal processing means 4 is supplied to the video output circuit 7 when the main screen is displayed. As a result, a main screen and three child screens are displayed as shown in FIG. 4.

The external video signals V1, V2, and V3 for the child screen are
As described above, each field is subjected to signal processing and sequentially stored in the field memory 16, so the video of each child screen becomes a new video every three fields.

In the above embodiment, the television image is used as the main screen and the image from the external video device is used as the sub screen. However, it is also possible to display one of the images from the external video device as the main screen and display the other images as the sub screen. Of course, it is also possible to display the main screen and any child screen instead of displaying all three child screens.

<Effects of the Invention> As described above, according to the present invention, the main circuit section that performs normal television image processing and the special image processing circuit section that performs special image processing for multiple sub-screen display modes. In the special image processing circuit section, a plurality of video signals are selected in a time-sharing manner, subjected to predetermined signal processing, converted into digital signals, stored in a memory, and read out from the memory during the display period of the small screen display mode. The main screen based on the video signal processed by the main circuit section and the multiple sub-screens based on the video signal from the memory of the special image processing circuit section are displayed at the same time. This is convenient for enjoying images from external video equipment at the same time, or for selecting the image you want to view. Moreover,
In the present invention, multiple video signals are selectively processed in a time-sharing manner in the special image processing circuit section.
There is no need to provide a plurality of processing circuits corresponding to the video signals, and a single display memory is sufficient, making the circuit configuration relatively simple and relatively inexpensive.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a diagram for explaining the sub-screen display mode.
The figure is a detailed diagram of the video input changeover switch, and FIG. 4 is a diagram showing an example of display in the small screen display mode according to an embodiment of the present invention. A...Main circuit part, B...Special image processing circuit part, 4...First signal processing means, 12...Second signal processing means, 13...Video input switching switch (first switching means), 14... ...A/D converter, 15...
Buffer memory, 16... Field memory (display memory), 17... D/A converter, 18... Video output switching switch (second switching means), 19...
System control unit.

Claims (1)

[Scope of Claims] 1. A main body circuit section that performs normal television image processing and a special image processing circuit section that performs special image processing for a plurality of child screen display modes, the main body circuit section comprising: A tuner, a video amplification circuit for amplifying and outputting a video signal output from the tuner, a first signal processing means having a synchronization signal processing circuit and a video signal processing circuit, a CRT, and a video output circuit to the CRT. The special image processing circuit portion includes a second signal processing means having a synchronization signal processing circuit and a video signal processing circuit, and a video signal from a video amplification circuit of the main circuit portion and an external signal from a plurality of external video devices. a first switching means for supplying one of the video signals to the first signal processing means and sequentially and selectively supplying the other video signals to the second signal processing means at a predetermined cycle; 2, an A/D converter that converts the video signal from the signal processing means into a digital signal, a buffer memory that stores the digital video signal from the A/D converter by thinning out the number of scanning lines, and a buffer memory that stores the digital video signal from the A/D converter, and a single display memory that stores a digital video signal; a D/A converter that converts the digital video signal read from the display memory into an analog video signal; and the first signal processing means or D/A converter. a second switching means for selectively switching the video signal from the device and applying it to the video output circuit; and switching control of the switching means;
and a control unit that controls writing and reading of the buffer memory and the display memory, and in the plurality of child screen display modes, a first
A television receiver characterized in that a plurality of small screen moving images based on the video signal from the D/A converter are displayed on a part of the normal image based on the video signal from the signal processing means.