JPS61193580A - Two-screen television receiver - Google Patents

Abstract

PURPOSE:To realize a two-screen television receiver with high resolution and high picture quality using a low-cost method by mounting two line-memory at least and screen change-over means and controlling not only a selective fetching means but also clock synchronization of fetch/read clocks against line memories. CONSTITUTION:Left half of the two-screen television receiver displays the image inputted from a video signal input terminal 61, while right half displays the image inputted from a external signal input terminal 62. When two screens are displayed, the control signal c of the switching circuit 65 must not be fixed at either 'high' or 'low' speed, but is set to switch 'high' and 'low' at high speed and select reciprocally the input signals a and b in the switching circuit 65. At this time, the frequency fc of the control signal c must be one half of the sampling clock frequency fck of the A/D converters 661 to 663. Thus high- quality picture images can be obtained by mounting only line memories and converting a scanning method to 1:1 non-interlacing method.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a two-screen television receiver that can simultaneously display two high-quality screens on one cathode ray tube display screen. [Background of the Invention] In order to make effective use of the cathode ray tube display screen in television receivers, so-called PIN technology has traditionally been used to display other television programs in a reduced size on a portion of the original television screen.
P (picture-in-picture format) televisions have been announced.The idea behind PinP is shown in Figures 6 to 10 below.
This will be briefly explained using figures.

FIG. 6 is a conceptual diagram of a PinP television screen, where 1 is a television receiver, 2 is a cathode ray tube, 3 is a main screen section, 4 is a child screen section into which another TV screen has been reduced and inserted, and the main screen , the sub-screens are in a format in which each channel can be selected independently. FIG. 7 shows an example of a method of inserting a sub-screen using a raster schematic diagram. In the same 1iW, ■ is the child screen before reduction, ■ is the parent screen into which the child screen is inserted, and the screen reduction rate of the child screen is calculated by setting the 0 screen reduction rate as (scanning period after reduction/scanning period of original signal). When both the vertical and horizontal directions are 1/3,
One out of every three scanning lines is extracted from the child screen (■), the horizontal period is compressed to 1/3 of the time axis, synchronized with the main screen, and then inserted into the main screen. Scanning line ■～
3 shows a part of the scanning line before and after reduction.

#! Figure 8 shows the state of child screen insertion on a time axis. ■ is the video signal before the reduction of the child screen, and ■ is the video signal of the main screen into which the child screen has been inserted.

When the screen reduction ratio is set to 1/3 in both the vertical and horizontal directions, one out of every three scanning lines is extracted from the sub-screen video signal and stored in analog or digital field memory, as shown in Figure 7. A two-screen TV signal can be obtained by writing the data into the sub-screen insertion position (bold-lined part) of the main screen video signal (2) and reading it out using a clock three times that of the writing clock.

FIG. 9 shows a typical conventional example of PinP television, and FIG. 10 shows its timing chart.

This conventional example is intended to display a child screen as a color image.

9th Fi! In J, 101 is 1 for television receiver.
1 is an antenna, 14 is a cathode ray tube, 21 is a main screen tuner, 22 is an IP/video detection circuit, 23 is a synchronization separation circuit, 24 is a color signal processing circuit, 25 is a video amplification circuit, 121
122 is a sub-screen luminance signal insertion circuit, 122 is a sub-screen color difference signal insertion circuit, and 26 is a matrix circuit.

Further, 102 is a child screen generation circuit, 31 is a child screen tuner, 32 is an IP/video detection circuit, 33 is a synchronization separation circuit, 34 is a color signal processing circuit, 35 is a video amplification circuit, and 36 is a (G-Y ) signal matrix circuit, 411 is a memory for luminance signals, 412 is a memory for (RY)/(B-Y) signals,
42 is a write click address generation circuit, 43 is [1
51 is (RY), (
52 is a phase shift circuit, and 53 and 54 are 7 lip-flop circuits that store and hold information for one picture element. In addition, in FIGS. 9 and 10, A indicates a sub-screen (RY) signal, B indicates a sub-screen (B-Y) signal, and B indicates a sub-screen (B-Y) signal.
) signal, and C is a switching signal of the switch circuit 51.

D and F represent the input signal and output signal of the memory 4120 for (几-Y)/(B-Y) signals, respectively. E is (RY)/
(B-Y) read clock signal of signal memory 412;
G and H are clock signals for driving the 7-lip, 70-tub circuits 53 and 54, respectively. J and I are respectively reduced,
These are the sub-screen (RY) signal and (B-Y) signal. Roughly K indicates the display period of the child screen.

First, processing of the child screen brightness signal will be described.

The brightness signal for the small screen obtained by the tuner 3 and the IF video detection circuit 32 is written to the memory 411 via the video amplifier circuit 35 using the clock of the write clock/address generation circuit 42 whose timing is set by the synchronization separation circuit 33. ◎The luminance signal written in the memory 411 is read out by the read clock/address generation circuit 43 whose insertion timing is determined according to the synchronization signal separated by the synchronization separation circuit 23 from the video signal of the main screen. 0 is inserted into the luminance signal of the main screen by the sub-screen insertion circuit 121. Next, processing of the sub-screen color difference signal will be described.

The sub-screen video signal obtained by the tuner 3 and the IP/detection circuit 32 is demodulated by the color signal processing circuit 34 to obtain two color difference signals: (几-Y) signal and (B-Y) signal B. . (
The (B-Y) signal A and the (B-Y) signal B are alternately selected by a switching signal CK synchronized with the clock of the write clock/address generation circuit 42. Therefore (RY)/
The input signal to the (B-Y) signal memory 412 is such that the (R-Y) signal A and the (B-Y) signal B are alternately selected, as shown in FIG.

On the other hand, the memory circuit output signal F read out at a predetermined timing by the readout quadruple signal gK is written into the seven-ribbon quadruple circuit 53m54 constituting one picture element memory.

The 7-rip 70-tube circuit 53 selects and writes only the (几-Y) signal at the rising timing of the clock signal q, while the 7-rip 7p-tube circuit 54 selects and writes the (B-Y) signal at the rising timing of the clock signal H. Y) Select and write only the signal. Therefore, 7 lip-flop circuits 53, 5
The output signals of No. 4 are I and J, respectively, and continuous sub-screen color difference signals are reproduced.

Next, from the sub-screen color difference signal, the (G-Y) matrix circuit 3
6, the (G-Y) signal was reproduced, and the signals were completed as described above (几-Y), (B-Y).

The (G-Y) signal is connected to the child screen color difference signal insertion circuit 122 of the television receiver 1010, where it is combined with the color difference signal of the main screen, and the cathode ray tube 14 is driven via the matrix circuit 26.

As explained above, in the conventional example of this PinP television, the color difference signal is alternately switched by 9J using a switching signal of a predetermined cycle and stored in the (B-Y)/(fL-Y) signal memory. Therefore, the number of pixels for each color difference signal is 1/2 that of the luminance signal, and the color difference signal memory circuit can be configured with a memory circuit having the same number of pixels as the luminance signal memory.

However, in the conventional example of this PinP TV,
In order to reduce the screen reduction rate to 1/3 in both the vertical and horizontal directions, in order to reduce the amount of memory required, we thinned out every third scanning line and reduced the number of samples in the horizontal period to about loo. Since the number of images is small, there were problems such as poor resolution and difficulty in reading text.

[Object of the Invention] An object of the present invention is to eliminate the drawbacks of the above-mentioned prior art and to realize a high-resolution, high-quality two-screen television signal using an inexpensive method.

[Summary of the invention]

In the present invention, one horizontal scanning line (l line) can be stored without the need for a side layer of field memory, which has a large memory capacity sufficient to store one field's worth of video signals, and therefore is expensive.
This makes it possible to simultaneously display two mutually synchronized input video signals on the same cathode ray tube screen using only a line memory that has a small memory capacity and is therefore inexpensive enough to store video signals for several minutes. , realized a 2° screen TV Jimin receiver in an inexpensive manner. In addition, since both screens are the same size, there is no need to perform operations such as thinning out and storing scan lines, and even when displaying two screens, the normal screen (one
You can obtain the same resolution as when displaying on a screen. Furthermore, by using the line memory, it is possible to convert a normal television signal based on the 2:1 interlaced scanning method into a television signal based on the 1:1 non-interlaced scanning method and display it on the screen. You can get the image.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, a 2:1 interlaced scanning video signal is converted into a 1:1 non-interlaced scanning video signal by line interpolation and displayed on the screen. Since the same numbers as in FIG. 9 represent the same functions, the explanation will be omitted.

Reference numeral 61 denotes a video signal input terminal, into which video signals from a VT box, VDP (video disc player), and ordinary television video signals obtained through an antenna, tuner, and IP/video detection circuit are input. Reference numeral 62 denotes an external input terminal, into which a video signal synchronized with the video signal input from the video signal input terminal 61 is input as a GB signal. 63 is Y
C separation circuit, 64 is GB→luminance/color difference conversion circuit, 65
is a video signal/external signal changeover switch circuit, and when the control signal of the switch circuit 650 is "high", K selects the video signal input from the video signal input terminal 61;
When it is "low", the video signal input from the external input terminal 62 is selected.

Reference numerals 44 and 45 indicate switching signal generation circuits, which control the switch circuit 65 and the switch circuit 51, respectively. 661-6
63 is an A/D converter, 68 is a color difference signal separation circuit, 6
91 to 693 are D/A converters. 671,67
Reference numeral 2 denotes a memory for a luminance signal and a memory for a point-sequential color difference signal, and both have the same configuration, each consisting of two line memories. The line memory is configured such that one side is reading while the other is writing.

In addition, in FIGS. 1 and 2, the switch circuit 65
Of the input signals to, the one from the video signal input terminal 61 is designated as 3, the one from the external input terminal is designated as b, and the control signal for the switch circuit 65 is designated as C. Also, d and e are respectively
The (几-Y) signal input to the switch circuit 51 and the (B
-Y) signal.

f is a control signal for the switch circuit 51, and g is a control signal for the switch circuit 5.
◇h indicating the output signal from 1 is (几-Y)/(B-Y)
Output signal of line memory 672 for point sequential color difference signal, i*
J is an output signal of the color difference signal separation circuit 68, which represents a (几-Y) signal and a (B-Y) signal, respectively.

Next, the circuit operation will be explained with reference to FIG. 1 and @2.

First, the operation in the normal one-screen display state will be explained. In the single screen display state, the switching signal generation circuit 4
The control signal C from 4 is ``high'' or @low''
Therefore, the output signal of the switch circuit 65 is only one of the input signal a from the video signal input terminal 61 and the input signal a from the external input terminal 62. At this time, the switch circuit 65
The luminance signal output from the luminance signal becomes digital data via the A/D converter 661, and is stored in the luminance signal line memory 6.
Once written to the D/A converter 691, it is read out twice in succession at twice the writing speed, and then the D/A converter 691
Then, the data becomes analog data again and is input to the matrix circuit 26.

On the other hand, the color difference signal output from the switch circuit 65 is converted into digital data via A/D converters 662 and 663, and then processed in the switch circuit 51 (R-Y
) signal d and (B-Y) signal e are alternately selected to produce a (几-Y)/(B-Y) point sequential color difference signal g.

That is, as shown in FIG. 2, when the control signal f of the switch circuit 510 is 'high', the (RY) signal d is selected, and when the control signal f is '@1 ow', the (B-Y) signal e is selected. and the frequency f of the control signal f is set to the A/D converter 6
1 of the sampling clock frequency 'ck of 62,663
/2, the output signal g will be a selection of both alternately as shown in the figure.0 The output signal g will be (R-Y)/(B-Y
) Once written into the line memory 672 for dot sequential color difference signals, it is read out twice in succession at twice the writing speed, and the color difference separation circuit 68 again outputs (R-Y) signals i and (B-Y). The signal j is separated into a D/A converter 69.
After becoming analog data at 2,693, it is input to the matrix circuit 26.

This series of processes for color difference signals is very similar to the color difference signal processing in the conventional PinP TV, and its purpose is to make the memory capacity required for color difference signal processing the same as the memory capacity required for luminance signal processing. This is for the purpose of
This is similar to the case of the conventional television.

Next, the circuit operation in the two-screen display state will be explained.

FIG. 3 is a conceptual diagram showing the screen display state of the two-screen television receiver according to the embodiment of the present invention.
The video input from the external signal input terminal 62 is displayed on the right half.

FIG. 4 is a timing chart of signals of various parts in FIG. 1 in a two-screen display state, and corresponds to a-j in FIG.

In the dual screen display state, the control signal C of the switch circuit 650 is not fixed at either "high" or "tow", but is changed at a very high speed as shown in FIG. 4C. gh" and "low" so that the input signal a and the input signal S are alternately selected in the switch circuit 65.

At this time, the frequency fc of the control signal C is the sampling frequency 'c of the A/D converters 661 to 663.
It is appropriate to set it to k O1/2. This is when the Taki height value of the reproducible frequency is in the normal single screen display state.
is the sampling frequency of the A/D converter 'c
k, whereas in the 2WJWJ display state, it is determined by the frequency of the control signal C, ltf. Considering this, the data after A/D conversion is as shown in #14, d.
, e, it is preferable to use fc-1/2 fck in which the input signals a and b are selected alternately.

The (RY) signal d and the (B-Y) signal e are alternately selected in the switch circuit 51 in the same manner as the color difference signal processing in the single screen display state, and the (几-Y)/(B-Y) point is selected. The color difference signal g is sequentially generated.

At this time, the frequency f of the switch circuit 510 control signal f,
is chosen so that f t-1/4' ck,
(B-Y)/(B-Y) point sequential color difference signal g is shown in Fig. 4 gK
As shown, during one period of the restraining signal f, the input signal a side 0 (RY) signal, ! : It is most convenient because all four signals, the (B-Y) signal, the (几-Y) signal on the input signal side, and the (B-Y) signal can be aligned.

The luminance signal and (R-Y)/(B-Y) signal g are stored in the luminance signal line memory 671 and (R-Y)/(B-Y), respectively.
) is written into the line memory 672 for point-sequential color difference signals. Input signal a will be displayed on the left side of the screen, and b will be displayed on the right side of the screen, so of the data input to the line memories 67 and 672, the data from input signal a will be displayed in the first half of the line memory, and the data from input signal b will be displayed on the right side of the screen. write clock address generation circuit 4 so that
2, the addresses are alternately switched.

As mentioned above, the frequencies of the control signals c and f are respectively fc
= 1/2 fck # fr= 1/4 fck! Ktlj:, address switching frequency fad
d''-1/2 As fck, an address in the first half of the memory and an address in the second half of the memory can be given alternately@This is indicated by hK.

However, this is not enough, so you need to do the following:

FIG. 5 shows the data written on the line memory divided into a portion W that needs to be visible on the screen and a portion U that does not need to be visible.

In Fig. 5, a indicates a video signal from the video signal input terminal 61, which indicates the data on the left side of the screen, and b indicates a video signal from the external input terminal 62, indicating data on the right screen on the m plane. The fifth drawing is for the normal screen, the part W that needs to be visible and the part V that is actually visible on the screen.
And Il. 1lIs Figure II is when the write address to the memory is switched at the frequency #fad and the data when displaying the 2WI screen is written to the memory, and the part U that does not need to be visible is visible on the screen. , the part W that needs to be visible protrudes from the screen.

+ tlE 5 fNm-a, By setting the start point of the address to a specific value like m-b, data a on the left screen is moved to the right, and data b on the right screen is moved.
It is necessary to shift it to the left and write it to the memory to make it look like I@5[IV ◇At this time, the period in which data is written is less than one horizontal scanning period, but the unwritten part can be read out. Even if it were, it would not be visible on the screen, so when reading it, the memory is read from the beginning and there is no effect.

Therefore, the data is read twice consecutively from the line memories 671 and 672 at twice the speed of writing, and the luminance signal is converted directly to I)/A, and (R-Y)/(B
-Y) point sequential color difference signal is separated into (RY) signal i and (B-Y) signal j by color difference signal separation circuit 68, then D/A converted and input to matrix circuit 26. .

Regarding the deflection system, the horizontal period is the normal horizontal period of 63.5
It is necessary to drive with a horizontal synchronizing signal that is half of μSee c. Also, when displaying two screens, the horizontal size is half of the normal one screen size, so there is a method to keep the aspect ratio at 4=3 by halving the vertical size. However, even though the vertical size is the same, it doesn't look too unnatural.

In the actual Wi example described above, when converting a television signal using the 2:1 interlaced scanning method to one using the l:1 non-interlaced scanning method, only repeated interpolation of the previous scanning line is performed. Even if other interpolation methods, which are more complicated, are to be performed, the other interpolation methods can be easily performed by simply slightly changing the configurations of the line memories 671 and 672 and their peripheral parts.

In addition, the memory capacity required for conventional PinP is 64Kb.
However, according to this embodiment, s'ck=
14 (Mllz), and the digital data is Gbit for the luminance signal and 6 bits for the color difference signal, the required memory capacity is 28 (Kbit), which is about 40% of the conventional amount, so it is very inexpensive and On top of that, you can get a high-quality screen that allows you to clearly read even the smallest details.

〔Effect of the invention〕

According to the present invention, by providing only a line memory without using a field memory, two mutually synchronized input video signals can be displayed simultaneously on the cathode ray tube surface. There is no need to extremely reduce or thin out scanning lines to store them, so even the smallest characters can be seen clearly, and by converting the scanning method to a 1=1 non-interlaced scanning method, you can obtain high-quality images. I can do it. Furthermore, since the memory capacity used is very small, a two-screen receiver can be realized economically.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram of each line signal during one-screen display in the embodiment of FIG. 1, and FIG. 3 is a two-screen television receiver according to the present invention. Conceptual diagram of the two-screen display of #! Figure 4 is a timing diagram of each line signal during two-screen display in the embodiment shown in Figure 1;
Fig. 5 is an explanatory diagram for explaining the state of writing to the line memory in this embodiment, Fig. 6 is a conceptual diagram of a PinP TV screen, and Fig. 7 is an explanatory diagram showing an example of a raster when inserting a child screen. , FIG. 8 is a diagram explaining a conventional method of inserting a sub-screen, FIG. 9 is a block diagram showing a conventional example of a PinP television receiver, and FIG. 110 is a timing diagram of each line signal in @9 diagram. . Description of symbols 26... Matrix circuit, 33... Synchronization separation circuit, 34... Color signal processing circuit, 42...
...Write clock/address generation circuit, 4
3... Readout clock/address generation circuit, 44..., 45... Switching signal generation circuit, 51,
65...Switch circuit, 61...Video signal input terminal, 62...External input terminal, 63
・・・・・・YC separation circuit, 64・・・・・・几GB→
Luminance/color difference conversion circuit, 661, 662, 663...
...A/D converter, 671,672...Memory, 68...Color difference separation circuit, 691,692
, 693...D/A converter. Agent Patent Attorney Akio Namiki Figure 3 Figure 4 Figure 5 V W 6 Figure m1181i! i! /74-LF

Claims (1)

[Claims] 1) A first video signal and a second video signal synchronized with the first video signal.
and a selective capture means that captures either one of the video signals or switches them in a time-division manner and captures both at the same time; It comprises at least two line memories having a capacity sufficient to store one line) and a screen switching means, and depending on whether the screen switching means is switched to either double-sided or two-screen, By controlling the selective capture means and the clock cycles of the write clock and the read clock for the line memory, the tenth double-sided image signal and the second two-sided image signal are displayed on the cathode ray tube display screen. 1. A two-screen television receiver characterized in that a second screen based on a video signal is displayed selectively or simultaneously as two screens in parallel. 2) In the two-screen television receiver according to claim 1, a line interpolation signal is created by controlling write operations and read operations for the at least two line memories, and the line interpolation signal is 2:1. A two-screen television receiver characterized in that the video signal as a television signal based on an interlaced scanning method is converted into a television signal based on a 1:1 non-interlaced scanning method and displayed. 3) In the two-screen television receiver according to claim 1 or 2, the line memory includes a first
A two-screen television receiver characterized in that the first video signal is stored in the first half address, and the second video signal is stored in the second half address. 4) A two-screen television receiver according to claim 3, characterized in that each address start point in the first half and second half of the line memory can be set to any specific value. John receiver.