JP2737557B2 - Dual screen television receiver and dual screen processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual-screen television receiver for displaying two screens simultaneously in the left and right direction, and a two-screen display for simultaneously displaying the two screens in the left and right direction.
The present invention relates to a screen processing circuit.

[0002]

2. Description of the Related Art In a television receiver, there are many demands for a user not only to switch and display a plurality of input images but also to display a plurality of input images on a screen at the same time. There is a so-called two-screen display in which the screens are displayed in the left and right directions simultaneously. FIG. 8 is a diagram showing a conventional two-screen display state. As shown in FIG. 8, an image A or B displayed by 480 normal scanning lines is reduced to 共 に in both the horizontal and vertical directions, and is arranged on the left and right sides to be displayed on two screens. In this case, the pixels of the images A and B are １ ／ each in the horizontal and vertical directions.
Therefore, the number of effective scan lines is halved to 240, and the remaining scan lines need to be blanked.

FIG. 5 shows a conventional configuration for realizing such a two-screen display. In FIG. 5, video signals a and b
Is input to the video distributor 21, which distributes the video signals a and b, respectively, and supplies them to the video synthesizing device 22 and the television receiver (monitor) 23. The video synthesizing device 22 synthesizes the video signals a and b and outputs a synthesized signal c as described later. This video synthesizing device 22 is well known as a special effect device, and is used for business purposes by a broadcast station or a video creator.

Here, a specific configuration and operation of the video synthesizing device 22 will be described with reference to FIGS. 6 and 7. FIG. FIG. 6 is a block diagram showing the overall configuration of the video compositing device 22.
The video signals a and b are stored in buffer memories 221 and 22 respectively.
The pixels are thinned out in the horizontal and vertical directions by に よ っ て by the horizontal / vertical reduction processing circuits 223 and 224 via the line 22, and then written into a predetermined area of the display memory 225.
Then, the combined signal c read out from the display memory 225 collectively becomes a signal displayed on two screens shown in FIG.
FIG. 7 is a block diagram showing a specific configuration of the horizontal / vertical reduction processing circuits 223 and 224. Horizontal / vertical reduction processing circuit 22
3, 224, a horizontal low-pass filter (horizontal LPF) 226, a horizontal pixel thinning circuit 227,
The horizontal LPF 226 comprises a vertical low-pass filter (vertical LPF) 228 and a line thinning circuit 229.
Through the line thinning circuit 229. And
The signal is a signal in which pixels are thinned in half in the horizontal and vertical directions.

[0005] Returning again to FIG.
The composite signal c output as described above is input to the television receiver 23. The television receiver 23 converts the input video signals a and b and the composite signal c into an input selector 231.
The image A is displayed on the display unit 232 by selecting and displaying
Alternatively, the display can be switched between the single screen display of B and the double screen display of the image AB.

[0006]

The video synthesizing device 22 which has been used conventionally, that is, the special effect device, is composed of the buffer memories 221 and 222 and the display memory 22 as described above.
5 requires a large circuit scale and is expensive, so that it has been difficult to apply it to a home television receiver. In addition, the conventional two-screen display is
In the horizontal direction, pixels are decimated by 、, and in the vertical direction, scanning lines are decimated by 、. Therefore, information of the original video signal is reduced by １ ／, resolution and the like are reduced, There is a problem that the image quality is greatly deteriorated. The present invention has been made in view of such a problem, and has a small circuit scale.
It is an object of the present invention to provide a two-screen display television receiver and a two-screen processing circuit that can easily realize two-screen display even with a home-use television receiver and have no deterioration in image quality.

[0007]

According to the present invention, in order to solve the above-mentioned problems of the prior art, (1) an image based on a first video signal and an image based on a second video signal are simultaneously displayed in a left-right parallel manner. A dual-screen television receiver, comprising: a first image memory for storing the first video signal; a second image memory for storing the second video signal;
And the second video signal are written to the first and second image memories, respectively, and the first and second video signals written to the first and second image memories are written in respective scanning lines. A memory control unit for controlling to alternately read at twice the writing speed and output a composite signal, and the first video signal, the second video signal, and the composite signal are input; A selection unit that selects and outputs a signal, a display unit that displays a signal output from the selection unit on a screen, and a system control unit that controls the memory control unit, the selection unit, and the display unit, The system control unit controls the memory control unit so that two images of the composite signal based on the first and second video signals are arranged on the display unit in a predetermined right and left direction, and outputs the composite signal. I will do it When the selection unit is controlled, the display unit is controlled so as to maintain the roundness of a display image by reducing the amplitude of vertical scanning in the display unit. (2) a two-screen processing circuit for simultaneously displaying an image based on a first video signal and an image based on a second video signal in a left-right parallel manner, wherein the first video signal is scanned line by line. A line memory for storing the second video signal in one or more fields, a frame memory for storing one or more fields of the second video signal, a first synchronization separation unit for separating and outputting a first synchronization signal from the first video signal, A second synchronization separation unit that separates and outputs a second synchronization signal from a second video signal, and the first synchronization signal is input, and converts the first video signal according to the first synchronization signal. No. to write to line memory And a second write control unit to which the second synchronization signal is input and writes the second video signal into the frame memory according to the second synchronization signal; The first video signal written to the line memory is input into the line memory at a writing speed of 2 according to the first synchronization signal.
A first read control unit for controlling to output at a double speed and output a first compressed signal; and a second video signal to which the first synchronizing signal is input and written to the frame memory. According to the first synchronization signal, the writing speed is 2
A second readout control unit for controlling to read out at a double speed and to output a second compressed signal, wherein the first compressed signal and the second compressed signal are alternately arranged in each scanning line. It is intended to provide a two-screen processing circuit characterized by being configured to read and combine.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A two-screen television receiver and a two-screen processing circuit according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a two-screen display television receiver of the present invention, FIG. 2 is a block diagram showing a basic configuration of a two-screen processing circuit of the present invention, and FIG. FIG. 4 is a block diagram showing a specific configuration of the circuit, and FIG. 4 is a diagram showing a state of two-screen display by the two-screen display television receiver and the two-screen processing circuit of the present invention.

First, a two-screen television receiver according to the present invention will be described with reference to FIG. The dual-screen television receiver of the present invention includes an image memory 1 for storing a video signal a, an image memory 2 for storing a video signal b, a memory control unit 3 for controlling writing and reading of the image memories 1 and 2, A selection unit 4 for switching between the signal a, the video signal b, and the synthesized signal c output from the image memories 1 and 2 and synthesized, a display unit 5 for displaying a signal d output from the selection unit 4 on a screen, and a memory control unit 3 , A selection unit 4 and a system control unit 6 for controlling the display unit 5.

In FIG. 1, a video signal a is input to an image memory 1, a memory control unit 3, and a selection unit 4, and a video signal b
Is input to the image memory 2, the memory control unit 3, and the selection unit 4. The memory control unit 3 writes the video signal a to the image memory 1 and writes the video signal b to the image memory 2. Then, the memory control unit 3 reads the written video signals a and b from the image memories 1 and 2 alternately in each scanning line at twice the writing speed, and displays the read video signals a and b on one scanning line. The compressed video signals a and b are arranged, and control is performed so as to output a composite signal c in which two screens are displayed in parallel on the left and right.

Further, the system control unit 6 controls the image memory 1
The memory control unit 3 is controlled so that two screens based on the video signals a and b in the synthesized signal c output and synthesized from the two are arranged in a predetermined left-right arrangement or order, and the selection unit 4 and the display unit 5 are controlled. I do. That is, when the system control unit 6 controls the selection unit 4 to output the video signal a or b as the signal d output from the selection unit 4, the system control unit 6 causes the vertical scanning on the display unit 5 to have a normal amplitude. Control. On the other hand, when the system control unit 6 controls the selection unit 4 so as to output the composite signal c as the signal d, the system control unit 6 reduces the amplitude of the vertical scanning on the display unit 5 and maintains the roundness of the display image. The display unit 5 is controlled as described above.

As a result, the two-screen display television receiver of the present invention switches between the video signal a, the video signal b, and the two-screen composite signal c, and is displayed by 480 scanning lines as shown in FIG. It is possible to selectively perform the two-screen display of the image A or B and the image AB arranged by the 480 scanning lines and arranged in the left and right parallel. In the two-screen display according to the present invention, pixels are not thinned out, so that there is no deterioration in image quality. The image memories 1 and 2 used here are simply used for compression on the time axis, and may be simple line memories or field memories.

Next, the configuration and operation of the two-screen processing circuit of the present invention will be described with reference to FIGS. In FIG. 2, a first horizontal compression means 7 compresses the video signal a in the horizontal direction by half and outputs a compressed signal a ', and a second horizontal compression means 8 converts the video signal b in the horizontal direction by one. / 2, and outputs a compressed signal b '. Then, the synthesizing means 9 synthesizes the compressed signal a 'and the compressed signal b' and outputs a synthesized signal c.

FIG. 3 shows a specific embodiment of FIG.
In FIG. 3, a video signal a is input to a line memory 10 and a sync separation unit 11, and a video signal b is input to a frame memory 1
4 and the synchronization separation unit 15. The synchronization signal of the video signal a output from the synchronization separation unit 11 is
The synchronization signal of the video signal b input to the read control unit 13 and the read control unit 17 and output from the sync separation unit 15 is input to the write control unit 16. The synchronization separation unit 1 surrounded by a broken line
1, write control unit 12, read control unit 13, synchronization separation unit 1
5, the write control unit 16 and the read control unit 17
0 and a memory control unit for controlling the frame memory 14.

The first horizontal compression means 7 comprises a line memory 10, a sync separation unit 11, a write control unit 12, and a read control unit 13. That is, the write controller 12 converts the video signal a into the line memory 10 according to the synchronization signal of the video signal a.
The read control unit 13 reads out the written video signal a at twice the writing speed, compresses it by half in the horizontal direction, and outputs it. The second horizontal compression means 8 includes a frame memory 14, a synchronization separation unit 15, a write control unit 16, and a read control unit 1.
7. The write control unit 16 writes the video signal b into the frame memory 14 in accordance with the synchronization signal of the video signal b, and reads out the written video signal b at a rate twice as fast as the writing speed, thereby obtaining one horizontal line. / 2 and output.

Further, the synthesizing means 3 is controlled by controlling the reading of the two memories 10 and 14 described above. That is, the read control unit 13 controls the read timing of the line memory 10 so that the display image A is at a predetermined display position in synchronization with the synchronization signal of the video signal a supplied from the synchronization separation unit 11, and The read control unit 17 controls the read timing of the frame memory 14 so that the display image B is at a predetermined display position in synchronization with the synchronization signal of the video signal a supplied from the synchronization separation unit 11, and The control units 13 and 17 alternately read out the compressed signals a 'and b' output from the memories 10 and 14 in the respective scanning lines, and control to combine them on the same scanning line to output a combined signal c.

Here, the writing control of the frame memory 14 is so-called asynchronous control in which the writing control is synchronized with the video signal b, and the reading control is synchronized with the video signal a. It is well known that an interlace signal requires a memory capacity of one or more fields. The composite signal c obtained by processing as described above
(Not shown) for displaying the vertical scanning amplitude of 1
/ 2 is displayed so as to maintain the roundness of the displayed image,
Thereby, as shown in FIG. 4, it is possible to perform a two-screen display of the images AB arranged on the left and right side, which are displayed by 480 scanning lines. In the two-screen display according to the present invention, pixels are not thinned out, so that there is no deterioration in image quality.

[0018]

As described in detail above, the present invention
The screen display television receiver reads the first and second video signals written in the first and second image memories alternately in each scanning line at twice the writing speed, and outputs the first and second video signals. When the two images based on the second video signal are controlled so as to be arranged in a predetermined left and right direction on the display unit, and when performing two-screen display, the amplitude of the vertical scanning in the display unit is reduced so that the trueness of the display image is reduced. Since the display unit is controlled so as to maintain the circularity, the circuit scale is small, a two-screen display can be easily realized even with a home television receiver, and the thinning processing of pixels in the horizontal and vertical directions is performed. Since there is no display, a high-quality two-screen display is achieved without lowering the resolution.

Further, the two-screen processing circuit of the present invention reads out the first video signal written to the line memory at twice the writing speed in accordance with the first synchronization signal, and reads out the first video signal from the first video signal.
And outputting the second video signal written in the frame memory at twice the writing speed in accordance with the first synchronizing signal and outputting the second compressed signal. Since the compression signal and the second compression signal are alternately read out and combined in each scanning line, the thinning process of the pixels in the horizontal and vertical directions is not performed, so that the resolution is not reduced and the image quality is high. A two-screen display can be performed. Further, since the memory to be used is a line memory or a frame memory, the memory capacity is small,
Further, since no filter is required for the reduction process, the circuit scale is small and the configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a dual screen television receiver according to the present invention.

FIG. 2 is a block diagram showing a basic configuration of a two-screen processing circuit according to the present invention.

FIG. 3 is a block diagram showing a specific configuration of a two-screen processing circuit of the present invention.

FIG. 4 is a two-screen display television receiver and 2 of the present invention.
FIG. 4 is a diagram illustrating a state of two-screen display by a screen processing circuit.

FIG. 5 is a conventional configuration diagram for realizing a two-screen display.

FIG. 6 is a block diagram showing an overall configuration of a video synthesizing device 22 in FIG. 5;

7 is a horizontal and vertical reduction processing circuit 223, 224 in FIG.
FIG. 3 is a block diagram showing a specific configuration of the embodiment.

FIG. 8 is a diagram showing a conventional two-screen display state.

[Description of Signs] 1, 2 image memory 3 memory control unit 4 selection unit 5 display unit 6 system control unit 10 line memory 11, 15 synchronization separation unit 12, 16 write control unit 13, 17 read control unit 14 frame memory

Claims (2)

(57) [Claims] 1. A dual-screen television receiver for simultaneously displaying an image based on a first video signal and an image based on a second video signal in a left-right parallel manner, wherein the first video signal stores the first video signal. An image memory, a second image memory for storing the second video signal, and writing the first and second video signals to the first and second image memories, respectively, A memory control unit that controls the first and second video signals written in the image memory to be alternately read at twice the writing speed in each scanning line and to output a composite signal; A selection unit that receives the first video signal, the second video signal, and the composite signal, selects and outputs these input signals, a display unit that displays a signal output from the selection unit on a screen, The memory control unit; A system control unit that controls the selection unit and the display unit, wherein the system control unit is configured such that two images of the combined signal based on the first and second video signals are displayed on the display unit at predetermined left and right positions. While controlling the memory control unit to be arranged, and controlling the selection unit to output the composite signal, the roundness of the display image is reduced by reducing the amplitude of vertical scanning in the display unit. A dual-screen television receiver, wherein the display unit is controlled to hold the display. 2. A two-screen processing circuit for simultaneously displaying an image based on a first video signal and an image based on a second video signal in a left-right parallel manner, wherein the first video signal is stored in units of scanning lines. A line memory, a frame memory that stores the second video signal in one or more fields, a first synchronization separation unit that separates and outputs a first synchronization signal from the first video signal, A second synchronization separation unit that separates a second synchronization signal from a video signal and outputs the second synchronization signal; and the first synchronization signal is input, and the first video signal is transferred to the line memory according to the first synchronization signal. A first write control unit for writing, a second write control unit to which the second synchronization signal is input, and writes the second video signal to the frame memory according to the second synchronization signal; 1 synchronization signal is input, A first read control unit configured to read out the first video signal written in the line memory at twice the writing speed in accordance with the first synchronization signal and output a first compressed signal; The first synchronization signal is input, the second video signal written to the frame memory is read at twice the writing speed according to the first synchronization signal, and a second compressed signal is output. A second read control unit for controlling the first and second compressed signals, wherein the first and second compressed signals are alternately read and combined in each scanning line, and are combined. circuit.