JPH0630351A - Two screen display television receiver and two-screen processing circuit - Google Patents

Abstract

PURPOSE:To provide the 2-screen display television receiver with a small circuitry without deterioration in picture quality. CONSTITUTION:A memory control section 3 controls video signals a, b so as to be written in picture memories 1, 2. Furthermore, the memory control section 3 reads the video signals a, b from the picture memories 1, 2 at a speed twice the write speed alternately in each scanning line, the video signals a, b compressed are arranged on one scanning line and a synthesis signal (c) is outputted to display two patterns in parallel to the left and right sides. A selection section 4 selects the video signals a, b and the synthesis signal (c) and outputs a signal (d). The signal (d) is displayed on a display section 5. When the synthesis signal (c) is displayed on the display section 5, a system control section 6 controls the display section 5 so as to reduce the amplitude of the vertical scanning.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-screen display television receiver that displays two screens simultaneously in left and right parallel, and a two-screen display television receiver that displays two screens simultaneously in left and right parallel.
The present invention relates to a screen processing circuit.

[0002]

2. Description of the Related Art In a television receiver, there are many demands of a user not only for switching and selectively displaying a plurality of input images but also for simultaneously displaying a plurality of input images on the screen. There is a so-called two-screen display in which the screens are displayed in parallel on the left and right simultaneously. FIG. 8 is a diagram showing a conventional two-screen display state. As shown in FIG. 8, the image A or B normally displayed by 480 scanning lines is reduced to 1/2 in both the horizontal and vertical directions, and arranged in parallel on the left and right sides to be displayed on two screens. In this case, the pixels of the images A and B are ½ in the horizontal and vertical directions, respectively.
Therefore, the effective scanning lines are halved to 240, and the remaining scanning lines need to be blanked.

FIG. 5 shows a conventional configuration for realizing such a two-screen display. In FIG. 5, video signals a and b
Is input to the video distributor 21, and the video distributor 21 distributes the video signals a and b to the video synthesizer 22 and the television receiver (monitor) 23. The video synthesizing device 22 synthesizes the video signals a and b as described later and outputs a synthetic signal c. This video synthesizing device 22 is well known as a special effect device, and is used for commercial purposes by a broadcasting station, a video creator, or the like.

Here, the specific structure and operation of the video synthesizing device 22 will be described with reference to FIGS. 6 and 7. FIG. 6 is a block diagram showing the overall configuration of the video synthesizing device 22.
The video signals a and b are stored in the buffer memories 221 and 221, respectively.
The pixels are thinned out to 1/2 in the horizontal and vertical directions by the horizontal and vertical reduction processing circuits 223 and 224 via 22 and then written in a predetermined area of the display memory 225.
Then, the combined signal c collectively read from the display memory 225 becomes the signal displayed on the two screens shown in FIG.
FIG. 7 is a block diagram showing a specific configuration of the horizontal and vertical reduction processing circuits 223 and 224. Horizontal / vertical reduction processing circuit 22
As shown in FIG. 7, reference numerals 3 and 224 denote horizontal low-pass filters (horizontal LPFs) 226, horizontal pixel thinning circuits 227,
A horizontal low pass filter (vertical LPF) 228 and a line thinning circuit 229 are provided.
~ Processed through the line thinning circuit 229. And
The signal becomes a signal in which pixels are decimated to 1/2 in the horizontal and vertical directions.

Now, returning to FIG. 5 again, the image synthesizer 22
The composite signal c output as described above is input to the television receiver 23. The television receiver 23 inputs the input video signals a and b and the composite signal c into the input selection unit 231.
The image A is displayed on the display unit 232 by selecting and displaying with.
Alternatively, the one-screen display of B and the two-screen display of image AB can be switched and displayed.

[0006]

As described above, the image synthesizing device 22, that is, the special effect device, which has been used conventionally, has the buffer memories 221, 222 and the display memory 22.
Since 5 is required, the circuit scale is large and it is expensive, so that it is difficult to apply it to a home-use television receiver. Also, the two-screen display that has been performed conventionally is
Pixels are thinned to 1/2 in the horizontal direction, and scanning lines are thinned to 1/2 in the vertical direction, so that the information of the original video signal is reduced to 1/4 and the resolution and the like are reduced. There is a problem that the image quality is significantly deteriorated. The present invention has been made in view of such problems, and has a small circuit scale,
It is an object of the present invention to provide a dual-screen display television receiver and a dual-screen processing circuit that can easily realize dual-screen display even on a home-use television receiver and that does not deteriorate image quality.

[0007]

In order to solve the above-mentioned problems of the prior art, the present invention (1) displays the image by the first video signal and the image by the second video signal simultaneously in the left and right directions. A two-screen display television receiver, comprising: a first image memory for storing the first video signal, a second image memory for storing the second video signal, and the first image memory.
And a second video signal are written in the first and second image memories, respectively, and the first and second video signals written in the first and second image memories are written in respective scanning lines. A memory control unit that controls to alternately read out at a speed twice as fast as the writing speed and output a combined signal, the first video signal, the second video signal, and the combined signal are input, and these inputs are input. A selection unit that selects and outputs a signal, a display unit that displays a signal output from the selection unit on a screen, a system control unit that controls the memory control unit, the selection unit, and the display unit, The system control unit controls the memory control unit so that the combined image has two images formed by the first and second video signals in a predetermined left-right arrangement on the display unit, and outputs the combined signal. I will do it When controlling the selection unit, the display unit is controlled so as to maintain the roundness of the display image by reducing the amplitude of vertical scanning in the display unit. (2) A two-screen processing circuit for displaying an image by the first video signal and an image by the second video signal simultaneously in parallel on the left and right sides, wherein the first video signal is a scanning line unit. A line memory that stores the second video signal, a frame memory that stores the second video signal for one field or more, a first sync separation unit that separates and outputs a first sync signal from the first video signal, and A second sync separator that separates and outputs a second sync signal from a second video signal, and the first sync signal is input to the first video signal according to the first sync signal. Write to line memory Write control unit, the second synchronization signal is input, the second write control unit that writes the second video signal in the frame memory according to the second synchronization signal, and the first synchronization A signal is input, and the first video signal written in the line memory has a writing speed of 2 according to the first synchronization signal.
A first read control unit that controls to read at a double speed and output a first compressed signal; and the second video signal that is input to the first synchronization signal and written in the frame memory. The writing speed is 2 according to the first synchronization signal.
A second read control unit for controlling to read at a double speed and output a second compressed signal, wherein the first compressed signal and the second compressed signal are alternately arranged in each scanning line. The present invention provides a two-screen processing circuit characterized by being configured so as to read out and synthesize.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A two-screen display television receiver and a two-screen processing circuit according to the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram showing an embodiment of a two-screen display television receiver of the present invention, FIG. 2 is a block diagram showing a basic configuration of a two-screen processing circuit of the present invention, and FIG. 3 is a two-screen processing of the present invention. FIG. 4 is a block diagram showing a specific configuration of the circuit, and FIG. 4 is a diagram showing a two-screen display state by the two-screen display television receiver and the two-screen processing circuit of the present invention.

First, the dual-screen display television receiver of the present invention will be described with reference to FIG. The two-screen display television receiver of the present invention includes an image memory 1 for storing a video signal a, an image memory 2 for storing a video signal b, a memory control unit 3 for controlling writing and reading of the image memories 1 and 2, and a video. Selector 4 for switching between signal a, video signal b, and combined signal c output from image memories 1 and 2 and combined, display 5 for displaying signal d output from selector 4, and memory controller 3 , A selection unit 4 and a system control unit 6 for controlling the display unit 5.

In FIG. 1, the video signal a is input to the image memory 1, the memory control unit 3, and the selection unit 4, and the video signal b is input.
Is input to the image memory 2, the memory controller 3, and the selector 4. The memory control unit 3 writes the video signal a in the image memory 1 and the video signal b in the image memory 2. Then, the memory control unit 3 alternately reads the written video signals a and b from the image memories 1 and 2 at a speed twice as fast as the writing speed in each scanning line, and reads them on one scanning line. The compressed video signals a and b are arranged and controlled so as to output a combined signal c in which two screens are displayed in parallel on the left and right.

Further, the system control section 6 includes an image memory 1
And 2 to control the memory control unit 3 so that the two screens by the video signals a and b in the combined signal c that are output and combined and are in a predetermined left-right arrangement or order, and also control the selection unit 4 and the display unit 5 To do. That is, when the system control unit 6 controls the selection unit 4 to output the video signal a or b as the signal d output from the selection unit 4, the system control unit 6 causes the vertical scanning in the display unit 5 to have a normal amplitude. Control. On the other hand, when the system control unit 6 controls the selection unit 4 to output the combined signal c as the signal d, the system control unit 6 reduces the vertical scanning amplitude in the display unit 5 and maintains the roundness of the display image. The display unit 5 is controlled as described above.

As a result, the two-screen display television receiver of the present invention switches between the video signal a, the video signal b, and the two-screen composite signal c, and is displayed by 480 scanning lines as shown in FIG. It is possible to selectively perform the two-screen display of the image A or B and the image AB displayed in parallel with each other by 480 scanning lines. In the two-screen display according to the present invention, pixels are not thinned out, so that the image quality does not deteriorate. The image memories 1 and 2 used here are merely used for compression on the time axis, and may be simple line memories or field memories.

Next, the configuration and operation of the two-screen processing circuit of the present invention will be described with reference to FIGS. In FIG. 2, the first horizontal compression means 7 compresses the video signal a to 1/2 in the horizontal direction and outputs a compressed signal a ', and the second horizontal compression means 8 outputs the video signal b to 1 in the horizontal direction. It is compressed to / 2 and a compressed signal b'is output. Then, the synthesizing means 9 synthesizes the compressed signal a'and the compressed signal b ', and outputs a synthesized signal c.

FIG. 3 shows a specific embodiment of FIG.
In FIG. 3, the video signal a is input to the line memory 10 and the sync separation unit 11, and the video signal b is input to the frame memory 1.
4 and the sync separation unit 15. The sync signal of the video signal a output from the sync separator 11 is the write controller 12,
The sync signal of the video signal b input to the read control unit 13 and the read control unit 17 and output from the sync separation unit 15 is input to the write control unit 16. Note that the sync separation unit 1 surrounded by a broken line
1, write control unit 12, read control unit 13, synchronization separation unit 1
5, the write controller 16 and the read controller 17 are line memories 1
0 and the frame memory 14 constitute a memory control unit.

The above-mentioned first horizontal compression means 7 comprises a line memory 10, a sync separator 11, a write controller 12, and a read controller 13. That is, the write controller 12 changes the video signal a to the line memory 10 according to the synchronization signal of the video signal a.
, And the read control unit 13 reads the written video signal a at a speed twice as fast as the write speed, and compresses it in the horizontal direction to 1/2 and outputs it. The second horizontal compression means 8 includes a frame memory 14, a sync separator 15, a write controller 16, and a read controller 1.
It is composed of 7. The writing control unit 16 writes the video signal b in the frame memory 14 in accordance with the synchronization signal of the video signal b, and reads the written video signal b line by line at a speed twice as fast as the writing speed. Compressed to / 2 and output.

Further, the synthesizing means 3 is controlled by reading the two memories 10 and 14 described above. That is, the readout control unit 13 controls the readout timing of the line memory 10 so that the display image A is at a predetermined display position in synchronization with the synchronization signal of the video signal a supplied from the synchronization separation unit 11. The readout control unit 17 controls the readout timing of the frame memory 14 so that the display image B is at a predetermined display position in synchronization with the synchronization signal of the video signal a supplied from the synchronization separation unit 11, and the readout is performed. The control units 13 and 17 alternately read the compressed signals a ′ and b ′ output from the memories 10 and 14 in the respective scanning lines, and control so that they are combined on the same scanning line to output a combined signal c.

Here, since the writing control of the frame memory 14 is so-called asynchronous control in which the writing control is synchronized with the video signal b and the reading control is synchronized with the video signal a, the memory capacity is required for one screen or more. It is well known that a memory capacity of one field or more is required for interlaced signals. Combined signal c obtained by processing in this way
The display unit (not shown) for displaying the
Reduced to / 2 and displayed so that the circularity of the displayed image is maintained,
As a result, as shown in FIG. 4, it is possible to perform two-screen display of the images AB displayed in 480 scanning lines and arranged side by side. In the two-screen display according to the present invention, pixels are not thinned out, so that the image quality does not deteriorate.

[0018]

As described above in detail, according to the present invention,
The screen display television receiver reads the first and second video signals written in the first and second image memories alternately in each scanning line at a speed twice as fast as the writing speed. The two images based on the second video signal are controlled so as to be arranged in a predetermined left-right arrangement on the display unit, and when two-screen display is performed, the amplitude of vertical scanning on the display unit is reduced to reduce the trueness of the display image. Since the display unit is controlled so as to maintain the circularity, the circuit scale is small, and a two-screen display can be easily realized even in a home-use television receiver, and horizontal and vertical pixel thinning processing is performed. Since it does not exist, the resolution is not lowered and a high-quality two-screen display is provided.

Further, in the two-screen processing circuit of the present invention, the first video signal written in the line memory is read at a speed twice as fast as the writing speed in accordance with the first synchronizing signal, and the first video signal is read.
Of the first compressed signal, the second video signal written in the frame memory is read at a speed twice as fast as the writing speed in accordance with the first synchronization signal, and the second compressed signal is output. Since the compressed signal and the second compressed signal are alternately read out in the respective scanning lines and combined, the pixels in the horizontal direction and the vertical direction are not thinned out. It can display two screens, and since the memory used is a line memory or frame memory, the memory capacity is small,
Further, since a filter associated with the reduction processing is unnecessary, the circuit scale is small and the configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dual-screen display television receiver of the present invention.

FIG. 2 is a block diagram showing a basic configuration of a two-screen processing circuit of the present invention.

FIG. 3 is a block diagram showing a specific configuration of a two-screen processing circuit according to the present invention.

FIG. 4 is a dual-screen display television receiver of the present invention and 2;
It is a figure which shows the state of the 2 screen display by a screen processing circuit.

FIG. 5 is a conventional configuration diagram for realizing a two-screen display.

FIG. 6 is a block diagram showing an overall configuration of a video synthesizing device 22 in FIG.

FIG. 7 is a horizontal / vertical reduction processing circuit 223, 224 in FIG.
3 is a block diagram showing a specific configuration of FIG.

FIG. 8 is a diagram showing a conventional two-screen display state.

[Explanation of symbols]

 1, 2 image memory 3 memory control unit 4 selection unit 5 display unit 6 system control unit 10 line memory 11, 15 sync separation unit 12, 16 write control unit 13, 17 read control unit 14 frame memory

Claims (2)

[Claims] 1. A two-screen display television receiver for displaying an image of a first video signal and an image of a second video signal simultaneously in a left-right parallel manner, wherein the first video signal is stored. An image memory, a second image memory for accumulating the second video signal, and writing the first and second video signals in the first and second image memories, respectively, and in addition to the first and second The first and second video signals written in the image memory of the memory are alternately read in each scanning line at a speed twice as fast as the writing speed, and a memory control unit is controlled to output a combined signal. A first video signal, the second video signal, and the composite signal, and a selection unit that selects and outputs these input signals; and a display unit that displays the signal output from the selection unit on a screen. With the memory control unit And a system control unit for controlling the display unit, wherein the system control unit displays two images of the first and second video signals as the combined signal on the display unit in a predetermined left and right direction. When the memory control unit is controlled to be arranged and the selection unit is controlled to output the combined signal, the roundness of the display image is reduced by reducing the amplitude of vertical scanning in the display unit. A two-screen display television receiver, characterized in that the display unit is controlled so as to be held. 2. A two-screen processing circuit for displaying an image of a first video signal and an image of a second video signal simultaneously in parallel in left and right, wherein the first video signal is accumulated in scanning line units. A line memory, a frame memory that stores the second video signal in one or more fields, a first sync separation unit that separates and outputs a first sync signal from the first video signal, and the second A second sync separator that separates and outputs a second sync signal from the video signal; and the first sync signal is input to the line memory according to the first sync signal. A first writing control section for writing; a second writing control section for receiving the second synchronization signal and writing the second video signal in the frame memory according to the second synchronization signal; 1 sync signal is input, A first read control unit for controlling the first video signal written in the line memory to read the first video signal at a speed twice as fast as the write speed in accordance with the first synchronizing signal and output a first compressed signal; The first synchronization signal is input, the second video signal written in the frame memory is read at a speed twice as fast as the writing speed in accordance with the first synchronization signal, and a second compressed signal is output. A second read control section for controlling the first compressed signal and the second compressed signal so as to alternately read and combine the first compressed signal and the second compressed signal in each scanning line. circuit.