JP2685432B2 - Television receiver with two-screen display function - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a television receiver capable of simultaneously displaying a moving image and a still image on one screen. [Background of the Invention] In recent years, in order to effectively utilize a CRT screen in a television receiver, a so-called small screen insertion (PinP) TV, which reduces and projects other TV programs on a part of the original TV screen, is announced. (See Japanese Patent Laid-Open No. 54-98116). The concept of PinP (picture-in-picture) will be briefly described below with reference to FIGS. 12 to 15. FIG. 12 is a conceptual diagram of a PinP screen. 10 is a television receiver, 11 is a cathode ray tube, 12 is a main screen part, and 13 is a small screen part in which another program screen is reduced and inserted. Each small screen has a format that allows independent selection. FIG. 13 shows an example of a small screen insertion method. I is the small screen before reduction, and II is the parent screen into which the small screen is inserted. If the screen reduction ratio is (scanning period after reduction) / (scanning period of original signal) and the screen reduction ratio of the small screen is 1/3 in the vertical and horizontal directions, one out of every three scanning lines starts from the screen of the small screen I. It is extracted, and the horizontal period is time-compressed to 1/3 to synchronize with the main screen and then inserted into the main screen. Scan line-shows a part of the scan line before and after reduction. Fig. 14 shows the state of small screen insertion on the time axis. I is the video signal of the small screen before reduction, and II is the video signal of the parent screen with the small screen inserted. From the image signal I of the small screen, as shown in FIG. 13, one scanning line is extracted for every three lines and written in the analog or digital field memory III,
A two-screen television signal can be obtained by reading out the video signal II of the main screen at the small screen insertion position (thick line portion) using the triple clock. Field memory at this time
III requires A and B2 fields. That is, when reading the memory A, the next field is written in the memory B, and when reading the memory B, the next field is written in the memory A. FIG. 15 shows the configuration of a conventional PinP television. In the figure, 21 is an antenna, 22 is a small screen insertion circuit, 23 is a video processing circuit, 24 is a cathode ray tube, 25 is a main screen tuner, 26 is an IF /
Video detection circuit, 27 is a sync separation circuit, 28 is a small screen tuner, 29 is an IF / video detection circuit, 30 is a sync separation circuit, 31 and 32 are field memories A, B, 33 is a write clock generation circuit, 34
Is a read clock generation circuit. The video signal for the small screen obtained by the tuner 28, the IF / video detection circuit 29 is supplied to, for example, the A field memory 31 by the writing clock generation circuit 33 which is timed by the sync separation circuit 30.
Is written to. During this period, the video signal one field before written in the B field memory 32 is read out by the clock generation circuit 34 whose insertion timing is determined according to the sync signal separated by the sync separation circuit 27 from the video signal of the parent screen.
Read out by the clock of FIG. 1 and inserted into the video signal of the parent screen by the small screen insertion circuit 22. If writing to the field memory for the small screen is stopped here, a still image can be obtained. By the way, the child screen in the conventional PinP television described above has a drawback that the number of scanning lines is 1/3 and the number of samples in the horizontal period is as small as 100, so that the image quality is rough and it is not possible to read fine characters. I got it. [Object of the Invention] The present invention has been conceived in view of the conventional technical circumstances as described above, and therefore the object of the present invention is to provide an image regardless of whether it is a parent screen or a child screen. In addition to high image quality, PinP is a high-definition television with a dual-screen display function that allows you to not only watch other channels' programs at the same time but also watch the same program screen as a video or still image on PinP. It is to provide Jiyoung receiver. [Summary of the Invention] [0012] The above object is to provide a first memory capable of storing an input video signal and horizontally compressing the same, and a first memory capable of storing the input video signal and statically compressing an image horizontally. For the writing speed of the second memory and the first memory,
By controlling the read speed to different speeds, the first
The video signal output from the second memory is horizontally compressed, and the video signal output from the second memory is horizontally compressed by controlling the reading speed to be different from the writing speed of the second memory. And a screen switching unit for switching the video signal output from the first memory and the video signal output from the second memory during a horizontal scanning period to create one screen. It is achieved by providing. According to the present invention, by displaying the video signal compressed by the first memory and the still image signal compressed by the second memory on the same screen by the switching means, two images can be simultaneously displayed in the same size. It is convenient to display and view at. Hereinafter, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the function of a television receiver according to the present invention. In FIG. 1, 101 is a scanning line conversion circuit, 10
Reference numeral 2 is a deflection circuit, and the same parts as those in FIG. 17 are denoted by the same reference numerals. Next, the operation of the embodiment of the present invention will be described. The video signal processed by the antenna 21, the tuner 25, and the IF / video detection circuit 26 is separated by a sync separation circuit 27 to generate a horizontal sync signal having a double repetition frequency. The deflection circuit 102 drives the scanning system by the horizontal synchronizing signal and the vertical synchronizing signal having the doubled frequency. The video signal converted by the scanning line conversion circuit 101 is subjected to various controls (for example, contrast, hue,
After being subjected to saturation, image quality, etc., it is displayed on the cathode ray tube 24. Next, a detailed block diagram of the scanning line conversion circuit 101 is shown in FIG. 2, and its operation will be described. In FIG. 2, 201 is a luminance signal input terminal, 202 is a field memory, 203 is a 1H delay circuit, 204 is a scanning line interpolation circuit, 20
5,208,209, switching circuit, 206,207 are 2H line memory, 210
Is a memory control circuit, 211 is an output terminal, and 212 is a screen switching switch. First, the luminance signal will be described. First, input terminal 20
When the luminance signal is input to 1, the field memory 202 is set to 1
Memorize the video for the field. This field memory can perform a write operation in two modes in which only writing and writing and reading are performed simultaneously, and in the mode in which writing and reading are performed simultaneously, the output signal is delayed by one field from the input signal. Next, the luminance signal input to the input terminal 201 is 1H (1
It is delayed by 1H in the horizontal cycle) delay circuit 203 and input to the interpolation circuit 204. The interpolation circuit 204 creates an interpolation signal 214 from the two signals that are shifted by 1H. This interpolation signal 214 and 1H delay signal 213
Is input to the switching circuit 205 and connected to the line memory in the write (W) state. The operation of this line memory will be described with reference to FIG. 5A. Now the input signal is input like 213 and the interpolation signal is 2
If the input is 14, the line memories 206 and 207 perform writing (W) and reading (R) as shown in the figure. For example, when one line memory is in the write (W) state, the other line memory reads (R) at twice the speed. The switching circuit 208 is connected to the line memory in the read state, and the output signal 215 thereof is converted into the double speed to obtain a high-quality signal. When the switch 212 is connected to the normal screen, the switching circuit 209 is connected to the signal 215 and the signal 215 is output to the output terminal 211. Next, the operation when the switch 212 is connected to the two screens will be described with reference to FIG. 5B. When the switch 212 is connected to two screens, the memory control circuit 210 controls the read speed from the line memory and the read speed from the field memory to 4 times.
Double it. Also, the field memory 202 is in a read-only mode, and no new information is written. For example, the line memories 206 and 207 perform reading in the 1 / 4H period as shown in the figure, and the field memories are similarly read in the 1 / 4H period during the empty period.
Read by period. Signal 215 from the line memory read
The signal from the field memory is switched by the switching circuit 209 every 1 / 4H cycle. As a result, the number of scanning lines is doubled at the output terminal 211, and a moving image can be obtained on the left side of the screen and a still image luminance signal can be obtained on the right side of the screen. Next, the color difference signal will be described. FIG. 3 is a block diagram showing the color difference signal circuit.
Is a color difference signal input terminal, 303 is a multiple circuit, 304 is a color difference field memory, 305 is a separation circuit, 306, 312, 309, 310, 315, 316 are switching circuits, 307, 308, 313, 314 are color difference line memories, 311, 3
Reference numeral 17 is a color difference signal output terminal, 318 is a control circuit, and the same parts as those in FIG. First, when the color difference signals RY and BY are input to the color difference input terminals 301 and 302, the multiplexing circuit 303 multiplexes the two color difference signals. This will be described with reference to FIG. Color difference input terminal
When a signal train as shown in the figure is input to 301 and 302, the multiplexing circuit 303 switches the signal for each pixel, and a signal 323 in which RY and BY signals are alternately multiplexed is obtained at the output. .
The color difference field memory performs the same operation as in the luminance signal. Next, the operation of the line memory will be described with reference to FIG. 6A. Here, the switching circuits 312, 315, 316 and the line memory 31
The reference numeral 3,314 has exactly the same circuit configuration as that of the upper side in the figure, and since the same operation is performed, its description is omitted. When the signal train shown in the figure is input to the color difference signal input terminal 301, the switching circuit 306 is connected to the line memory in the writing (W) state and writing is performed. Line memory 307,30
In step 8, the memory control circuit 318 repeats writing (W) and reading (R) in 2H cycles. Reading is performed in a 1 / 2H cycle. When one of the line memories 307 and 308 is written (W), the other is read (R). In the signal thus read, only the read signal is selected by the switching circuit 309, and at its output, a high quality signal 319 converted to double speed is obtained. The switching circuit 310 is connected to the signal of 319 when the switch 212 is connected to the normal screen, and the signal of 319 is obtained at the output terminal 311. Next, the operation when the switch 212 is connected to the two screens will be described with reference to FIG. 6B. When the switch 212 is connected to two screens, the memory control circuit 318 doubles the read speed from the line memory and the read speed from the field memory as in the case of the luminance signal. Further, the field memory 304 is in the read (R) only mode, and new information is not written. Writing to the line memory (W) is the same as for the normal screen (Fig. 6A), but reading (R) is
Information of 1H is read in a 1 / 4H period, and the field memory 304 is read in a 1 / 4H period during the empty period. Since the color difference signals are multiplexed in the data of the field memory, they are separated into two color difference signals 321 and 322 by the demultiplexing circuit 305 performing an operation opposite to the multiplexing operation. The signal 321 from the field memory and the signal 319 from the line memory are 1/4 by the switching circuit 310.
The color difference signal of the moving image is obtained on the left side of the screen and the still image is obtained on the right side of the screen whose number of scanning lines is doubled at the output terminal 311 which is switched every H period. By operating the above two screens, a moving image on the left side and a still image on the right side are obtained on the CRT as shown in FIG. Further, when the color signal is not necessary for the still image, the multiplex circuit 303, the field memory 304, the separation circuit 30 in FIG.
A black and white still image can be obtained simply by removing 5. Next, another embodiment will be described with reference to FIGS. 7 to 10. First, the luminance signal will be described. FIG. 7 is a block diagram showing the circuit of the luminance signal, and 701 is a switching circuit.
The same parts as those in the figure are denoted by the same reference numerals. If the switch 212 is connected to the normal screen,
Since the operation is the same as in FIG. Here, the operation of the same circuit as that of FIG. When the switch 212 is connected to the two screens, the field memory 202, which has been continuously writing, stops writing (W) and enters the reading (R) mode. Field memory 202
Signal 702 read from and signal 213 passed through the 1H delay circuit
Is input to the switching circuit 701. The switching circuit 702 is connected to the line memory in the write (W) mode. Writing and reading of the line memories 206 and 207 are controlled by the memory control circuit 210 as shown in FIG. The control of the line memory is almost the same as 206 and 207 shown in FIG. 5B, but the signal from the field memory is read out in FIG. 9 during the empty period in FIG. In this way, at the output terminal 212, a luminance signal of two screens of a moving image and a still image whose number of scanning lines has been converted is obtained. Next, the color difference signal will be described. FIG. 8 is a block diagram showing the circuit of the color difference signal.
Is a switching circuit, and the same portions as those in FIG. 3 are denoted by the same reference numerals. The operation of the same circuit as that in FIG. When the switch is connected to the normal screen, the switching circuit
801 and 802 are connected to the inputs from the switches 301 and 302, and other circuits are the same as the operation shown in FIG. 6A. When the switch is connected to two screens, the memory control circuit 31
8 stops the writing (W) of the field memory 304 and changes to the reading (R) mode. The operation of this memory and peripheral circuits will be described with reference to FIG. Line memory 307,308
The operation of is basically the same as the operation shown in FIG. 6B, but, for example, the signal _F from the field memory which is written in the line memory at the same time as the input signal is alternately read in the next read period. Thus, the number of scanning lines is 2 at the output terminal 311.
The signal of 2 screens, a moving image and a still image, can be obtained by doubling. As a result, a moving image on the left side and a still image on the right side are obtained on the CRT as shown in FIG. EFFECTS OF THE INVENTION According to the present invention, there is the convenience that two images can be displayed and viewed at the same time at the same size. Further, since the moving image and the still image can be created by the line memory and the field memory, there is an effect that two screens having a good image quality can be viewed as a practical means.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of a scanning line conversion circuit for luminance signals, and FIG. 3 is scanning for color difference signals. Block diagram showing a specific example of the line conversion circuit, FIG. 4 is a schematic diagram for explaining the method of multiplexing the color difference signals, FIG. 5A is a timing diagram showing the operation of the luminance signal line memory, and FIG. FIG. 6A is a timing diagram showing the operation of the luminance signal line memory, FIG. 6A is a timing diagram showing the operation of the color difference signal line memory, and FIG. 6B is a timing diagram showing the operation of the color difference signal line memory when two screens are displayed. FIG. 7 is a block diagram showing another specific example of the scanning line conversion circuit for the luminance signal, FIG. 8 is a block diagram showing another specific example of the scanning line conversion circuit for the color difference signal, and FIG.
Timing diagram showing the operation of the line memory for the luminance signal at the time of the screen, FIG. 10 is a timing diagram showing the operation of the line memory for the color difference signal at the time of the two screens, and FIG. 11 is a conceptual diagram of the screen of the two-screen television according to the present invention. , Fig. 12 shows PinP
FIG. 13 is a conceptual diagram for explaining the small screen insertion method, and FIG. 15 is a block diagram showing a conventional small screen insertion television. [Short description of symbols] 21 ... Antenna, 23 ... Video signal processing circuit 24 ... CRT, 25 ... tuner 26 ... IF / video detection circuit 27 ... Sync separation circuit, 101 ... Scan line conversion circuit 102 ... Deflection circuit

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References JP-A-57-109477 (JP, A)                 JP-A-8-51575 (JP, A)                 JP-A-8-46889 (JP, A)                 JP-A-8-51576 (JP, A)                 Actual Development Sho 60-17072 (JP, U)

Claims (1)

(57) [Claims] The first memory and the second memory that store the input video signal, and the first memory are output by controlling the reading speed to be different from the writing speed of the first memory. The video signal is compressed in the horizontal direction, and the read speed is controlled to be different from the write speed of the second memory, whereby the video signal output from the second memory is compressed in the horizontal direction and a screen is displayed. When the change-over switch is switched to the two-screen display, the writing of the video signal to the second memory is stopped and the output of the second memory is a still image signal. And a screen switching means for switching between the video signal output from the second memory and the video signal output from the second memory during the horizontal operation period to create one screen. Two-screen display function with a television receiver to be. 2. The television receiver with a dual-screen display function according to claim 1, wherein the second memory is a field memory. 3. The television receiver with a dual-screen display function according to claim 1, wherein the first memory is a line memory. 4. In the television receiver with a dual screen display function according to claim 1, two color difference signals obtained by separating a luminance signal and a color difference signal of an input television signal are multiplexed in a dot-sequential manner. A television receiver with a dual-screen display function, which is characterized by being processed first.