JPH0662339A - Two-screen display television receiver - Google Patents

Abstract

PURPOSE:To arrange two video signals of an NTSC system with the aspect ratio 4:3 on the screen of the high vision receiver of the aspect ratio 16:9 so as to make them same in size and to display them. CONSTITUTION:Data of a first video signal 5 and a second video signal 6 which are converted into a digital are respectively made to be 1/2 by reduction screen processing parts (7 and 8) and the size (horizontal and longitudinal) is reduced to 1/2. Reduced data are respectively written in field memories (11 and 12) and they are read so as to make one image synchronized with the other image. Respective field memory outputs are changed-over in order of the first video signal, a muting signal and the second video signal by a change-over circuit 14 about every half of a scanning line. A memory controller 17 controls the writing and reading of the respective field memories (11 and 12) and the change- over of the change-over circuit 14. The output of the change-over circuit 14 is scanning-line-converted by a scanning line converting part 18 for forming the image with a normal aspect ratio. Then, it is returned to an analog signal by a D/A circuit 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an NTS having an aspect ratio of 4: 3 on a screen such as a high-definition display having an aspect ratio of 16: 9.
The present invention relates to a two-screen display television receiver in which two C-type video signals are displayed side by side in the same size.

[0002]

2. Description of the Related Art Conventionally, so-called picture-in-picture, which displays video signals of the same system as a parent screen and a child screen, has been implemented in many television receivers.

[0003]

SUMMARY OF THE INVENTION The present invention provides a two-screen display television receiver in which two screens of the NTSC system are arranged side by side in the same size on the screen of a high-definition display having an aspect ratio of 16: 9. With the goal.

[0004]

DISCLOSURE OF THE INVENTION The present invention provides a first video signal and a second video signal of the NTSC system having an aspect ratio of 4: 3, wherein the analog first video signal is converted into a digital signal. A first A / D conversion circuit for conversion, means for reducing the data from the first A / D conversion circuit to 1/2 both horizontally and vertically, and a first field memory for storing the reduced data , A second A / D conversion circuit for converting the analog second video signal into a digital signal, and the second A / D conversion circuit.
A means for reducing the data from the D conversion circuit to 1/2 in both the horizontal and vertical directions, a second field memory for storing the reduced data, and a horizontal switching between the first video signal and the second video signal. A mute signal generating circuit for generating a mute signal to be inserted in the boundary portion, a signal from the first field memory, the mute signal, and a signal from the second field memory are sequentially switched under the control of the memory controller. A switching circuit; a memory controller for controlling writing and reading of the first field memory and the second field memory; and switching control of the switching circuit; a means for converting a signal from the switching circuit into a scanning line; A screen having a D / A conversion circuit for converting the converted digital signal to an analog signal and having an aspect ratio of 16: 9. There is provided a two-screen display television receivers be displayed over the video image mute the first and second video signals and the left and right half increments and the boundary portion.

[0005]

The data of each of the first video signal and the second video signal converted into the digital signal is halved and the size (horizontal, vertical) is halved. The reduced data are written in the field memories, respectively, and read so that one image is synchronized with the other image. The output of each field memory is switched by the switching circuit for each half of the scanning lines, and at this time, a mute signal is inserted at the boundary between both screens. The memory controller controls the switching of the switching circuit, as well as the writing and reading of the respective field memories. The output of the switching circuit is scan line converted in order to obtain an image with a normal aspect ratio. After this, it returns to an analog signal.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A dual-screen display television receiver according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of essential parts showing an embodiment of a dual-screen display television receiver according to the present invention. In the figure, reference numeral 1 is an NTSC system and analog first video signal, 2 is the same second video signal, and 3 and 4 are a first A / D conversion circuit for converting an analog signal into a digital signal and a second video signal. A / D conversion circuits 5 and 6 are first digital video signals and second digital video signals, and 7 and 8 are first digital video signals.
Digital video signal 5 and second digital video signal 6
A first reduced screen processing unit and a second reduced screen processing unit for reducing each horizontal and vertical data to 1/2, 9 and 10 are a first reduced video signal and a second reduced video signal, and 11 and 12. Is a first field memory and a second field memory for storing the first reduced video signal 9 and the second reduced video signal 10, respectively, and 13 is a mute signal to be inserted at the horizontal boundary between the two video signals. Generated mute signal generation circuit, 14
Is the first field memory 11 and the second field memory
12 Switching circuit for switching between the signal read from each and the mute signal, 15 horizontal and vertical synchronization signals corresponding to the first video signal 1, 16 horizontal and vertical synchronization signals corresponding to the second video signal 2 A signal, 17 is a memory controller for controlling writing and reading of the first field memory 11 and the second field memory 12, and switching of the switching circuit 14, 18 is a scanning line conversion unit, 19 is a D / A conversion circuit,
20 is a video output signal.

Next, the operation of the present invention will be described. The first video signal 1 and the second video signal 2 are non-interlaced signals that do not include a synchronization signal. Each of these video signals is supplied to the first A / D conversion circuit 3 and the second A / D conversion circuit 3.
It is converted into a first digital video signal 5 and a second digital video signal 6 by the D conversion circuit 4, and is input to the first reduced screen processing section 7 and the second reduced screen processing section 8. The first reduced screen processing unit 7 and the second reduced screen processing unit 8 reduce the data of the first digital video signal 5 and the second digital video signal 6 to 1/2, but the reason is that This is because images of the same size are made into two screens. Then, as a method, in the vertical direction, thinning is performed for each scanning line, and in the horizontal direction, every other pixel is thinned. These data may be interpolated by each reduced screen processing unit.
The first reduced video signal 9 and the second reduced video signal 9 thus reduced
The reduced video signal 10 of the first field memory 11 and the second field memory 12 is controlled by the memory controller 17.
Written to each. Here, one field is one frame on the screen. The signals written in the respective field memories are sequentially read by the memory controller 17, and at that time, the signals are read so as to synchronize one image (horizontal / vertical) with the other image. For example, the second video is synchronized with the first video as a reference. The signal thus read out enters the switching circuit 14. The switching timing of the switching circuit 14 is approximately 1/2 scanning point of each scanning line.
The mute signal generating circuit 13 is switched during a fixed width period before and after the 1/2 scanning point. For example, when arranging the first video on the left side of the screen and the second video on the right side, the first video side is selected in the first half of scanning, the mute signal is then selected, and the second video side is selected in the second half. To do. This is repeated for each scan line.
In the mute period, a range (several μs) in which the video component is not much lost is appropriate in relation to the horizontal frequency. The memory controller determines this switching timing.
The switching signal 21 is output from 17. Then, the switching signal 21 is generated with reference to the first synchronizing signal and the second synchronizing signal.

[0008] As described above, one image is read in synchronization with the other image, and switching is performed in the first half and second half of scanning, and a mute signal is inserted at the boundary portion at the time of switching to synchronize with each other. One video signal composed of two images is completed. However, this signal is
If it is projected horizontally on a 16: 9 display, it will become a horizontally elongated image (horizontally elongated image). Aspect ratio 4
When the original signal of pair 3 is horizontally and vertically scanned at the ratio of 16: 9,
This is because the horizontal direction is stretched to 4/3 times the original signal even if both vertical directions are combined. Therefore, in order to obtain an image with the correct aspect ratio (for example, a circle is a true circle), the vertical direction should be 4
A correction to stretch it by 3 times is required. The scanning line conversion unit 18 corrects this. That is, the scanning line conversion unit 18 increases the number of scanning lines of the signal from the switching circuit 14 by 4/3. As a result, a horizontally long image becomes an image with a normal aspect ratio, but since unnecessary scanning lines due to increase are included, these are cut as image blanking. The scan line converted signal is returned to analog, and the video output signal 20 for two screens is completed. FIG. 2 shows a conceptual diagram when such a video signal is displayed. In the figure, the dotted portions in the vertical direction of the first and second image boundary portions are the image mute period, and the dotted portions at the top and bottom of the screen are the non-projected portions (blanking).

[0009]

As described above, according to the present invention, by utilizing the characteristics of the high-definition horizontally long screen having the aspect ratio of 16: 9, two NTSC system images having the same aspect ratio and having the same aspect ratio are provided. Since the display is full, it is possible to obtain a function having a characteristic different from that of the conventional parent-child screen composed of large and small screens. Further, since the mute period is provided at the boundary between the two screens, the division of the two screens becomes clear.

[Brief description of drawings]

FIG. 1 is a main block diagram showing an embodiment of a dual-screen display television receiver according to the present invention.

FIG. 2 is a conceptual diagram when two screens are displayed.

[Explanation of symbols]

 1 1st video signal 2 2nd video signal 3 1st A / D conversion circuit 4 2nd A / D conversion circuit 7 1st reduction screen processing part 8 2nd reduction screen processing part 11 1st Field memory 12 Second field memory 13 Mute signal generation circuit 14 Switching circuit 17 Memory controller 18 Scan line conversion unit 19 D / A conversion circuit

Claims (1)

[Claims] 1. An NTSC first video signal and a second video signal having an aspect ratio of 4: 3, wherein the analog first video signal
First A / D conversion circuit for converting the video signal of 1 to a digital signal, means for reducing the data from the first A / D conversion circuit to 1/2 both horizontally and vertically, and storing the reduced data And a second field memory for converting the analog second video signal into a digital signal.
A D conversion circuit, means for reducing the data from the second A / D conversion circuit to 1/2 both horizontally and vertically, a second field memory for storing the reduced data, and the first
Signal generating circuit for generating a mute signal to be inserted at the boundary between the horizontal switching between the second video signal and the second video signal, a signal from the first field memory, the mute signal, and the second field memory A switching circuit that sequentially switches the signal from the memory controller based on the control of the memory controller; a memory controller that controls writing and reading of the first field memory and the second field memory and switching control of the switching circuit;
Means for scanning line conversion of signals from the switching circuit, and D / for converting scanning line converted digital signals to analog signals
An A conversion circuit is provided, and the first video signal and the second video signal are displayed on the left and right halves on a screen having an aspect ratio of 16: 9, and video is muted at the boundary between them. A dual-screen display television receiver characterized in that