JPH05328245A - Two-pattern display television receiver - Google Patents

Two-pattern display television receiver

Info

Publication number
JPH05328245A
JPH05328245A JP4128663A JP12866392A JPH05328245A JP H05328245 A JPH05328245 A JP H05328245A JP 4128663 A JP4128663 A JP 4128663A JP 12866392 A JP12866392 A JP 12866392A JP H05328245 A JPH05328245 A JP H05328245A
Authority
JP
Japan
Prior art keywords
signal
video signal
video
reduced
field memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4128663A
Other languages
Japanese (ja)
Inventor
Akihiko Suzuki
彰彦 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP4128663A priority Critical patent/JPH05328245A/en
Publication of JPH05328245A publication Critical patent/JPH05328245A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To display two video signals of the NTSC system whose aspect ratio is 4:3, while being arranged side by side horizontally with the same size onto a screen of a High Vision receiver whose aspect ratio is 16:9. CONSTITUTION:A horizontal component of a 1st video signal 5 and a 2nd video signal 6 converted into digital signals is reduced to 1/2 and a vertical component of the signals is reduced to 2/3 by reduction pattern processing sections 7, 8. The reduced data are respectively written in field memories 11, 12, and they are read so that the other video image is synchronously with one video image. The output of each field memory is selected by a changeover circuit 13 for each half of a scanning line. A memory controller 16 applies write and read control of the field memories 11, 12 and changeover control of the changeover circuit 13. An output of the changeover circuit 13 is converted into an analog signal by a D/A converter circuit 17.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、縦横比16対9のハイビ
ジョンディスプレイ等の画面上に縦横比4対3のNTS
C方式の2つの映像信号を左右同じ大きさに並べて表示
するようにした2画面表示テレビ受信機に関する。
BACKGROUND OF THE INVENTION The present invention relates to an NTS having an aspect ratio of 4: 3 on a screen such as a high-definition display having an aspect ratio of 16: 9.
The present invention relates to a two-screen display television receiver in which two C-type video signals are displayed side by side in the same size.

【0002】[0002]

【従来の技術】従来、同一方式の映像信号を親画面と子
画面として表示する、いわゆるピクチャ・イン・ピクチ
ャは多くのテレビ受信機で実施されている。
2. Description of the Related Art Conventionally, so-called picture-in-picture, in which video signals of the same system are displayed as a parent screen and a child screen, has been implemented in many television receivers.

【0003】[0003]

【発明が解決しようとする課題】本発明は、NTSC方
式の2画面を縦横比16対9のハイビジョンディスプレイ
の画面上に同サイズで表示するようにした2画面表示テ
レビ受信機を提供することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a two-screen display television receiver in which two NTSC screens are displayed in the same size on the screen of an HDTV display having an aspect ratio of 16: 9. To aim.

【0004】[0004]

【課題を解決するための手段】本発明は、縦横比が4対
3のNTSC方式の第1の映像信号と第2の映像信号で
あって、アナログの該第1の映像信号をディジタル信号
に変換する第1のA/D変換回路と、該第1のA/D変
換回路よりのデータを水平成分については1/2に縮小
し、垂直成分については2/3に縮小する手段と、縮小
したデータを記憶する第1のフィールドメモリと、アナ
ログの該第2の映像信号をディジタル信号に変換する第
2のA/D変換回路と、該第2のA/D変換回路よりの
データを水平成分については1/2に縮小し、垂直成分
については2/3に縮小する手段と、縮小したデータを
記憶する第2のフィールドメモリと、該第1のフィール
ドメモリよりの信号と該第2のフィールドメモリよりの
信号とをメモリコントローラの制御に基づいて切り換わ
る切換回路と、該第1のフィールドメモリと該第2のフ
ィールドメモリそれぞれへの前記縮小したデータの書き
込み制御と、第1の映像または第2の映像のいづれか一
方の同期を基準にして他方の映像を該一方の映像に同期
するように読み出す制御と、該読み出し制御とタイミン
グを合わせた切換回路の切換制御とをなすメモリコント
ローラと、切換回路よりの信号をディジタルの信号から
アナログ信号に変換するD/A変換回路とを具備し、縦
横比が16対9の画面上に該第1の映像信号と該第2の映
像信号とを左右半分づつ同じ大きさで表示するようにし
た2画面表示テレビ受信機を提供するものである。
According to the present invention, there are provided a first video signal and a second video signal of an NTSC system having an aspect ratio of 4: 3, wherein the analog first video signal is converted into a digital signal. A first A / D conversion circuit for conversion, means for reducing the data from the first A / D conversion circuit to 1/2 for the horizontal component and 2/3 for the vertical component, and reduction The first field memory for storing the stored data, the second A / D conversion circuit for converting the analog second video signal into a digital signal, and the data from the second A / D conversion circuit Means for reducing the components to 1/2 and vertical components to 2/3, a second field memory for storing the reduced data, a signal from the first field memory and the second field memory. The signal from the field memory and the memory A switching circuit that switches based on the control of the tracker, a control for writing the reduced data to the first field memory and the second field memory, and either one of the first image and the second image. A memory controller that controls reading of the other image so that the other image is synchronized with the one image on the basis of synchronization, and a switching control of a switching circuit that matches the timing of the reading control, and a signal from the switching circuit that is a digital signal. A D / A conversion circuit for converting a signal to an analog signal is provided, and the first video signal and the second video signal are displayed in the same size in left and right halves on a screen having an aspect ratio of 16: 9. The present invention provides a dual screen display television receiver.

【0005】[0005]

【作用】ディジタル信号に変換した第1の映像信号と第
2の映像信号それぞれのデータを、水平成分については
1/2に縮小し、垂直成分については2/3に縮小す
る。縮小したデータは対応するフィールドメモリにそれ
ぞれ書き込まれ、そして一方の映像に他方の映像が同期
するように読み出される。各フィールドメモリ出力は切
換回路で走査線半分ごとに切り換えられる。メモリコン
トローラは該各フィールドメモリの書き込みと読み出し
制御および該切換回路の切換制御をする。切換回路の出
力は、D/A変換回路でアナログ信号へ戻す。
The data of each of the first video signal and the second video signal converted into the digital signal is reduced to 1/2 for the horizontal component and 2/3 for the vertical component. The reduced data are respectively written in the corresponding field memories, and then read so that one image is synchronized with the other image. The output of each field memory is switched by the switching circuit for each half scanning line. The memory controller controls writing and reading of each field memory and switching control of the switching circuit. The output of the switching circuit is returned to an analog signal by the D / A conversion circuit.

【0006】[0006]

【実施例】以下、図面に基づいて本発明による2画面表
示テレビ受信機を説明する。図1は本発明による2画面
表示テレビ受信機の一実施例を示す要部ブロック図であ
る。図において、1はアナログの第1の映像信号、2は
同・第2の映像信号、3と4はアナログ信号をディジタ
ル信号に変換する第1のA/D変換回路と第2のA/D
変換回路、5と6は第1のディジタル映像信号と第2の
ディジタル映像信号、7と8は第1のディジタル映像信
号5と第2のディジタル映像信号6それぞれのデータを
水平成分については1/2に縮小し、垂直成分について
は2/3に縮小する第1の縮小画面処理部と第2の縮小
画面処理部、9と10は第1の縮小映像信号と第2の縮小
映像信号、11と12は第1の縮小映像信号9と第2の縮小
映像信号10それぞれを記憶する第1のフィールドメモリ
と第2のフィールドメモリ、13は第1のフィールドメモ
リ11と第2のフィールドメモリ12それぞれから読み出さ
れた信号を切り換える切換回路、14は第1の映像信号1
に対応する水平および垂直の同期信号、15は第2の映像
信号2に対応する水平および垂直の同期信号、16は第1
のフィールドメモリ11と第2のフィールドメモリ12への
データ書き込みと読み出しおよび切換回路13の切り換え
の各制御をするメモリコントローラ、17はD/A変換回
路、18は映像出力信号、19は切換信号である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A dual-screen display television receiver according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of essential parts showing an embodiment of a dual-screen display television receiver according to the present invention. In the figure, 1 is an analog first video signal, 2 is the same / second video signal, and 3 and 4 are a first A / D converter circuit and a second A / D converter for converting an analog signal into a digital signal.
The conversion circuits 5 and 6 are the first digital video signal and the second digital video signal, and 7 and 8 are the data of the first digital video signal 5 and the second digital video signal 6 for the horizontal component, respectively. A first reduced screen processing unit and a second reduced screen processing unit that reduce the image size to 2 and to reduce the vertical component to 2/3, 9 and 10 denote a first reduced image signal and a second reduced image signal, 11 And 12 are the first field memory and the second field memory for storing the first reduced video signal 9 and the second reduced video signal 10, respectively, and 13 is the first field memory 11 and the second field memory 12, respectively. A switching circuit for switching the signal read from the, 14 is the first video signal 1
Horizontal and vertical sync signals corresponding to the second video signal 2, 15 horizontal and vertical sync signals corresponding to the second video signal 2, and 16 the first
A memory controller for controlling writing and reading of data to and from the field memory 11 and the second field memory 12 and switching of the switching circuit 13, 17 is a D / A conversion circuit, 18 is a video output signal, and 19 is a switching signal. is there.

【0007】次に、本発明の動作について説明する。第
1の映像信号1および第2の映像信号2は同期信号は含
まれていない且つノンインターレースの信号である。こ
れら各映像信号は第1のA/D変換回路3と第2のA/
D変換回路4とで第1のディジタル映像信号5と第2の
ディジタル映像信号6に変換され、第1の縮小画面処理
部7と第2の縮小画面処理部8とへ入力する。第1の縮
小画面処理部7と第2の縮小画面処理部8で、第1のデ
ィジタル映像信号5と第2のディジタル映像信号6の各
データを水平成分については1/2に縮小し、垂直成分
については2/3に縮小するが、その理由は、最終的に
同サイズの画像を2画面にするからである。そして、縮
小する方法として、垂直方向については走査線3本に1
本を間引き、水平方向については画素データを1つおき
に間引く。間引く比率が水平と垂直とで相違するのは以
下の理由からである。即ち、4対3の信号を縦横比16対
9のディスプレイ上に縦横一杯に映出すると水平方向に
伸びた映像(横長の映像)になる。垂直方向を双方一致
させた場合、水平方向は16/12倍、つまり原信号の4/
3倍に引き伸ばされる。このことは縮小画面についても
同様であり、例えば、水平および垂直双方のデータをそ
れぞれ1/2に縮小した場合には各縮小画像の水平方向
は4/3倍に引き伸ばされ、横長の映像になる。従っ
て、水平および垂直双方のデータをそれぞれ1/2に縮
小する場合には後段回路で走査線変換をして走査線の数
を4/3倍に増加し、垂直振幅を引き伸ばす補正が必要
となる。この走査線変換により水平と垂直とが正規比率
になり、例えば円が真の円になる。以上から、垂直デー
タの間引きを当初から2/3〔(1/2)×(4/
3)〕にし、水平データは1/2に縮小すれば上記のよ
うな走査線変換することなく正常な縮小画面とすること
ができる。これが、水平と垂直とで間引く比率が相違す
る理由である。
Next, the operation of the present invention will be described. The first video signal 1 and the second video signal 2 are non-interlaced signals that do not include a synchronization signal. Each of these video signals includes a first A / D conversion circuit 3 and a second A / D conversion circuit 3.
It is converted into a first digital video signal 5 and a second digital video signal 6 by the D conversion circuit 4, and is input to the first reduced screen processing section 7 and the second reduced screen processing section 8. In the first reduced screen processing unit 7 and the second reduced screen processing unit 8, each data of the first digital video signal 5 and the second digital video signal 6 is reduced to 1/2 in the horizontal component, and vertically reduced. The components are reduced to 2/3 because the image of the same size is finally made into two screens. Then, as a method of reduction, one in three scanning lines is used in the vertical direction.
Books are thinned out, and every other pixel data in the horizontal direction is thinned out. The thinning ratio differs between horizontal and vertical for the following reasons. That is, when a 4: 3 signal is displayed in a vertical / horizontal manner on a display having an aspect ratio of 16/9, a horizontally elongated image (horizontally elongated image) is obtained. When both vertical directions are matched, the horizontal direction is 16/12 times, that is, 4 / of the original signal.
It is stretched 3 times. This also applies to the reduced screen. For example, when both horizontal and vertical data are reduced to 1/2, the horizontal direction of each reduced image is stretched by 4/3 times to form a horizontally long image. .. Therefore, in order to reduce both the horizontal and vertical data to 1/2 respectively, it is necessary to perform a scan line conversion in the latter stage circuit to increase the number of scan lines to 4/3 times and to extend the vertical amplitude. .. By this scanning line conversion, the horizontal and vertical become a normal ratio, and for example, a circle becomes a true circle. From the above, vertical data decimation from the beginning is 2/3 [(1/2) × (4 /
3)] and the horizontal data is reduced to 1/2, it is possible to obtain a normal reduced screen without the above-mentioned scanning line conversion. This is the reason why the thinning ratio differs between horizontal and vertical.

【0008】このようにして縮小した第1の縮小映像信
号9と第2の縮小映像信号10はメモリコントローラ16の
制御により第1のフィールドメモリ11と第2のフィール
ドメモリ12それぞれへ書き込まれる。ここで、1フィー
ルドが画面1コマである。各フィールドメモリに書き込
まれた信号は、メモリコントローラ16により順次読み出
すが、その際、一方の映像の同期(水平/垂直)に他方
の映像を同期させるように読み出す。例えば、第1の映
像を基準にして第2の映像をこれに同期させる。尚、こ
の逆でもよい。このようにして読み出された信号は切換
回路13へ入る。該切換回路13の切り換えタイミングは各
走査線の1/2走査点である。例えば、走査の前半で第
1の映像側を選択し後半で第2の映像側を選択し、これ
を各走査線で繰り返す。この切り換えタイミングを定め
るものがメモリコントローラ16より出力する切換信号19
である。そして、この切換信号19は第1の同期信号と第
2の同期信号とを基準にしてつくられる。
The first reduced video signal 9 and the second reduced video signal 10 reduced in this way are written into the first field memory 11 and the second field memory 12 under the control of the memory controller 16. Here, one field is one frame of the screen. The signals written in the respective field memories are sequentially read by the memory controller 16, and at that time, the signals are read so as to synchronize one image with the other image (horizontal / vertical). For example, the second video is synchronized with the first video as a reference. The reverse is also possible. The signal thus read out enters the switching circuit 13. The switching timing of the switching circuit 13 is 1/2 scanning point of each scanning line. For example, the first video side is selected in the first half of scanning, the second video side is selected in the latter half, and this is repeated for each scanning line. The switching signal 19 output from the memory controller 16 determines the switching timing.
Is. Then, the switching signal 19 is generated with reference to the first synchronizing signal and the second synchronizing signal.

【0009】以上のように、一方の映像に他方の映像を
同期させて読み出し、さらに走査の前半後半で切り換え
ることにより相互に同期した2つの画像からなる1つの
映像信号が成立する。このようにして成立した1つの映
像信号はディジタルからアナログに戻され、2画面の映
像出力信号19が完成する。かかる映像信号を映出した場
合の概念図を図2に示す。尚、図中の斜線部分は非映出
部分(ブランキング)である。
As described above, by reading one image in synchronization with the other image and further switching in the first half and second half of scanning, one image signal composed of two images synchronized with each other is established. One video signal thus established is returned from digital to analog, and the video output signal 19 for two screens is completed. FIG. 2 shows a conceptual diagram when such a video signal is displayed. The shaded area in the figure is the non-projected area (blanking).

【0010】[0010]

【発明の効果】以上説明したように本発明によれば、縦
横比16対9というハイビジョンの横長画面の特徴を生か
して縦横比4対3のNTSC方式の映像を同じ大きさで
2画面且つ画面一杯に表示するので、従来の大小画面か
らなる親子画面とは異なった特徴となる機能を得ること
ができる。また、走査線変換という手段を要しないとい
う点も大きな特徴である。
As described above, according to the present invention, by utilizing the feature of the high-definition horizontally long screen having the aspect ratio of 16: 9, the NTSC system image having the aspect ratio of 4: 3 has two screens and the same size. Since the display is full, it is possible to obtain a function having a characteristic different from that of the conventional parent-child screen composed of large and small screens. Another major feature is that scanning line conversion is not required.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による2画面表示テレビ受信機の一実施
例を示す要部ブロック図である。
FIG. 1 is a main block diagram showing an embodiment of a dual-screen display television receiver according to the present invention.

【図2】2画面表示したときの概念図である。FIG. 2 is a conceptual diagram when two screens are displayed.

【符号の説明】[Explanation of symbols]

1 第1の映像信号 2 第2の映像信号 3 第1のA/D変換回路 4 第2のA/D変換回路 7 第1の縮小画面処理部 8 第2の縮小画面処理部 11 第1のフィールドメモリ 12 第2のフィールドメモリ 13 切換回路 16 メモリコントローラ 17 D/A変換回路 1 1st video signal 2 2nd video signal 3 1st A / D conversion circuit 4 2nd A / D conversion circuit 7 1st reduction screen processing part 8 2nd reduction screen processing part 11 1st Field memory 12 Second field memory 13 Switching circuit 16 Memory controller 17 D / A conversion circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 縦横比が4対3のNTSC方式の第1の
映像信号と第2の映像信号であって、アナログの該第1
の映像信号をディジタル信号に変換する第1のA/D変
換回路と、該第1のA/D変換回路よりのデータを水平
成分については1/2に縮小し、垂直成分については2
/3に縮小する手段と、縮小したデータを記憶する第1
のフィールドメモリと、アナログの該第2の映像信号を
ディジタル信号に変換する第2のA/D変換回路と、該
第2のA/D変換回路よりのデータを水平成分について
は1/2に縮小し、垂直成分については2/3に縮小す
る手段と、縮小したデータを記憶する第2のフィールド
メモリと、該第1のフィールドメモリよりの信号と該第
2のフィールドメモリよりの信号とをメモリコントロー
ラの制御に基づいて切り換わる切換回路と、該第1のフ
ィールドメモリと該第2のフィールドメモリそれぞれへ
の前記縮小したデータの書き込み制御と、第1の映像ま
たは第2の映像のいづれか一方の同期を基準にして他方
の映像を該一方の映像に同期するように読み出す制御
と、該読み出し制御とタイミングを合わせた切換回路の
切換制御とをなすメモリコントローラと、切換回路より
の信号をディジタルの信号からアナログ信号に変換する
D/A変換回路とを具備し、縦横比が16対9の画面上に
該第1の映像信号と該第2の映像信号とを左右半分づつ
同じ大きさで表示するようにしたことを特徴とする2画
面表示テレビ受信機。
1. An NTSC first video signal and a second video signal having an aspect ratio of 4: 3, wherein the analog first video signal
Of the first A / D conversion circuit for converting the video signal of No. 2 into a digital signal, and the data from the first A / D conversion circuit are reduced to 1/2 for the horizontal component and 2 for the vertical component.
Means for reducing to ⅓ and storing the reduced data first
Field memory, a second A / D conversion circuit for converting the analog second video signal into a digital signal, and the data from the second A / D conversion circuit are halved for horizontal components. Means for reducing and reducing the vertical component to 2/3, a second field memory for storing the reduced data, a signal from the first field memory and a signal from the second field memory. A switching circuit that switches under the control of a memory controller, a control for writing the reduced data in each of the first field memory and the second field memory, and either one of a first image and a second image. Based on the synchronization of the other video, a control for reading the other video so as to be synchronized with the one video, and a switching control of a switching circuit in timing with the read control. A re-controller and a D / A conversion circuit for converting a signal from the switching circuit from a digital signal to an analog signal are provided, and the first video signal and the second video signal are displayed on a screen having an aspect ratio of 16: 9. A dual-screen display television receiver characterized in that the video signal and the left and right halves are displayed in the same size.
JP4128663A 1992-05-21 1992-05-21 Two-pattern display television receiver Pending JPH05328245A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4128663A JPH05328245A (en) 1992-05-21 1992-05-21 Two-pattern display television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4128663A JPH05328245A (en) 1992-05-21 1992-05-21 Two-pattern display television receiver

Publications (1)

Publication Number Publication Date
JPH05328245A true JPH05328245A (en) 1993-12-10

Family

ID=14990372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4128663A Pending JPH05328245A (en) 1992-05-21 1992-05-21 Two-pattern display television receiver

Country Status (1)

Country Link
JP (1) JPH05328245A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504535A (en) * 1993-12-24 1996-04-02 Kabushiki Kaisha Toshiba Television receiver for displaying two pictures of similar or different aspect ratios simultaneously

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504535A (en) * 1993-12-24 1996-04-02 Kabushiki Kaisha Toshiba Television receiver for displaying two pictures of similar or different aspect ratios simultaneously

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