JPH06311426A - Image processor - Google Patents

Abstract

PURPOSE:To provide an image processor which is capable of improving the resolution at the time of magnifying an image by a simple configuration. CONSTITUTION:This device is provided with an imaging device 1, a buffer 2, an A/D converter 3, a vertical magnifying circuit 4 magnifying the signal transmitted from the A/D converter 3 in the vertical direction, a horizontal magnifying circuit 5 magnifying the signal transmitted from the vertical magnifying circuit 4 in the horizontal direction, a D/A converter 6 and a buffer 7. Further, the processor is composed of a synchronizing signal generation circuit 8 generating reference timing signals for inputting in each device and circuit except the buffers 2 and 7 and a controller 9 controlling the output of the synchronizing signal generation circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video data enlargement processing apparatus.

[0002]

2. Description of the Related Art In a conventional video apparatus, a method has been devised in which image data is stored in an image memory, the image data is repeatedly read, and the image is enlarged.

[0003]

In the conventional circuit configuration in which the same image data is repeatedly read a plurality of times and the expansion processing is performed, the same data is continuously displayed, resulting in a reduction in resolution. There was a problem.

In view of the above problems of the prior art, it is an object of the present invention to provide an image processing apparatus capable of improving the resolution when enlarging an image with a simple circuit configuration.

[0005]

In order to achieve the above object, an image processing apparatus according to the present invention provides an image pickup means for picking up an optical image and a video signal output from the image pickup means which is composed of a plurality of memories. First image storage means for storing and reading out two adjacent lines at the same time, first image calculation means for adding data of two lines output from the first image storage means, and the first image storage A first output switching means for switching the output of the means and the output of the first image calculation means in a predetermined order, and a second output for storing the output of the first output switching means and reading out two adjacent pixels at the same time. The image storage means, the second image calculation means for adding the two pixel data output from the second image storage means, and the outputs of the second image storage means and the second image calculation means are predetermined. Switching in the order of And an output switching means.

[0006]

Therefore, it is possible to prevent the resolution from being lowered during the image enlargement process only by providing the simple circuit as described above.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS. FIG. 1 is a basic configuration diagram of an image processing apparatus according to the present invention, FIG. 2 is a configuration diagram of a vertical expansion circuit in the image processing apparatus, FIG. 3 is an explanatory diagram showing operation timing of the vertical expansion circuit, and FIG. 4 is the image. FIG. 5 is a configuration diagram of a horizontal expansion circuit in the processing device, and FIG. 5 is an explanatory diagram showing operation timing of the horizontal expansion circuit.

In FIG. 1, reference numeral 1 denotes an image pickup element for performing image pickup by photoelectrically converting input light, 2 a buffer, and 3 a video signal sent from the image pickup element 1 via the buffer 2 from an analog signal to a digital signal. An A / D converter for conversion, 4 is a vertical expansion circuit for vertically expanding the signal sent from the A / D converter 3, and 5 is a horizontal expansion circuit for horizontally expanding the signal sent from the vertical expansion circuit 4, 6 is a D / A converter for converting the signal sent from the horizontal expansion circuit 5 from a digital signal to an analog signal,
Reference numeral 7 is a buffer, 8 is a sync signal generating circuit for generating a reference timing signal, and 9 is a controller. The sync signal output from the sync signal generation circuit 8 is input to the A / D converter 4 and the D / A converter 6 via the controller 9 and is used as a clock signal for driving these. Further, the controller 9 is the synchronization signal generation circuit 8
Is configured so that the image pickup device 1 can be driven and the operation control of the vertical expansion circuit 4 and the horizontal expansion circuit 5 can be performed in synchronization with the synchronization signal output by. The video signal output from the buffer 7 is input to a television monitor (not shown) so that the video signal can be observed as an image, and the sync signal output from the sync signal generation circuit 8 is also the video signal. Along with this, it is input to the television monitor and is configured to be observed as an image.

Next, the structure of the vertical expansion circuit 4 will be described with reference to FIG. The video signal digitally converted by the A / D converter 3 is stored in the frame memory 10 in the vertical expansion circuit 4.
Sent to and stored in. Further, the output signal from the frame memory 10 is sent to and stored in the line memory 11.
Therefore, the data for two lines can be obtained by reading the video signals stored in the frame memory 10 and the line memory 11, respectively. Output signals from the frame memory 10 and the line memory 11 are added by the adder 12. On the other hand, the output signal from the frame memory 10 is also sent to the vertical selector 13 and, together with the output signal sent from the adder 12, one of the two signals is selected in the vertical selector 13 to the horizontal expansion circuit 5. It is configured to be delivered.

Next, the configuration of the horizontal expansion circuit 5 will be described with reference to FIG. The output signal from the vertical selector 13 in the vertical expansion circuit 4 is the line memory 14, 1 in the horizontal expansion circuit 5.
5 are sent to and stored in the memory. Line memories 14, 15
Are configured so that mutually different pixel data can be output, and the two output signals are sent to the P / S converter 17 and also to the adder 16, where the two outputs are added. Further, the output signal from the adder 16 is also sent to the P / S converter 17. All the data sent to these P / S converters 17 are parallel data. The P / S converter 17 is configured to convert the input parallel data into serial data and send the serial data to the D / A converter 6 in a predetermined order.

The operation of the device according to the present invention will be described below. In this embodiment, it is assumed that the video signal is magnified three times in the vertical and horizontal directions. The video signal picked up by the image pickup device 1 is digitally converted by the A / D converter 3 after passing through the buffer 2, sent to the vertical expansion circuit 5, and stored in the frame memory 10 in the vertical expansion circuit 5. The frame memory 10 repeatedly outputs the same line data three times as shown in FIG. 3 in order to expand the video signal by three times in the vertical direction. Line memory 11
Then, by storing the output signal from the frame memory 10 every three lines, it is possible to repeatedly output data every three lines as in the frame memory 10. The adder 12 adds the output signals from both the frame memory 10 and the line memory 11. Then, in the vertical selector 13, the frame memory 10 and the adder 1
By outputting both output signals from 2 while switching at a ratio of 2 to 1, as shown in FIG.
A video signal that is doubled in size is obtained. The output of each data is output in synchronization with the sync signal from the sync signal generation circuit 8.

The video signals output from the vertical selector 13 are sent to the line memories 14 and 15 in the horizontal expansion circuit 5, respectively, and are stored in a state where one pixel is thinned out from four pixels. By thinning out the data from the fourth pixel of the input signal in the line memory 14 and from the first pixel of the input signal in the line memory 15, the adjacent pixels from the line memories 14 and 15 are removed from the line memories 14 and 15 as shown in FIG. Can be output. These two outputs and the data obtained by adding these two outputs by the adder 16 are sent to the P / S converter 17. The P / S converter 17 converts the input 4 words into 1 word, and in order to output the data sent from the line memory 14, the adder 16 and the line memory 15, it is shown in FIG. 3 horizontally
It is possible to obtain data that is doubled in size. even here,
Similar to the operation in the vertical expansion circuit 4, each output data is output in synchronization with the sync signal from the sync signal generation circuit 8. From the above, it is possible to obtain data in which the original video signal is expanded three times in the vertical and horizontal directions.

Next, another example of the vertical expansion circuit 4 will be described with reference to FIG. FIG. 6 shows the configuration of the vertical expansion circuit 4 when the image pickup device 1 takes an image by the interlace method. The data imaged in the odd field by the image sensor 1 is stored in the field memory 18, and the data imaged in the even field is stored in the field memory 19. Field memory 1
The data stored in 8 and 19 are read out at the same time,
The two outputs are sent to the vertical selector 21. On the other hand,
The two outputs are added by the adder 20 and then sent to the vertical selector 21. The vertical selector 21 is configured so that the data sent from the field memories 18 and 19 and the adder 20 can be switched in a predetermined order and sent to the horizontal expansion circuit 5.

The operation of the vertical expansion circuit shown in FIG. 6 will be described below. Also in the vertical expansion circuit of this embodiment,
It shall be magnified three times in the vertical direction. The video signal picked up by the image pickup device 1 is passed through the buffer 2 to A
It is sent to the / D converter 3. The video signal is digitally converted by the A / D converter 3, and then the video signal is sent to and stored in the field memory 18 in the odd field and stored in the field memory 19 in the even field. The data stored in the field memories 18 and 19 are read simultaneously as shown in FIG. At this time, data on the same line is repeatedly output three times. Further, the vertical selector 21 repeatedly outputs the transmitted data from the field memory 18, the adder 20, and the field memory 19 in this order.
When the same operation is performed for the odd field and the even field and output to the TV monitor via the buffer 7,
The screen as shown in FIG. 8 is displayed. Here, the solid line shows the display data of the odd field and the dotted line shows the display data of the even field. As is clear from this figure, the number of lines in each line is tripled compared to the original data, and it can be seen that the video signal has been tripled in the vertical direction.

[0015]

Since the present invention is constructed as described above, image enlargement can be realized with a small and inexpensive circuit. Moreover, since it is possible to add the data of adjacent lines or pixels and switch the output at a constant rate, it is possible to prevent a decrease in resolution when the image is enlarged. Further, in the present invention, although the video signal is not specified, the RG
B3 primary color signals may be used, or luminance and color difference signals may be used. Even an interlaced signal as defined by the NTSC can be dealt with by using the circuit shown in FIG. In addition, the frame memory,
Each storage method of line memory, field memory, or
By changing the read rate, the vertical selector, the switching timing of the P / S conversion circuit, etc., it can be easily realized even if the image enlargement ratio is n times (n ≧ 4, n is an integer).

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of an image processing apparatus according to the present invention.

FIG. 2 is a diagram showing a configuration of a vertical enlargement circuit of the image processing apparatus according to the present invention.

FIG. 3 is an explanatory diagram showing operation timing of the vertical expansion circuit shown in FIG.

FIG. 4 is a diagram showing a configuration of a horizontal enlargement circuit of the image processing apparatus according to the present invention.

5 is an explanatory diagram showing an operation timing of the horizontal expansion circuit shown in FIG.

FIG. 6 is a diagram showing another embodiment of the configuration of the vertical expansion circuit shown in FIG.

7 is an explanatory diagram showing operation timings of the vertical expansion circuit shown in FIG.

8 is a diagram showing a state of a screen where an output from the vertical expansion circuit shown in FIG. 6 is displayed on a television monitor.

[Explanation of symbols]

1 Image Sensor 2, 7 Buffer 3 A / D Converter 4 Vertical Enlargement Circuit 5 Horizontal Enlargement Circuit 6 D / A Converter 8 Sync Signal Generator 9 Controller 10 Frame Memory 11, 14, 15 Line Memory 12, 16, 20 Adder 13 , 21 Vertical selector 17 P / S converter 18, 19 Field memory L ₁ , L ₂ , ..., D ₁ , D ₂ , ... Each output data

Claims (1)

[Claims] 1. An image pickup means for picking up an optical image, a first image storage means composed of a plurality of memories for storing a video signal output from the image pickup means and simultaneously reading out two adjacent lines. First image calculation means for adding two lines of data output from one image storage means,
The first output switching means for switching the output of the first image storage means and the output of the first image calculation means in a predetermined order and the output of the first output switching means are stored adjacent to each other.
Second image storage means for simultaneously reading out pixels, second image calculation means for adding two pixel data output from the second image storage means, second image storage means, and second An image processing apparatus comprising: a second output switching unit that switches the output of the image calculation unit in a predetermined order.