JP2006235434A - Device and method for driving display panel, and digital camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a required circuit configuration in a configuration for simultaneously producing a video signal and a display signal for driving a display panel such as a liquid crystal panel. <P>SOLUTION: The display panel driving device includes a variable power circuit 42 for horizontal variable magnification which transforms the number of horizontal pixels of YUV data of the number of horizontal pixels according to a video signal into the number of horizontal pixels of the liquid crystal panel; an RGB arithmetic circuit 43 for transforming the transformed YUV data into RGB data; and a parallel-serial transformation circuit 44 for producing a serial RGB signal from the transformed parallel RGB data. Timing of driving the liquid crystal panel synchronizing with that of producing the video signal is controlled by a data enable signal from a control counter 45, and the parallel-serial transformation circuit 44 is made to sample only the RGB data of effective pixels except invalid data produced by the transformation of the number of horizontal pixels performed by the circuit 42 for horizontal variable magnification, and is made to produce the serial RGB signal for driving the liquid crystal panel. It is unnecessary to arrange a line buffer at the pre-stage of the circuit 42 for horizontal magnification. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display panel driving apparatus, a display panel driving method, and a digital camera for driving a display panel by a display signal for driving generated simultaneously with generation of a video signal.

  Conventionally, in a digital camera equipped with an LCD (Liquid Crystal Display) that displays a through image or a recorded image in a shooting standby state, a video signal of the NTSC system is generated from image data recorded on a recording medium such as a memory card. And a function for outputting the recorded image, and the recorded image or the like can be reproduced and displayed on the TV receiver. In addition, in a device having such a video output function, a TV signal can be generated simultaneously by generating an externally output video signal and an RGB signal for driving an LCD based on a YUV signal generated from recorded image data or the like. Many of them enable simultaneous display of recorded images and the like on the receiver and the LCD.

  Further, the resolution of the LCD used in the digital camera, that is, the number of pixels of the liquid crystal panel is smaller than the number of pixels of the display image by the video signal. When the video signal is of the NTSC system, the number of horizontal pixels is 704 pixels, whereas the liquid crystal panel has 560 pixels, 480 pixels, 352 pixels, 320 pixels, and the like. For this reason, when generating RGB signals for driving the liquid crystal panel during simultaneous display, pixel thinning is performed to match the number of horizontal pixels with the number of horizontal pixels of the liquid crystal panel.

For example, Japanese Patent Application Laid-Open No. H10-228688 discloses a liquid crystal panel having a number of display lines in the vertical direction suitable for an NTSC video signal for driving a liquid crystal panel, and a PAL system having a larger number of scanning lines than the NTSC system. In the case of driving with, a method is disclosed that enables display corresponding to video signals of different systems on the same liquid crystal panel by performing line thinning.
JP 2002-218285 A

  However, as described above, when the video signal is subjected to pixel thinning or the like and sent to the LCD, there are the following problems.

  That is, if the number of horizontal pixels on the liquid crystal panel is 704 pixels, for example, the number of pixels compliant with the NTSC system, or 352 pixels, which is half that number, the pixels can be thinned out at equal intervals for each line. Can be easily implemented. On the other hand, when the number of horizontal pixels of the liquid crystal panel is not compliant with the video system, for example, 560 pixels and 480 pixels, the pixels to be thinned out in each line are not equally spaced. Therefore, when the number of horizontal pixels of the liquid crystal panel is not compliant with the video system, particularly when the input interface of the LCD is a digital system, for example, a line buffer that temporarily stores a YUV signal generated from image data or the like is used. Therefore, it is necessary to generate and output an RGB signal for driving the LCD, and there is a problem that a processing circuit for driving becomes complicated.

  The present invention has been made in view of such a conventional problem, and simplifies a necessary circuit configuration in a configuration for simultaneously generating a video signal and a display signal for driving a display panel such as a liquid crystal panel. It is an object of the present invention to provide a display panel driving device, a display panel driving method, and a digital camera that can perform the above.

  In order to solve the above-mentioned problem, in the first aspect of the present invention, for driving the display panel based on the image data in synchronism with the generation of the video signal based on the image data of the horizontal pixel number according to the television system. A display panel driving apparatus that generates a display signal and drives the display panel by the display signal, and a scaling unit that converts the number of horizontal pixels of the image data into the number of horizontal pixels of the display panel; and the video signal Drive timing generation means for generating the drive timing of the display panel in synchronization with the generation timing of the display, timing control means for controlling the drive timing generated by the drive timing generation means, and the drive timing controlled by the timing control means Only effective pixel data excluding invalid data generated by conversion from the image data converted by the scaling means Was sampled, was that a display signal generating means for generating the display signal based on the sampled pixel data.

  In such a configuration, when the display signal for driving the display panel is generated in synchronization with the generation of the video signal, the image data used for generating the video signal can be changed to any arbitrary horizontal pixel without using a line buffer or the like. A display signal for driving the display panel can be generated from the converted image data while converting into a number of image data.

  According to the invention of claim 2, a display signal for driving the display panel is generated based on the image data in synchronization with the generation of the video signal based on the image data having the number of horizontal pixels according to the television system. A display panel driving apparatus for driving the display panel by the display signal, a scaling unit for converting the number of horizontal pixels of the image data into the number of horizontal pixels of the display panel, and a generation timing of the video signal; The pixel data is sampled from the image data after the conversion by the scaling unit at the driving timing generating unit for generating the synchronized driving timing of the display panel and the driving timing generated by the driving timing generating unit. Display signal generating means for generating the display signal based on the display timing and the drive timing by the display signal generating means. Timing control means for controlling the sampling operation of the pixel data, and causing the display signal generating means to sample only effective pixel data excluding invalid data generated by the conversion from the image data after the conversion by the scaling means. It was assumed.

  Even in such a configuration, when the display signal for driving the display panel is generated in synchronization with the generation of the video signal, the image data used for generating the video signal can be changed to any arbitrary horizontal pixel without using a line buffer or the like. A display signal for driving the display panel can be generated from the converted image data while converting into a number of image data.

  According to a third aspect of the present invention, the zooming means comprises a plurality of zooming means including a first zooming means located in the preceding stage and a second scaling means located in the subsequent stage. And selecting one of the image data converted by the first scaling unit and the image data converted stepwise by the first scaling unit and the second scaling unit The display signal generating means samples only the effective pixel data from the image data output by the selecting means, and generates the display signal based on the sampled pixel data; did.

  According to a fourth aspect of the present invention, the zooming means comprises a plurality of zooming means provided in a plurality of stages, each having a different zooming ratio.

  In the invention of claim 5, when the image data having the number of horizontal pixels corresponding to the television system is converted from the original image data having a predetermined number of horizontal pixels in the plurality of scaling units. It is assumed that a scaling unit having a scaling factor (N / M) that is the reciprocal of the scaling factor (M / N) is included.

  In the invention of claim 6, the pixel arrangement of the display panel is a delta arrangement in which the three color component pixels constituting one pixel are arranged in a triangle shape across two lines. .

  In the invention of claim 7, a display signal for driving the display panel based on the image data is generated while the video signal is generated based on the image data of the number of horizontal pixels corresponding to the television system. A display panel driving method for generating and driving the display panel according to the display signal, the step of converting the number of horizontal pixels of the image data into the number of horizontal pixels of the display panel, and the video during the conversion operation The sampled pixel data is obtained by sampling effective pixel data excluding invalid data generated by the conversion from the converted image data at the sampling timing obtained by controlling the drive timing of the display panel in synchronization with the signal generation timing. And generating the display signal based on the method.

  According to this method, when the display signal for driving the display panel is generated in synchronization with the generation of the video signal, the image data used for generating the video signal can be changed to any arbitrary horizontal direction without using a line buffer or the like. A display signal for driving the display panel can be generated from the converted image data while converting the image data to the number of pixels.

  In the invention of claim 8, an image pickup means for picking up a subject, an image storage means for storing image data of the subject picked up by the image pickup means, and an image data stored in the image storage means. In a digital camera comprising an image display means for displaying an image based on the original image scaling means for converting the image data stored in the image storage means into image data of the number of horizontal pixels according to the television system, and A video signal generation unit that generates a video signal based on the image data converted by the original image scaling unit, and a display panel that has the number of horizontal pixels of the image data converted by the original image scaling unit in the image display unit. Scaling means for converting to the number of horizontal pixels, and drive timing generation for generating drive timing of the display panel synchronized with the generation timing of the video signal Stage, timing control means for controlling the drive timing generated by the drive timing generation means, and invalidity caused by conversion from the image data converted by the scaling means at the drive timing controlled by the timing control means. Only effective pixel data excluding data is sampled, and display signal generating means for generating the display signal based on the sampled pixel data is provided.

  In such a configuration, when the display signal for driving the display panel is generated in synchronization with the generation of the video signal in the digital camera, the image data used for generating the video signal is different without using a line buffer or the like. A display signal for driving the display panel can be generated from the converted image data while converting into image data having an arbitrary number of horizontal pixels.

  As described above, in the present invention, when the display signal for driving the display panel is generated in synchronization with the generation of the video signal, the image data used for generating the video signal is different without using a line buffer or the like. A display signal for driving the display panel can be generated from the converted image data while converting into image data having an arbitrary number of horizontal pixels. Therefore, in a configuration in which a video signal and a display signal for driving a display panel such as a liquid crystal panel are generated at the same time, a necessary circuit configuration can be simplified. As a result, it is possible to easily cope with various display pals that do not comply with the video system.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing an electrical configuration of a digital camera common to each embodiment including a liquid crystal driving device according to the present invention. That is, the CCD 1 captures the subject image formed by the lens. The color image signal picked up by the CCD 1 is sequentially A / D converted based on a timing signal generated by the CCD control unit 2 and then sent to the YUV processor 3. The YUV processor 3 creates YUV data composed of luminance component data and two color component data from each pixel of the color image. The created YUV data is stored in the image memory 5 such as a flash memory by the memory controller 4.

  The CPU 6 controls the operation of the memory controller 4 based on a key input signal from the key processing unit 7 and a program recorded on the recording medium 8. The recording medium 8 includes a ROM and a RAM. The program is stored in the ROM and the RAM is used as a work memory.

  When the contents of the image memory 5 are displayed by the memory controller 4, the image data read by the memory controller 4 is expanded by the CPU 6 and stored in the VRAM 9 as YUV data having a display VGA size (horizontal 640 pixels × vertical 480 pixels). Be expanded. The developed YUV data is sequentially sent to the encoder 10, converted into RGB signals, and then displayed on the liquid crystal panel of the liquid crystal display device (LCD) 11. The YUV data sent to the encoder 10 is converted into a video signal and output from the video output terminal 12 to a monitor such as a TV receiver.

  FIG. 2 is a block diagram mainly showing a circuit configuration of the encoder 10. In the encoder 10, the YUV data sequentially stored in the VRAM 9 by the horizontal pixel conversion unit 21 is converted to 11/10 times the number of pixels in the horizontal direction by linear interpolation processing, and the horizontal 704 corresponding to the horizontal scanning cycle of the NTSC system. It is converted into YUV data (24-bit width parallel signal) of the pixel and output to a video encoder (Video Encode) 22 and a liquid crystal encoder (LCD Encode) 24. The horizontal pixel conversion unit 21 converts the number of pixels in the vertical direction in the YUV data into 240 pixels corresponding to the NTSC vertical scanning cycle. Further, the horizontal pixel conversion unit 21 receives a horizontal valid signal indicating a horizontal effective data range generated separately from the reference clock from a video timing generation circuit (Video Timing Gen.) 25, and a vertical effective data range. A vertical valid signal is supplied.

  The video encoder 22 and the liquid crystal encoder 24 operate on the basis of a reference clock supplied from a video timing generation circuit (Video Timing Gen.) 25. The video encoder 22 converts the YUV data from the horizontal pixel converter 21 into a video signal compatible with the NTSC system and outputs the video signal. The output digital video signal is converted into an analog signal at 27 MHz sampling by a D / A converter (DAC) 23 and output to an external monitor such as a TV receiver via the video output terminal 12.

  In addition, the liquid crystal encoder 24 generates RGB data obtained by thinning out the number of pixels in the horizontal direction in the YUV data from the horizontal pixel conversion unit 21 in accordance with the number of pixels of the liquid crystal panel of the liquid crystal display device 11. 11 directly. Details of the liquid crystal encoder 24 will be described later.

  FIG. 3A is a diagram showing a module structure of the liquid crystal display device 11. The liquid crystal display device 11 includes a digital input interface including a liquid crystal panel 31, a source driver 32, and a gate driver 33, and a liquid crystal timing generation circuit (CLD Timing Gen.) 26 based on a reference clock supplied from the video timing generation circuit 25. It is driven by a timing signal for liquid crystal display that generates the image, and an image based on the RGB data from the liquid crystal encoder 24 is displayed. FIG. 3B is a diagram showing a pixel (color filter) arrangement in the liquid crystal panel 31. The number of pixels is 240 vertical pixels × 320 horizontal pixels, and the arrangement thereof is such that each of R, G, and B pixels adjacent in the vertical direction is arranged so as to be shifted from each other by half a dot, and a pair of lines indicated by a broken line in the figure This is a so-called “delta arrangement” in which three dots of R, G, and B constituting a pixel are arranged in a triangle shape across two lines.

  Correspondingly, in the liquid crystal encoder 24, when displaying the image data of vertical 240 pixels × horizontal 720 pixels shown in FIG. 4, it is adjacent in the horizontal direction in the corresponding odd lines and even lines. Serial RGB data is generated and output to the liquid crystal display device 11 while switching between odd-numbered lines and even-numbered lines so that the same color elements are shifted by 1.5 pixels. That is, the pixels of the respective color components indicated by the symbol “◯” in the figure are output in the odd and even lines.

  For example, in two lines corresponding to X1 and X2 of the liquid crystal panel 31, image data to be displayed as dots R of (X1, Y1) and dots R of (X2, Y3) as adjacent dots of the same color component is obtained. Think about the case. The dot R of (X1, Y1) is shifted to the right by half a dot from the dot G of (X2, Y1). Therefore, among the two pieces of pixel data of the row number “1” and the column numbers “1” and “2” in the digital image shown in FIG. ”And displayed as (X1, Y1) dots R on the liquid crystal 31 panel. Similarly, the data displayed by the dot R of (X2, Y3) on the liquid crystal panel 31 has the R component in the pixel data of the row number “2” and the column number “5” in the digital image represented by the symbol “◯”. Will be selected as shown.

  FIG. 5 is a block diagram showing a circuit configuration of the liquid crystal encoder 24 described above. In the liquid crystal encoder 24, the delay circuit 41 delays the YUV data (24-bit width parallel signal) from the horizontal pixel conversion unit 21 described above, and outputs the delay data (dlyYUV data) to the horizontal scaling circuit 42 together with the YUV data. To do. The lateral scaling circuit 42 performs 10/11 times (pixel thinning) while performing linear interpolation using delay data (dlyYUV data) based on the reference clock from the video timing generation circuit 25 supplied via the control counter 45. The YUV data of 720 pixels in the horizontal direction is converted into YUV data of 620 pixels in the horizontal direction according to the number of horizontal pixels of the liquid crystal panel 31 and output. The converted YUV data is converted into an RGB signal by the RGB operation circuit 43 and output to the parallel-serial conversion circuit 44.

  In accordance with the count signal supplied from the control counter 45, the parallel-serial conversion circuit 44 converts the parallel YUV data from the RGB operation circuit 43 into a serial RGB signal in which 8-bit width RGB color component data are arranged in order, It outputs to the liquid crystal display device 11 as a drive signal. In the conversion to the RGB signal, the RGB color component data to be output to the liquid crystal panel 31 is selected from the input parallel RGB signals according to the odd-numbered line and the even-numbered line.

  The control counter 45 outputs a sampling frequency count signal generated based on the reference clock from the video timing generation circuit 25 to the delay circuit 41, the lateral scaling circuit 42, and the parallel-serial conversion circuit 44. Further, by sending a data enable signal to the liquid crystal timing generation circuit 26 at a timing described later, the driving clock to the liquid crystal display device 11 based on the reference clock from the video timing generation circuit 25 in the liquid crystal timing generation circuit 26 is inverted. The timing at which the control counter 45 sends the data enable signal to the liquid crystal timing generation circuit 26 is determined depending on the circuit configuration of the lateral scaling circuit 42. That is, in the processing of the horizontal scaling circuit 42, pixel data that has been lost due to the decrease in the number of horizontal pixels is treated as dummy data (data indicated by the symbol “*” in FIG. 6). A data enable signal is sent to the liquid crystal timing generation circuit 26 at the appearance timing of the dummy data.

  FIG. 6 shows the contents of the above-described signals in the liquid crystal encoder 24 and the liquid crystal display device when the video signal of a certain image is generated and output and simultaneously the liquid crystal display device 11 is driven to display the image. 11 is a diagram illustrating drive timings 11. As shown in the figure, the YUV data of 704 pixels in the horizontal direction ("input DATA" in the figure) sequentially input to the liquid crystal encoder 24 is 640 pixels of YUV data (see figure) corresponding to the number of horizontal pixels (320 pixels) of the liquid crystal panel 31. To “10/11”).

  On the other hand, during this period, only effective pixels are sampled from the converted YUV data according to the drive clock in the tooth missing state that is inverted at the above-described dummy data appearance timing, and “2”, “ Serial RGB signals (“LCDDT (odd)” in the figure) composed of color component data (R, G, B, R,...) Corresponding to the pixels 4, “6”, “8”,. ), And the driving period of the even lines is composed of color component data (G, B, R, G,...) Corresponding to the pixels “1”, “3”, “5”,. A serial RGB signal (“LCDDT (even)” in the figure) for 320 pixels per line is generated. Then, the generated serial RGB signal is output, and thereby the liquid crystal display device 11 is driven in synchronization with the generation of the video signal in the video encoder 22.

  As described above, according to the present embodiment, the number of pixels in the horizontal direction of the liquid crystal panel 31 of the liquid crystal display device 11 is 320 pixels, and the liquid crystal display device 11 is not compliant with the video system. Even without using a line buffer that temporarily stores YUV signals for video generated from image data or the like, it is possible to generate and output RGB signals for driving the liquid crystal display device 11 by using only the liquid crystal encoder 24 as they are. Therefore, the circuit configuration of the encoder 10 can be simplified as much as possible, and various liquid crystal display devices that do not comply with the video system can be handled.

  In the present embodiment, since the number of pixels in the horizontal direction of the liquid crystal panel 31 is 320, the scaling factor of the horizontal scaling circuit 42 in the liquid crystal encoder 24 is 10/11 times. If the magnification ratio of the lateral magnification circuit 42 and the output timing of the data enable signal from the control counter 45 are appropriately changed according to the number of pixels in the horizontal direction, various liquid crystal display devices can be supported.

  Here, in the present embodiment, the waveform of the drive clock supplied from the liquid crystal timing generation circuit 26 to the liquid crystal display device 11 is controlled by the data enable signal, so that a serial RGB signal consisting only of color component data of effective pixels is controlled. Is generated, but may be generated as follows. For example, the parallel-serial conversion circuit 44 may be configured to skip the dummy data based on the data enable signal without changing the drive clock waveform of the liquid crystal timing generation circuit 26. The horizontal valid signal and the vertical valid signal supplied from the video timing generation circuit 25 to the horizontal pixel converter 21 may be directly supplied to the liquid crystal encoder 24.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. FIG. 7 is a diagram showing another circuit configuration of the liquid crystal encoder 24 corresponding to FIG. Since the configuration is basically the same as that described above, the same parts are denoted by the same reference numerals and the description thereof is omitted.

  That is, in the present embodiment, another lateral scaling circuit 51 having an arbitrary scaling factor (M / N times) different from that is provided at the subsequent stage of the above-described lateral scaling circuit 42, while the preceding lateral scaling circuit is provided. The YUV data (Y'U'V 'in the figure) in which the number of pixels in the horizontal direction has been converted by 42 and the YUV data (Y'U'V' in the figure) in which the number of pixels in the horizontal direction has been converted by the horizontal scaling circuit 51 in the subsequent stage. Y ″ U ″ V ″) are once input to the selection circuit (SEL) 52, and only one of them is output to the RGB operation circuit 43.

  The selection circuit 52 and the control counter 45 are provided with setting registers 52a and 45a, respectively. The preceding horizontal scaling circuit 42, the subsequent horizontal scaling circuit 51 and the selection state in the selection circuit 52 are set based on the setting data written in the register 52a by the CPU 6, and similarly in the corresponding control counter 45. The generation timing of the data enable signal described above is set based on the setting data written in the register 45a by the CPU 6.

  According to this configuration, by appropriately switching the selection state of the selection circuit 52 and the generation timing of the data enable signal of the control counter 45 by software, the liquid crystal display device 11 having 320 pixels in the horizontal direction, It is possible to easily cope with both of other liquid crystal display devices having different numbers of pixels in the horizontal direction. Therefore, versatility can be secured in the circuit configuration of the liquid crystal encoder 24 portion.

  It should be noted that the scaling factor of the preceding horizontal scaling circuit 42 shown in the present embodiment may be other than 10/11 as required. Further, the above switching setting in the selection state of the selection circuit 52 corresponding to the liquid crystal display device to be used and the generation timing of the data enable signal of the control counter 45 may be performed by hardware before shipment of the digital camera. it can. Even in this case, versatility can be secured in the circuit configuration of the liquid crystal encoder 24 portion.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. In the present embodiment, although not shown, the circuit configuration of the liquid crystal encoder 24 is eliminated by, for example, eliminating the selection circuit 52 in the configuration shown in FIG. 7 and simply providing a plurality of lateral scaling circuits. It corresponds to an arbitrary liquid crystal display device having a predetermined number of pixels in the direction.

  FIG. 8 is a diagram corresponding to FIG. 6 and showing the drive timing of the liquid crystal display device when the lateral scaling circuit has two stages. In this example, when the liquid crystal display device to be used has a delta-aligned liquid crystal panel with 640 pixels in the horizontal direction, the magnification at the front stage is doubled and the magnification at the rear stage is 10 times. / 11 times the drive timing.

  FIG. 9 is a diagram corresponding to FIG. 6 showing the driving timing of the liquid crystal display device in the case where the lateral scaling circuit has three stages. In this example, when the liquid crystal display device used has a delta-aligned liquid crystal panel with 480 pixels in the horizontal direction, the first stage magnification is doubled and the second stage magnification is changed. This is the drive timing when the magnification is 10/11 times and the third stage magnification is 3/4 times.

  In the case where a plurality of lateral magnification circuits are provided as described above, when obtaining the required number of pixels in the horizontal direction, each lateral variation is compared with the case where it is obtained with a single lateral magnification circuit. Since the configuration of the double circuit can be simplified, as a result, the circuit scale can be made smaller. At the same time, since the circuit design is simplified, it can be easily applied to various liquid crystal display devices. Further, as in the example shown in FIGS. 8 and 9, the horizontal pixel conversion shown in FIG. 2 is indispensable for the generation of the video signal, that is, the scaling factor of any of the plurality of horizontal scaling circuits is 10/11 times. A scaling factor for canceling the horizontal pixel number conversion by the unit 21 is used. In other words, the circuit scale can be suppressed by further simplifying the circuit by providing a lateral scaling circuit having a scaling ratio of 10/11 independently. Such an effect can be similarly obtained when the circuit configuration shown in FIG. 7 is implemented in the second embodiment.

(Embodiment 4)
Next, a fourth embodiment of the present invention will be described. In the present embodiment, the liquid crystal display device 11 includes a liquid crystal panel having a stripe arrangement, and the liquid crystal encoder 24 is provided with two stages of lateral scaling circuits, and the parallel-serial conversion circuit 44 corresponding thereto. However, this is a circuit configuration for generating serial RGB signals by performing data sampling in units of RGB for each pixel from YUV data.

  FIG. 10 is a diagram corresponding to FIG. 6 showing the driving timing of the liquid crystal display device in that case. This example shows a case where the number of pixels in the horizontal direction of the liquid crystal panel is 320, the magnification of the horizontal scaling circuit in the front stage is 2 times, and the scaling ratio of the horizontal scaling circuit in the back stage is 10/11 times. In addition, the drive timing of the liquid crystal display device 11 is a predetermined tooth missing sampling drive in which data sampling of one pixel is performed every four clocks.

  In this embodiment, as in the first to third embodiments described above, the circuit configuration of the encoder 10 can be simplified as much as possible, and various liquid crystal display devices that are not compliant with the video system can be supported. The effect that it is possible can be obtained.

  Here, in the description of the first to fourth embodiments described above, a configuration for adjusting the number of pixels in the horizontal direction in the RGB signals mainly for driving the liquid crystal display device to the number of pixels in the horizontal direction of the liquid crystal panel. In the case where it is necessary to match the number of pixels in the vertical direction of the RGB signal with the number of pixels in the vertical direction of the liquid crystal panel, or in a configuration capable of outputting two types of video signals of the NTSC system and the PAL system. In other words, the above-described liquid crystal encoder 24 may be provided with the vertical scaling unit 61 as shown in FIG. 11 before and after the lateral scaling circuit.

  Here, the vertical scaling unit 61 is provided at the subsequent stage of the horizontal scaling circuit, and after horizontal scaling, the number of pixels in the horizontal direction of YUV data is M pixels, and the number of vertical pixels is 288 pixels corresponding to the PAL system. It is assumed that the number of pixels in the vertical direction in the required RGB signal is 240 pixels.

  That is, the vertical scaling unit 61 temporarily stores YUV data (parallel data) for one line in the line buffer 62, and the YUV data pixels one line before stored in the line buffer 62 by the vertical scaling circuit 63. Based on the data and the pixel data of the input YUV data for one line, for example, new pixel data that is 5/6 times (line thinning) is generated by linear interpolation, and is input to the RGB arithmetic circuit 43 in the subsequent stage. Further, a drive for causing the control counter 64 to output a line enable signal based on the vertical valid signal indicating the effective range of the data in the vertical direction and sampling the color component data for the required horizontal line based on the line enable signal. The liquid crystal timing generation circuit 26 generates the clock. As a result, an RGB signal having 240 pixels in the vertical direction is output to the liquid crystal display device.

  In the above description, the case where the display panel of the present invention is a liquid crystal panel has been described. However, the present invention is also effective in a configuration using another display panel such as an EL (electroluminescence) panel. Although the case where the present invention is applied to a digital camera has been described, the present invention can also be applied to a video movie camera, a mobile phone terminal with a camera function, and the like.

It is a block diagram which shows the electric constitution of the digital camera common to each embodiment of this invention. It is a block diagram which shows the circuit structure of an encoder. It is explanatory drawing which shows the module structure (a) of a liquid crystal display device, and the pixel arrangement | sequence (b) of a liquid crystal panel. It is explanatory drawing which shows the example of the serial drive of a liquid crystal panel. It is a block diagram which shows the circuit structure of the liquid-crystal encoder in 1st Embodiment. It is a figure which shows the drive timing of the liquid crystal panel in the embodiment. It is a block diagram which shows the circuit structure of the liquid-crystal encoder in the 2nd Embodiment of this invention. It is a figure which shows the drive timing of a liquid crystal panel in case the horizontal scaling circuit which shows the 3rd Embodiment of this invention is two steps | paragraphs. It is a figure which shows the drive timing of a liquid crystal panel in case the horizontal scaling circuit which shows the same embodiment is three steps | paragraphs. It is a figure which shows the drive timing of the liquid crystal panel in the 4th Embodiment of this invention. It is a block diagram which shows the circuit structure of the vertical scaling part common to each embodiment.

Explanation of symbols

9 VRAM
DESCRIPTION OF SYMBOLS 10 Encoder 11 Liquid crystal display device 12 Video output terminal 21 Horizontal pixel conversion part 22 Video encoder 24 Liquid crystal encoder 25 Video timing generation circuit 26 Liquid crystal timing generation circuit 31 Liquid crystal panel 32 Source driver 33 Gate driver 41 Delay circuit 42 Horizontal scaling circuit 43 RGB Arithmetic circuit 44 Parallel-serial conversion circuit 45 Control counter 51 Horizontal scaling circuit 52 Selection circuit 61 Vertical scaling section

Claims (8)

A display signal for driving the display panel is generated based on the image data in synchronization with the generation of the video signal based on the image data having the number of horizontal pixels according to the television system, and the display panel is driven by the display signal. A display panel driving device comprising:
Scaling means for converting the number of horizontal pixels of the image data into the number of horizontal pixels of the display panel;
Drive timing generation means for generating a drive timing of the display panel synchronized with the generation timing of the video signal;
Timing control means for controlling the drive timing generated by the drive timing generation means;
At the drive timing controlled by this timing control means, only the effective pixel data excluding invalid data generated by the conversion is sampled from the image data after conversion by the scaling means, and the display signal is based on the sampled pixel data. And a display signal generating means for generating the display panel driving device. A display signal for driving the display panel is generated based on the image data in synchronization with the generation of the video signal based on the image data having the number of horizontal pixels according to the television system, and the display panel is driven by the display signal. A display panel driving device comprising:
Scaling means for converting the number of horizontal pixels of the image data into the number of horizontal pixels of the display panel;
Drive timing generation means for generating a drive timing of the display panel synchronized with the generation timing of the video signal;
Display signal generation means for sampling pixel data from the image data after conversion by the scaling means at the drive timing generated by the drive timing generation means, and generating the display signal based on the sampled pixel data;
The display signal generation means controls the sampling operation of the pixel data at the drive timing, and the display signal generation means only has the effective pixel data excluding the invalid data generated by the conversion from the image data converted by the scaling means. Timing control means for sampling,
A display panel driving device comprising: The zooming means is composed of a plurality of zooming means including a first zooming means located in the preceding stage and a second scaling means located in the subsequent stage,
One of the image data converted by the first scaling unit and the image data converted stepwise by the first scaling unit and the second scaling unit is selectively selected. Selecting means for outputting,
The display signal generation unit samples only the effective pixel data from the image data output by the selection unit, and generates the display signal based on the sampled pixel data. Display panel drive device.   3. The display panel driving apparatus according to claim 1, wherein the scaling unit includes a plurality of scaling units that are set in a plurality of stages and each has a different scaling factor.   The plurality of scaling units have a reciprocal of a scaling factor (M / N) when image data having a horizontal pixel number corresponding to the television system is converted from original image data having a predetermined horizontal pixel number. 5. The display panel driving device according to claim 3, further comprising a scaling unit in which a scaling factor (N / M) is set.   6. The pixel arrangement of the display panel is a delta arrangement in which three color component pixels constituting one pixel are arranged in a triangle shape over two lines. The display panel drive device described in 1. While the video signal is generated based on the image data of the horizontal pixel number according to the television system, a display signal for driving the display panel is generated based on the image data, and the display panel is driven by the display signal A display panel driving method
Converting the number of horizontal pixels of the image data into the number of horizontal pixels of the display panel;
Valid pixel data excluding invalid data generated by the conversion from the converted image data by the sampling timing obtained by controlling the drive timing of the display panel synchronized with the generation timing of the video signal during the conversion operation And a step of generating the display signal based on the sampled pixel data. An image pickup means for picking up an object, an image storage means for storing image data of the object picked up by the image pickup means, and an image display means for displaying an image based on the image data stored in the image storage means are provided. In digital cameras,
Original image scaling means for converting the image data stored in the image storage means into image data of the number of horizontal pixels according to a television system;
Video signal generating means for generating a video signal based on the image data converted by the original image scaling means;
Scaling means for converting the number of horizontal pixels of the image data converted by the original image scaling means to the number of horizontal pixels of the display panel of the image display means;
Drive timing generation means for generating a drive timing of the display panel synchronized with the generation timing of the video signal;
Timing control means for controlling the drive timing generated by the drive timing generation means;
At the drive timing controlled by the timing control means, only the effective pixel data excluding invalid data generated by the conversion is sampled from the image data converted by the scaling means, and the display signal is obtained based on the sampled pixel data. And a display signal generating means for generating the digital camera.

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