JP2001296832A - Conversion circuit and picture processor using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a conversion circuit capable of performing display on the display device of an interlaced system even when the signal processing circuit of the display device is the signal processing circuit of progressive outputs. SOLUTION: In this picture processor, a memory controller 122 which generates a write request WREQ instructing so as to perform the writing of data signals of the progressive system for every other data signal based on a synchronizing signal corresponding to signals of the progressive system by a scan converter 11 and generates a read request RREQ instruction so as to read out data to be written in accordance with the write request WREQ based on the frequency-divided synchronizing signal in which the synchronizing signal is frequency-divided and a DC-FIFO (DC first-in first-out) memory 121 which reads out the written data based on the read request signal while writing the data signals of the progressive system to be inputted for every other data signal based on the write request signal are provide.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlaced plasma display panel (Plasma Display Panel) using a signal processing circuit such as a scan converter that outputs progressive output of fixed image quality.
The present invention relates to a conversion circuit for extracting data of a signal processing circuit every other line and converting the data into an interlace when driving a display device such as PDP), and an image processing apparatus using the same.

[0002]

2. Description of the Related Art At present, liquid crystal display devices (Li)
For a display device of a fixed pixel such as a liquid crystal device (LCD) or a PDP, a progressive system is mainly used. Therefore, the scan converters used in these devices are often of the progressive output type.

For example, in a display device using a PDP, three primary color signals R (red), G
After (green) and B (blue) are restored, the analog signal is converted to a digital signal and supplied to the scan converter. Then, in the scan converter, since the input signal and the number of vertical and horizontal pixels of the display device may be different, adjustment and conversion are performed. For example, an input digital signal is written to an image memory at a predetermined clock, and then the written data is read out in synchronization with a clock having a frequency different from, for example, a writing clock, and an image corresponding to, for example, the number of vertical and horizontal pixels of the plasma display is read. Generate a signal and supply it to the display.

[0004]

By the way, some PDPs adopt an interlace method because of their merits in terms of resolution, brightness and cost.

However, as described above, at present, only a progressive output scan converter is practically used, so that it is impossible to drive an interlaced display device as it is. Therefore, it is desired to realize a circuit that can display a progressive output scan converter on an interlaced display device.

The present invention has been made in view of such circumstances, and has as its object to convert a progressive output signal processing circuit capable of displaying on an interlaced display device, and a conversion circuit using the same. To provide an image processing apparatus.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a conversion circuit for converting a progressive signal into an interlace signal, based on a synchronization signal corresponding to the progressive signal. hand,
A write request instructing to write every other data signal of the progressive system is generated, and based on a divided synchronization signal obtained by dividing the synchronization signal, data written in response to the write request is read. First to generate an instructed read request signal
And a second circuit that reads out the written data based on the read request signal while writing every other progressive data signal based on the write request from the first circuit.

In the present invention, when the progressive signal input to the first circuit is a signal converted from an interlaced signal, the interlaced signal is an odd field or an even field. And a third circuit for generating a parity signal indicating the determination result and outputting the parity signal to the first circuit, wherein the first circuit performs an odd field or even number Generate a write request and a read request for the data corresponding to the field.

In the present invention, the third circuit performs the field determination based on a horizontal synchronizing signal and a vertical synchronizing signal corresponding to an interlaced signal.

In the present invention, the third circuit may be configured such that, when the progressive signal input to the first circuit is generated based on the progressive signal, A parity signal is generated based on a vertical synchronizing signal corresponding to a progressive signal input to the circuit of (1).

The image processing apparatus according to the present invention further comprises: a signal processing circuit which receives a progressive or interlaced image signal, performs predetermined signal processing, and outputs the signal as a progressive signal; On the basis of the output synchronization signal corresponding to the progressive signal, a write request instructing to write every other progressive data signal is generated, and the divided synchronization signal is divided into a divided synchronization signal. A first circuit for generating a read request signal instructing to read data to be written in response to the write request, and a progressive data by the signal processing circuit based on the write request by the first circuit; While reading every other signal, read the above And a conversion circuit and a second circuit for reading data written on the basis of the quest signal.

In the present invention, when the signal input to the signal processing circuit is an interlaced signal, the conversion circuit determines whether the interlaced signal is an odd field or an even field. A third circuit that performs field discrimination, generates a parity signal indicating the discrimination result, and outputs the parity signal to the first circuit, wherein the first circuit is configured to generate an odd field or an even field based on the parity signal; Generate a write request and a read request for the corresponding data.

According to the present invention, in the first circuit, a write request instructing to write every other progressive data signal is generated based on a synchronization signal corresponding to the progressive signal, and A read request signal for instructing to read data to be written in response to the write request is generated based on the frequency-divided synchronization signal obtained by dividing the synchronization signal, and a second request signal is generated.
Circuit. In the second circuit, the data written based on the read request signal is read while every other progressive data signal is written based on the write request by the first circuit. That is, a progressive signal is converted into an interlace signal and output.

According to the present invention, when the progressive signal input to the first circuit is a signal converted from an interlaced signal, the interlaced signal is converted to an odd field in the third circuit. Or an even field is determined, and the result is supplied to the first circuit as a parity signal. Then, in the first circuit, a write request and a read request for data corresponding to the odd field or the even field are generated based on the parity signal.

[0015]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus employing a conversion circuit according to the present invention.

As shown in FIG. 1, the image processing apparatus 10 has a scan converter 11 as a signal processing circuit and a progressive-interlace (PI) conversion circuit 12 as main components. Then, the PI conversion circuit 12 includes a DC-FIFO (Dual
Clock First in First Out) Memory 121, DC-FI
It comprises a memory controller 122 as a first circuit for controlling the FO memory 121 and a parity generator 123 as a third circuit.

The scan converter 11 includes three primary color signals R (red), G (green), and B converted to digital signals by an analog / digital (A / D) converter (not shown).
(Blue), horizontal synchronization signal H-SYNC, vertical synchronization signal V-
SYNC and the clock signal CLK, and the input 3
The primary color signals, that is, the R, G, and B digital signals are written into the image memory at a predetermined clock, and then the written data is read out in synchronization with a clock having a frequency different from the write clock, for example, and the vertical and horizontal pixels of the plasma display are read out. A progressive video signal corresponding to the number is generated, and the DC-FIFO of the PI conversion circuit 12 is generated.
(Dual Clock First in First Out) Supply to memory.

The scan converter 11 converts various input signals into images and outputs the converted signals in a fixed pixel progressive system. That is, the input signal of the progressive system is not only output in the progressive system, but also the input signal of the interlace system is converted into a progressive video signal and output. When outputting the progressive video signal, the scan converter 11 outputs the corresponding horizontal synchronizing signal H-SYNCO, vertical synchronizing signal V-SYNCO and clock signal CLKO to P
The I-conversion circuit 12 supplies the vertical synchronization signal V-SYNCO to the memory controller 122 of the parity generator 12.
3 and supplies a clock signal having a frequency of 80 MHz to the DC-FIFO memory 121, for example.

The DC-FIFO memory 121 stores progressive R, G, and B data by the scan converter 11.
While the digital signal is written by the memory controller 122 in synchronization with the write request WREQ by the clock signal of 80 MHz, in synchronization with the clock of 40 MHz and the read request RREQ, in the case of an odd field, as shown in FIG. 1, 3, 5. . . A line is taken out and output. In the case of an even field, FIG.
, 2, 4, 6,. . . Take out the line and output. That is, the DC-FIFO memory 121 converts a progressive signal into an interlace signal and outputs the signal.

For example, the write clock signal in the DC-FIFO memory 121 is 80 MHz, the write horizontal synchronization signal (H.Sync) is 67.5 kHz, the read side is half each, and the read clock signal is 40 MHz.
z, the horizontal synchronization signal (H.Sync) is 33.75 kHz.

As shown in FIG. 2, in the case of an odd field, first, while writing data of the first line into the DC-FIFO memory 121 with a write clock signal of 80 MHz, the data is read and output by a read clock signal of 40 MHz. I do. Then, without doing anything on the second line, the next line is read out and output while similarly writing. By repeating this operation, data is taken out every other line and converted to interlace.

In the case of even-numbered fields, as shown in FIG. . . Take out the line and output.

The memory controller 122 receives the horizontal synchronizing signal H-SYNCO from the scan converter 11, and for example, as shown in FIG. 2B or FIG. 3B, the odd field or even number of the horizontal synchronizing signal H-SYNCO. A write request signal WREQ having a predetermined pulse width is generated between adjacent pulses defining
It is supplied to the C-FIFO memory 121 and, for example, a horizontal synchronizing signal H-SYNC from the scan converter 11.
In response to O, for example, as shown in FIG. 2 (D) or FIG. 3 (D), a horizontal synchronizing signal H-SYNCO is frequency-divided by 2 to generate a read horizontal synchronizing signal, and a read of a predetermined pulse width is performed between the pulses. Generates request signal RREQ to DC
Supply to the FIFO memory 121; Further, the memory controller 122 receives the parity signal S123 from the parity generator 123, and receives a write request WREQ and a read request RR according to an odd or even number.
It generates an EQ and supplies the parity signal to a display device (not shown), for example, a PDP.

First, the parity generator 123 determines whether the input signal to the scan converter 11 is a progressive signal based on the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC input to the can converter 11. Since the conversion circuit 12 determines whether the signal is an interlaced signal or not, and the conversion circuit 12 converts the progressive signal into an interlaced signal, if the signal is an interlaced signal, whether the signal is an odd field or an even field. And supplies a parity signal S123 indicating the result of the determination to the memory controller 122.

Since the output from the scan converter 11 is a progressive signal, it can be considered that the parity signal may have any polarity in order to convert it into an interlace. Parity generator 123
Since the polarity of the signal when the input signal to the scan converter 11 is a progressive signal may be any, the vertical synchronizing signal V-SYN of the output of the scan converter 11 can be used.
In response to CO, a T-type flip-flop (T-FF
(Toggle-Flip Flop)) and the parity signal S123.
Generate

However, when the input signal to the scan converter 11 is an interlace signal, as a result of an experiment, the image quality is deteriorated unless the input parity and the polarity are matched. For this purpose, the parity generator 123 according to the present embodiment uses the horizontal synchronization signal HS input to the scan converter 11.
The parity signal S123 is generated based on the YNC and the vertical synchronization signal V-SYNC.

The horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC of the NTSC, PAL and DTV interlace signals have a relationship as shown in FIG. That is, in a field at the edge of the vertical synchronization signal V-SYNC, the horizontal synchronization signal H-SYNC
The edges of the NC and the vertical synchronization signal V-SYNC are aligned, and are shifted by 0.5H in the next field.

Next, the operation of the above configuration will be described.

For the scan converter 11, R, G, B digital signals of three primary colors converted into digital signals by an A / D converter (not shown), and a horizontal synchronizing signal H-SYN.
C, vertical synchronization signal V-SYNC, and clock signal C
LK is supplied. In the scan converter 11, for example, R, G, and B digital signals are written into the image memory at a predetermined clock, and the next written data is read out in synchronization with, for example, a clock having a frequency different from the write clock, and the vertical and horizontal directions of the PDP are read out. Is generated according to the number of pixels of the progressive system, and the PI conversion circuit 1
2 is supplied to the DC-FIFO memory 121.

When a progressive video signal is output from the scan converter 11, a horizontal synchronizing signal H-SYNCO and a vertical synchronizing signal V corresponding to the progressive video signal are output.
-SYNCO and the clock signal CLKO are supplied to the memory controller 122 of the PI conversion circuit 12, and the vertical synchronization signal V-SYNCO is supplied to the parity generator 123.
It is supplied to the C-FIFO memory 121.

Here, the horizontal synchronization signal H-SY input to the scan converter 11 is supplied to the parity generator 123.
NC and a vertical synchronization signal V-SYNC are supplied.

In the parity generator 123, the horizontal synchronizing signal H-SYN input to the can converter 11 is output.
Based on C and the vertical synchronization signal V-SYNC, it is determined whether the input signal to the scan converter 11 is a progressive signal or an interlace signal. As a result of the determination, when the input signal to the scan converter 11 is a progressive signal, the vertical synchronization signal VS supplied from the scan converter 11 is output.
A parity signal S123 is generated based on YNCO and supplied to the memory controller 122.

On the other hand, as a result of the determination, the scan converter 1
If the input signal to 1 is an interlaced signal, field discrimination is performed as to whether the field is an odd field or an even field, and the discrimination result is supplied to the memory controller 122 as a parity signal S123.

In the memory controller 122, the horizontal synchronizing signal H-SYNC from the scan converter 11 is output.
O, for example, as shown in FIG. 2 (B) or FIG. 3 (B), a write request signal WREQ having a predetermined pulse width between adjacent pulses defining an odd field or an even field of the horizontal synchronization signal H-SYNCO. Is generated and supplied to the DC-FIFO memory 121. In the memory controller 122, for example, the horizontal synchronization signal H-SYNC from the scan converter 11 is output.
In response to O, for example, as shown in FIG. 2 (D) or FIG. 3 (D), a readout horizontal synchronizing signal is generated by dividing the horizontal synchronizing signal H-SYNCO by 2, and a readout of a predetermined pulse width is performed between the pulses. A request signal RREQ is generated and supplied to the DC-FIFO memory 121. The memory controller 122 receives the parity signal S123 from the parity generator 123, generates a write request WREQ and a read request RREQ corresponding to an odd or even number, and supplies the parity signal to a display device (not shown) such as a PDP. Is done.

Then, in the DC-FIFO memory 121, progressive R, G, B digital signals by the scan converter 11 are written in synchronization with a write request WREQ by the memory controller 122 with a clock signal of 80 MHz, for example. In parallel with the 40 MHz clock and the read request RREQ, in the case of an odd field, as shown in FIG. . . Lines are taken out and output. In the case of an even field, as shown in FIG. . . The line is taken out and output. That is, in the DC-FIFO memory 121, a progressive signal is converted into an interlace signal and output.

As described above, according to the present embodiment, the scan converter 11 that performs predetermined signal processing on an input image signal and outputs the signal as a progressive signal, Based on the corresponding synchronization signal, a write request WREQ instructing to write every other progressive data signal is generated, and based on the divided synchronization signal obtained by dividing the synchronization signal, the write request WREQ is generated in response to the write request. The memory controller 122 generates a read request signal RREQ for instructing to read data to be written, and writes data based on a read request signal while writing every other progressive data signal input based on a write request. data DC-FIFO memory 1 read
Since the output device 21 is provided, even if the output is a progressive scan converter, it can be displayed on an interlaced display device.

When the signal input to the scan converter 11 is an interlaced signal, the signal of the interlaced signal is discriminated as an odd field or an even field, and a parity indicating the discrimination result is obtained. Parity generator 1 for generating a signal
Since the input signal 23 is provided, when the input signal is an interlace signal, the quality of the image can be reduced by matching the polarity of the parity signal used for progressive / interlace conversion with the parity of the input signal.

[0038]

As described above, according to the present invention,
Even when the output is a progressive signal processing circuit, it can be displayed on an interlaced display device.

According to the present invention, when the input signal is an interlace signal, the parity of the parity signal used for the progressive / interlace conversion is matched with the parity of the input signal, so that the deterioration of the image quality can be reduced. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus employing a conversion circuit according to the present invention.

FIG. 2 is a timing chart for explaining a conversion operation in an odd field.

FIG. 3 is a timing chart for explaining a conversion operation in the case of an even field.

FIG. 4 is a horizontal synchronizing signal H-SYN of an interlace signal;
FIG. 6 is a diagram illustrating a relationship between C and a vertical synchronization signal V-SYNC.

[Explanation of symbols]

10 image processing apparatus, 11 scan converter, 12
... Progressive-interlace (PI) conversion circuit
121: DC-FIFO memory, 122: memory controller, 123: parity generator.

Claims (10)

[Claims] 1. A conversion circuit for converting a progressive signal into an interlaced signal, wherein the progressive data signal is written alternately based on a synchronization signal corresponding to the progressive signal. Is generated, and based on the divided synchronization signal obtained by dividing the synchronization signal,
A first circuit for generating a read request signal for instructing to read data to be written in response to the write request; and writing the progressive data signal every other based on the write request by the first circuit. A second circuit for reading data written based on the read request signal. 2. When the progressive signal input to the first circuit is a signal obtained by converting an interlaced signal, a field discrimination as to whether the interlaced signal is an odd field or an even field. And a third circuit that generates a parity signal indicating a determination result and outputs the parity signal to the first circuit. The first circuit corresponds to an odd field or an even field based on the parity signal. 2. The conversion circuit according to claim 1, wherein the conversion circuit generates a data write request and a data read request. 3. The conversion circuit according to claim 2, wherein the third circuit performs the field determination based on a horizontal synchronization signal and a vertical synchronization signal corresponding to an interlaced signal. 4. The third circuit, wherein a progressive signal input to the first circuit is input to the first circuit when the signal is generated based on the progressive signal. 3. The conversion circuit according to claim 2, wherein the parity signal is generated based on a vertical synchronization signal corresponding to a progressive signal. 5. The third circuit, when the progressive signal input to the first circuit is generated based on the progressive signal, the third circuit inputs the signal to the first circuit. 4. The conversion circuit according to claim 3, wherein a parity signal is generated based on a vertical synchronization signal corresponding to the progressive signal. 6. A signal processing circuit which inputs a progressive or interlaced image signal, performs predetermined signal processing and outputs the signal as a progressive signal, and a progressive signal output from the signal processing circuit. Based on the corresponding synchronization signal, generate a write request instructing to write every other progressive data signal, and respond to the write request based on a divided synchronization signal obtained by dividing the synchronization signal. A first circuit for generating a read request signal instructing to read data to be written, and a progressive data signal written by the signal processing circuit based on a write request from the first circuit. And write based on the read request signal. The image processing device having a conversion circuit and a second circuit for reading data I. 7. When the signal input to the signal processing circuit is an interlaced signal, the conversion circuit performs field discrimination as to whether the interlaced signal is an odd field or an even field. And a third circuit for generating a parity signal indicating a determination result and outputting the generated parity signal to the first circuit, wherein the first circuit generates a parity signal corresponding to an odd field or an even field based on the parity signal. 7. The image processing device according to claim 6, wherein a write request and a read request are generated. 8. The image processing apparatus according to claim 7, wherein the third circuit performs the field determination based on a horizontal synchronization signal and a vertical synchronization signal corresponding to an interlaced signal. 9. The third circuit, when the progressive signal input to the first circuit is generated by the signal processing circuit based on the progressive signal, 8. The image processing apparatus according to claim 7, wherein the parity signal is generated based on a vertical synchronization signal corresponding to a progressive signal input to one circuit. 10. The third circuit, when the progressive signal input to the first circuit is generated by the signal processing circuit based on the progressive signal, 8. The image processing apparatus according to claim 7, wherein the parity signal is generated based on a vertical synchronization signal corresponding to a progressive signal input to one circuit.