JP2006184619A - Video display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video display device which does not need to increase a circuit scale, cost and driving electric power in displaying a high vision video signal of a progressive system having 720 pieces of the effective number of scanning lines on a display panel having prescribed vertical resolution different from the effective number of scanning lines. <P>SOLUTION: The video display device 1 is equipped with the display panel 20 which has the prescribed (for example, 540 pieces) vertical resolution different from 720 pieces, and a scaler 14 which applies scaling to the inputted 720p signals using a line memory 13. The video display device 1 interpolates the horizontal scanning lines of the 720p signals to the horizontal scanning lines corresponding to the display panel 20. For example, the 720p signals are converted to 1080p signals by the scaler 14 and thereafter, the signals are thinned out and the video signals for 540 pieces are displayed on the display panel. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a video display device, and more particularly to a video display device that displays a progressive high-definition video signal having 720 effective scanning lines on a display panel having a predetermined vertical resolution.

  In order to display a video source, a video display device using a matrix type display panel such as a liquid crystal panel or a plasma panel is known. For such a video display device, a display panel according to the display standard of a personal computer is usually used. For example, in the case of a display panel of 4: 3 type VGA (640 dots × 480 dots), it consists of 480 rows of pixel columns, and in the case of a display panel of XGA (1024 dots × 768 dots), it consists of 768 rows of pixel columns. .

  On the other hand, the video source format defines 576i for PAL (phase alternation line) video signal, 1080i for HDTV (High Definition TeleVision) video signal, and the like. 576i is an interlace signal having 576 scanning lines, and 1080i is an interlace signal having 1080 scanning lines. That is, the number of scanning lines of the video source is different from the number of rows of pixels of the matrix display panel.

  Therefore, in order to display the video source on the matrix type display panel, it is necessary to perform vertical scaling. In this case, the vertical scaling means that a new horizontal line is calculated by adding / averaging horizontal scanning line signals adjacent to each other at a predetermined ratio in order to convert the number of video scanning lines into the number of vertical pixels of the panel. This is a process for generating a scanning signal. In addition, in order to display the video source on the matrix type display panel, horizontal scaling is performed in combination with vertical scaling.

  FIG. 11 is a diagram showing the main part of the configuration of a video display device for a PAL video source, FIG. 12 is a diagram for explaining the scaling of a standard (SD) video signal of the PAL system, and FIG. It is a figure for demonstrating the scaling of a (HD) video signal. FIG. 11 shows an example of a video display device that displays a PAL video source or a high-definition signal on a W-XGA liquid crystal display panel conforming to the 16: 9 PC standard. In this video display device, the PAL method is shown. Scaling when displaying a standard video signal and a high-definition video signal will be described with reference to FIGS.

  The video display device 100 illustrated in FIG. 11 includes an input switching unit 101 that switches and inputs video signals A, B, and C from a plurality of video sources, an AD converter 102 that converts an analog signal into a digital signal, and a scaling frame memory. 103, a video signal conversion unit 104 that is a scaler that performs video signal conversion processing such as scaling and IP conversion, an image quality enhancement correction unit 105 that performs image quality enhancement correction processing, and an OSD (On Screen Display) control unit 106 that controls on-screen signals. An OSD mixing unit 107 that mixes on-screen signals, a γ correction unit 108 that performs γ correction, a liquid crystal controller 109 that controls a liquid crystal panel, a liquid crystal panel 110, a gate driver 111, and a source driver 112.

  The video signal conversion unit 104 performs video signal conversion processing such as IP conversion, and also uses a scaling frame memory 103 to generate an interlace video signal (hereinafter referred to as 576i signal) having 576 scanning lines if it is a PAL video signal. 768 progressive signals (hereinafter referred to as 768p signals) for scanning lines, and 1080 signals for interlaced video signals (hereinafter referred to as 1080i signals) and 720 progressive signals for high-definition signals. A video signal (hereinafter referred to as a 720p signal) is vertically scaled to a 768p signal. When displaying a PAL video signal by an NTSC video source or a display panel in accordance with a PC display standard, a scaling frame memory 103 is required as a working memory for scaling.

  With reference to FIG. 12, the vertical scaling of the PAL standard video signal will be described. In FIG. 12, reference numeral 123 denotes a pixel column of a 16: 9 type W-XGA (1366 dots × 768 dots) display panel (corresponding to the liquid crystal panel 110 of FIG. 11). This display panel is simply referred to as a W-XGA panel.

  First, the 576i signal 120 is converted into a progressive signal 121 having 547 scanning lines. Hereinafter, the signal thus generated is simply referred to as a 547p signal 121. Here, the number of scanning lines is changed from 576 interlaces to 547 progressives. One line signal is converted from one line to 2 lines by a line memory and converted to a 576p signal. This is because 29 lines were cut for scanning. Next, the 547p signal 121 is converted into a progressive signal (768p signal) 122 having 768 scanning lines by vertical scaling. Since the number of scanning lines is 768, the 768p signal 122 can be displayed on a W-XGA panel having 768 rows of pixel columns. Since the 576i video signal 120 is a 4: 3 type, horizontal scaling is also required to display it on a 16: 9 type display panel.

  Next, the vertical scaling of the 1080i signal will be described with reference to FIG. In FIG. 13, reference numeral 133 schematically represents a pixel column of the W-XGA panel. First, the 1080i signal 130 is converted into a progressive signal 131 having 540 scanning lines. Hereinafter, the signal thus generated is simply referred to as a 540p signal 131. Here, the reason why the number of scanning lines is reduced from 1080 interlaces to progressive 540 lines is that one of the signals in the even field or the odd field is used as one screen signal. Next, the 540p signal 131 is converted into a progressive signal (768p signal) 132 having 768 scanning lines by vertical scaling. Since the number of scanning lines is 768, the 768p signal 132 can be displayed on a W-XGA panel having 768 rows of pixel columns. Since the 1080i video signal is 16: 9 type, when it is displayed on a 16: 9 type display panel, horizontal scaling is not necessary.

As a conventional technique related to a video display device, there is a video signal processing circuit that includes a bell table having an amplitude defined by a SECAM (sequential a memory) system for color difference signals and is compatible with the PAL system, NTSC system, and SECAM system. It has been proposed (see, for example, Patent Document 1). In addition, the phase of the gate pulse is controlled so that the holding period of the voltage accumulated in the signal line is constant based on the period of the horizontal synchronizing signal, and the liquid crystal in which the difference in display quality between the NTSC system and the PAL system is eliminated. A display device has also been proposed (see, for example, Patent Document 2).
JP 2002-185975 A JP-A-5-127621

  However, in such a conventional W-XGA display panel, it is necessary to perform vertical scaling when displaying a PAL video source or a high-vision signal. In this case, the vertical scaling is performed by adding / averaging the horizontal scanning line signals adjacent to each other at a predetermined ratio in order to convert the number of video scanning lines into the number of vertical pixels of the panel. This is a process for generating a signal, and there is a problem that the image is always more blurred than the original video signal.

  Further, when performing such vertical scaling, it is necessary to develop an image for at least one frame on the memory, so that a frame memory is required and the configuration of the scaler is complicated. For example, when a PAL video signal is displayed on a W-XGA display panel, as illustrated in FIG. 11, a video having a relatively large circuit scale for converting an image using the scaling frame memory 103 and the frame memory 103. The signal conversion unit 104 is necessary, which causes an increase in cost.

  Also, recent video display devices display not only conventional video signals with an aspect ratio of 4: 3 but also wide-screen video signals with an aspect ratio of 16: 9 in any system such as the NTSC system and the PAL system. Also need to respond. The number of vertical pixels is optimally the number corresponding to the number of scanning lines in which 4: 3 video signal display signals exist, but by setting the number of horizontal pixels to 16/9 times the number of vertical pixels, It is appropriate to set the aspect ratio of the display panel to 16: 9. Conventionally, there is no PAL display panel corresponding to such a wide video signal having an aspect ratio of 16: 9. For this reason, larger scaling is required, resulting in the influence of the above-described image quality and an increase in cost.

  Furthermore, since the VGA resolution of the PC is close to the number of scanning lines on which the display signal of the NTSC video signal exists, the NTSC signal can easily match the display signal and the panel pixel, but the PAL signal or SECAM can be used. Since signals have different numbers of scanning lines, vertical scaling using a frame memory is required. For this reason, there is a need for a device that displays a display signal and a pixel that are matched by a display panel having the same number of pixels in the vertical direction as that of a PAL or SECAM video signal.

  Further, when a display panel having the number of vertical pixels optimized for 540 PAL signals or SECAM signals (also referred to as vertical resolution or number of lines) is employed, the number of effective scanning lines in the display panel is When displaying more 1080i signals and 720p signals, the resolution is downscaling, so vertical scaling using a frame memory is necessary, and an increase in circuit scale, an increase in cost, and an increase in driving power are inevitable. . If a 1080i signal is to be displayed with 540 lines (or a number close to it) without using a frame memory, the display is possible because both the even field and odd field of 1080i are 540 lines. However, the odd field is displayed at the same position with respect to the even field, and the image displayed on the display panel is blurred in the vertical direction.

  Such a problem is not limited to the display panel having the number of vertical pixels (540 vertical resolutions) optimized for the PAL signal or the SECAM signal, and is different from the number of effective scanning lines of the input video signal. The same occurs when an attempt is made to display on a display panel having a vertical resolution. Therefore, even if an attempt is made to display a 720p signal on a display panel having a vertical resolution different from that of 720 lines, downscaling is required, so vertical scaling using a frame memory is required, increasing the circuit scale and cost. In addition, an increase in driving power is inevitable.

  The present invention has been made in view of the above circumstances, and a display panel having a predetermined vertical resolution that is different from the number of effective scanning lines of a progressive high-definition video signal having 720 effective scanning lines. It is an object of the present invention to provide a video display device that does not require an increase in circuit scale, cost, and driving power when displayed on the screen.

In order to solve the above-described problems, the video display device according to the present invention is configured by the following technical means.
The first technical means is a video display device capable of displaying a progressive high-definition video signal having 720 effective scanning lines, and a display panel having a predetermined vertical resolution different from the effective scanning lines. A scaler that scales the input high-definition video signal using a line memory, and interpolates a horizontal scanning line of the high-definition video signal to a horizontal scanning line corresponding to the display panel by the scaler. It is characterized by.

  The second technical means is a video display device capable of displaying a progressive high-definition video signal having 720 effective scanning lines, and has a vertical resolution of 540 pixels corresponding to the PAL or SECAM system. A display panel and a scaler that scales the input high-definition video signal using a line memory, and the horizontal scan lines of the high-definition video signal corresponding to the display panel are horizontally provided by the scaler. It is characterized in that it is displayed on the display panel by interpolating with scanning lines.

  A third technical means is a video display device capable of displaying a progressive high-definition video signal having 720 effective scanning lines, a display panel having a vertical resolution of 540 pixels, and the input high-definition video signal. A scaler that scales the video signal using a line memory, and interpolates the horizontal scanning lines of the high-definition video signal into 1080 horizontal scanning lines by the scaler, and then the 1080 horizontal scanning lines Of these, 540 horizontal scanning lines corresponding to the display panel are displayed on the display panel.

  According to the present invention, when a progressive type HDTV video signal having 720 effective scanning lines is displayed on a display panel having a predetermined vertical resolution different from the number of effective scanning lines, the circuit scale, cost, and There is no need to increase the driving power.

  The video display device according to the present invention is a device capable of displaying a progressive high-definition video signal (720p signal) having 720 effective scanning lines, and a display panel having a vertical resolution different from the effective scanning lines. And a scaler that scales the input high-definition video signal using a line memory, and mainly inputs and displays a video signal suitable for the vertical resolution.

  For example, a display panel having a vertical resolution of 540 (including the number close to it), that is, a resolution of 540 pixels in the vertical direction can be applied. In this example, the display panel is optimized for a PAL or SECAM video signal. Display panel. In that case, the video display device according to the present invention is a device mainly intended to display a PAL signal or a SECAM signal, and can display a 720p signal without using a frame memory. It becomes that.

  In the video display device according to the present invention, the horizontal scanning lines of the high-definition video signal are interpolated by the scaler into horizontal scanning lines corresponding to the display panel (540 horizontal scanning lines in the above example). By this interpolation, 720 scanning line signals of the high vision signal are converted into 540 scanning line signals of the display panel. This scaler uses a line memory, and the screen size can be easily scaled.

  According to another aspect of the present invention, a display panel having a vertical resolution of 540 pixels is provided, and a horizontal scan line of 720p signal is interpolated into 1080 horizontal scan lines (scan line signals) by a scaler ( It is preferable that 540 horizontal scanning lines are displayed on the display panel by, for example, thinning out 1080 horizontal scanning lines. Hereinafter, the description of the present invention will proceed with the preferred embodiment as a center.

  FIG. 1 is a diagram illustrating a main part in a configuration example of a video display apparatus according to an embodiment of the present invention. Hereinafter, the video display device according to the present embodiment will be described by taking, as an example, a display panel including a liquid crystal panel for a PAL video source having 540 vertical resolutions. The present invention can be similarly applied to a matrix type display device that supports video signals of the SECAM system and other systems. The video display device according to the present invention is also applicable to a PAL or SECAM broadcast receiving device that can receive and display a 720p signal.

  1 includes an input switching unit 11, an AD converter 12, a scaling line memory 13, a simple scaler 14, an image quality enhancement correction unit 15, an OSD control unit 16, an OSD mixing unit 17, and a γ correction unit. 18, a liquid crystal controller 19, a liquid crystal panel 20, a gate driver 21, and a source driver 22. It should be noted that the configuration and connection relationship of each part constituting the video display device 1 is not limited to this.

  The input switching unit 11 includes video signals A, B, C,. . . Change the input. As the video signal input here, for example, a video signal of at least a 720p signal, such as a PAL system, an NTSC system, and an HD system, is selected, and one of them is selected and transmitted to the subsequent stage. The video signal of each system is selected by a tuner, and an arbitrary signal is selected by input switching. Here, an example is given in which the video signal is an analog signal, and the AD converter 12 converts the analog signal selected by switching into a digital signal.

  The simple scaler 14 performs video signal conversion processing such as IP conversion using the scaling line memory 13 and performs simple scaling (to be described later) using the scaling line memory 13 according to the size of the liquid crystal panel 20. Convert the data to a resolution. Although the clock frequency varies depending on the input video signal, the clock frequency is also changed according to this data conversion. Further, when displaying not only the PAL standard signal but also the NTSC standard signal, the PAL method can be displayed by the simple scaler 14 using the scaling line memory 13. When the HD video signal (720p signal or 1080i signal) is displayed on the video display device 1, the PAL system display is performed using the simple scaler 14 and the scaling line memory 13.

  The image quality enhancement correction unit 15 performs image quality enhancement correction processing such as edge enhancement of a video by using a digital filter using only the line direction or several pixels in the vertical and horizontal directions. The OSD control unit 16 performs control to generate an on-screen signal (GUI signal) using built-in font data or bitmap data. The OSD mixing unit 17 mixes on-screen signals representing the fonts and graphics created by the OSD control unit 16 in order to superimpose them on the screen. The γ correction unit 18 adjusts the tone of the video by changing the γ characteristic of the video according to the γ table. The liquid crystal controller 19 controls the liquid crystal panel 20 by converting the video data into signals for driving the liquid crystal panel 20 and outputting the signals to the gate driver 21 and the source driver 22. The gate driver 21 determines which line is to be written by controlling the gate signal of the active matrix of the liquid crystal panel 20. The source driver 22 controls an active matrix source signal of the liquid crystal panel 20.

  The liquid crystal panel 20 has an X and Y matrix structure in which the vertical and horizontal intervals of pixels are equal, and is a matrix type display panel that inputs a scaled video signal and displays a progressive video. is there. The liquid crystal panel 20 has the number of vertical pixels corresponding to the number of horizontal scanning lines in which display signals are present among the PAL horizontal scanning lines. The number of horizontal pixels is, for example, 16 for the number of vertical pixels. The number of pixels corresponding to the number of ratios of / 9 is given.

  Hereinafter, the video signal conversion processing in the simple scaler 14 of the video display device configured as described above will be described.

  FIG. 2 is a diagram for explaining an example of video signal conversion processing when displaying a PAL video signal in the video display apparatus of FIG. 1, and FIG. 3 shows a PAL video signal (even field) for each line of the liquid crystal panel. FIG. 4 is a diagram for explaining a method for assigning a PAL video signal (odd field) to each line of the liquid crystal panel.

  The PAL (or SECAM) video signal is an interlaced video signal having 625 scanning lines, of which 576 scanning lines are used for the video signal. In order to display the video signal (576i signal) 30 on the liquid crystal panel 20 composed of 540 pixel columns, the 576i signal 30 in one field is first subjected to IP conversion using the line memory 13 and scanned. The signal is converted into a progressive signal (hereinafter referred to as a 576p signal) 31 having 576 lines. This IP conversion example is simple vertical scaling for the 576i signal 30 that uses the scaling line memory 13 to increase the number of scanning lines in the field from 288 to 576. Here, the interlace signal is changed to a progressive signal, but the number of scanning lines is not changed, so that complicated vertical scaling is not necessary.

  The 576i signal 30 has 540 effective scanning lines (270 single fields), and the 576p signal 31 also has 540 effective scanning lines. Therefore, it is necessary to perform an overscan process that limits the number of scanning lines input to the line memory 13 to the number of scanning lines (540 lines) that matches the liquid crystal panel 20. By this overscan processing, the 576p signal 31 is converted into a progressive signal (hereinafter referred to as a 540p signal) 32 having 540 scanning lines. The reason why the number of scanning lines is reduced from 576 to 540 is because 6.25% of overscan is cut, and vertical scaling is not necessary here either.

  The 540p signal 32 can be displayed on the liquid crystal panel 20 composed of 540 pixel columns as indicated by reference numeral 33 in FIG. Reference numeral 33 schematically represents a pixel column of a 16: 9 type European standard display panel (960 dots × 540 dots). Hereinafter, this display panel is simply referred to as a wide euro panel. The video display device according to the present invention is not limited to the provision of the wide euro panel. Further, an overscan process may be performed before the IP conversion from the 576i signal 30 to the 576p signal 31, that is, the 576i signal is overscanned and converted into a 540i signal, and then the IP conversion is performed. You may convert into a 540p signal. Further, since the 576i signal 30 is a 4: 3 type, in order to display it on a 16: 9 type wide euro panel, horizontal scaling is required.

  In this way, the PAL video signal is subjected to the IP conversion process and the overscan process using the line memory 13. Also, here, as the simplest IP conversion example, an example in which video signals corresponding to each scanning line are input to a plurality of pixel columns in the liquid crystal panel 20 is shown. In this IP conversion example, the even-field video signal is displayed by two pixel columns in the liquid crystal panel 20 as shown in FIG. 3, and the odd-field video signal is shown in FIG. As shown in FIG. 3, since it is necessary to lower the video signal of the first scanning line by one line, it is necessary to display the video signal corresponding to each scanning line in the liquid crystal panel 20. Are displayed in two pixel columns. Since the video signal of the same scanning line is supplied to the three pixel columns in the odd field, the line memory 13 used in this IP conversion is two lines that can be read and written simultaneously, and 288 lines in the 576i signal. By capturing one line and outputting it at a double clock frequency after capturing, the number of lines is doubled to 576 lines. At this time, the horizontal period of one line is set to half the horizontal period of the 576i signal.

  Here, the panel drive frequency in the liquid crystal panel 20 will be described by taking an euro panel (the number of panel horizontal dots is 960 and the number of panel vertical dots is 540) as an example. A PAL video signal is composed of one field of 270 lines, with a vertical synchronization frequency of 50 Hz and a horizontal synchronization frequency of 15.62 KHz. On the other hand, the liquid crystal panel 20 suitable for the PAL system including the euro panel is configured to display with one field of 540 lines, and has a vertical synchronization frequency of 50 Hz and a horizontal synchronization frequency of 31.25 KHz. Clock) is 40.5 MHz. The total number of vertical clocks is 625.

  The panel drive frequency is determined by the horizontal synchronization frequency and the total number of horizontal clocks. The horizontal total clock number is the number of drive clocks when the horizontal line includes the blanking period, and in the case of the liquid crystal panel 20 suitable for the PAL system, it is 1296 clocks. At the time of the PAL signal (at the time of 576p), the horizontal synchronization frequency is 31.25 KHz, so the panel drive frequency in this case is 31.25 KHz × 1296 = 40.5 MHz.

  FIG. 5 is a diagram for explaining an example of video signal conversion processing when a 720p signal is displayed in the video display device of FIG. 1, and FIG. 6 is a diagram for explaining a method of assigning the 720p signal to each line of the liquid crystal panel. FIG.

  The 720p signal 40 is a progressive video signal (hereinafter referred to as a 750p signal) having 750 scanning lines, of which 720 effective scanning lines exist. In order to display the 720p signal 40 on the liquid crystal panel 20 having 540 pixel columns, the line memory 13 is used, and the 720p signal 40 is first a progressive signal having 1080 scanning lines (hereinafter referred to as a 1080p signal). IP conversion is performed by applying simple vertical scaling to 41 with the simple scaler 14. Then, the 1080p signal 41 is converted into a 540p signal 42 by using an average between two lines using the line memory 13. Alternatively, the 720p signal 40 may be directly converted to the 540p signal 42 by simple vertical scaling with the simple scaler 14. Regardless of which method is adopted, the 720p signal 40 is finally converted to a 540p signal 42 by a simple vertical scaling process, and is composed of 540 pixel columns as indicated by reference numeral 43 in FIG. Display on the liquid crystal panel 20 becomes possible. Reference numeral 43 schematically represents a pixel column of the euro panel. Since the 720p signal 40 is a 16: 9 type, horizontal scaling is also unnecessary when displaying it on a 16: 9 type wide euro panel.

  The line assignment for the 720p signal is illustrated in FIG. 6 and will be described with reference to this. First, the first column of the 1080p signal is an n-line (first line) signal of the 720p signal. The second column of the 1080p signal is a signal obtained by averaging the n line and the n + 1 line of the 720p signal. The third and fourth columns of the 1080p signal are the n + 1 line and the n + 2 line of the 720p signal, respectively, and the fifth column is a signal obtained by averaging the n + 2 line and the n + 3 line. Thereafter, the same is repeated. With respect to the 1080p signal generated in this way, the liquid crystal panel 20 displays the signal of the first column of the 1080p signal (the n line of the 720p signal) in the first column, and the second column is the third column of the 1080p signal. The signal of (n + 1 line of 720p signal) is displayed, and the third column displays the signal of the fifth column of 1080p signal (average of n + 2 line and n + 3 line of 720p signal). Thereafter, the same is repeated.

  In this way, since the four lines of the original 720p signal correspond to the three lines of the liquid crystal panel 20, when the 720p signal is directly converted to the 540p signal by the simple scaler 14, the line memory 13 can be simultaneously written. 4 things are needed. Also, since the four lines of the original 720p signal correspond to the six lines of the 1080p signal and they correspond to the three lines of the liquid crystal panel 20, the simple scaler 14 converts the 720p signal into the 1080p signal and then the 540p signal. When converting into signals, six line memories 13 that can be written simultaneously are required.

  When the 720p signal is displayed by these methods on the PAL type liquid crystal panel 20, the display clock of the liquid crystal panel 20 must be lowered in order to absorb the difference in horizontal synchronization frequency. The 720p signal is composed of one field, 720 lines, and has a vertical synchronization frequency of 50 Hz and a horizontal synchronization frequency of 37.5 KHz. Since the effective video signal (720p) has a horizontal synchronization frequency of 37.5 KHz, assuming that 720 horizontal lines of the 720p signal correspond to the drive time of 540 liquid crystal panels 20, the horizontal synchronization frequency at this time is 37. 5/720 × 540 = 28.1 KHz. On the other hand, since the panel horizontal total clock number is 1296 as described above, the panel drive frequency is 28.1 KHz × 1296 = 36.4 MHz. As described above, the liquid crystal panel 20 lowers the display clock to 40.5 MHz when the PAL signal is displayed and 36.4 MHz when the 720p signal is displayed.

  However, as described above, the 540p horizontal scanning lines are interpolated into 1080 horizontal scanning lines by the simple scaler 14 and then thinned out of the 1080 horizontal scanning lines. Is preferably displayed on the liquid crystal panel 20. In this preferred embodiment, the even-numbered signal of 1080p signal is thinned, so that the same display as in the above example is possible, and only three lines necessary for conversion from 720p signal to 1080p signal are possible. The memory 13 can be configured. This embodiment will be described with reference to FIGS.

  7 is a diagram for explaining another example of the video signal conversion processing when displaying the 720p signal in the video display device of FIG. 1, and FIG. 8 is a diagram showing a timing chart at the time of displaying the PAL signal. FIG. 9 is a diagram illustrating a timing chart when a 720p signal is displayed.

  In order to display the 720p signal 40 on the liquid crystal panel 20 composed of 540 pixel columns, the line memory 13 is used, and the 720p signal 40 is first a progressive signal (hereinafter referred to as 1080p signal) 41 having 1080 scanning lines. By performing simple vertical scaling with the simple scaler 14, IP conversion is performed. In this way, first, the line memory 13 is used to generate one line between adjacent lines by simply averaging the two adjacent lines. Here, the line which becomes the average value of the adjacent lines between the adjacent horizontal lines is generated by interpolation. However, since 2 lines should be 3 lines, instead of interpolating between all the lines, every 2 lines are interpolated. Interpolate. By this operation, the signal becomes 1.5 times substantially 1080p signal, and the horizontal synchronization frequency becomes 1.5 times 56.25 KHz from 37.5 KHz. By this simple vertical scaling processing, the 720p signal 40 is finally converted into a 1080p signal 41, and display on the liquid crystal panel 20 composed of 540 pixel columns is possible as indicated by reference numeral 43 in FIG. Here, by controlling the liquid crystal panel 20 so that 1080p signal lines are simply halved, a pair of 540 line PAL panels (liquid crystal panel 20) is used without additional line processing. 1 can be displayed.

  The line assignment for the 720p signal is as illustrated in FIG. 6, but since the two lines of the original 720p signal correspond to the three lines of the liquid crystal panel 20 in this conversion, the line memory 13 is used. Requires only three that can be written simultaneously. Further, when the 720p signal is displayed by this method on the PAL type liquid crystal panel 20, the display clock of the liquid crystal panel 20 must be increased in order to absorb the difference in horizontal synchronization frequency. The 720p signal is composed of one field, 720 lines, and has a vertical synchronization frequency of 50 Hz and a horizontal synchronization frequency of 37.5 KHz. Since an effective video signal (720p) has a horizontal synchronization frequency of 37.5 KHz, assuming that 720 horizontal lines of the 720p signal correspond to 1080 drive times of the liquid crystal panel 20, the horizontal synchronization frequency at this time is 37. 5/720 × 1080 = 56.25 KHz. On the other hand, since the panel horizontal total clock number is 1296 as described above, the panel drive frequency is 56.25 KHz × 1296 = 72.9 MHz. Thus, the liquid crystal panel 20 raises the display clock to 40.5 MHz when the PAL signal is displayed and 72.9 MHz when the 720p signal is displayed.

  An example of the thinning process will be described with reference to FIGS. The liquid crystal panel 20 of FIG. 1 has an X and Y matrix structure, and the X direction control is performed by the source driver 22 and the Y direction control is performed by the gate driver 21. As will be described with reference to FIG. 8, the RGB signal to be written to the liquid crystal and the liquid crystal drive clock (XCLK) are input to the source driver 22. The gate driver 21 receives an OE signal for controlling whether or not to write, and YCLK for moving the writing line. When a PAL signal (converted to 540p) is input, YCLK enters 1 clock at the start of 1-field display, the first line is designated as the write line, OE becomes active, and a writable state is entered. An RGB signal is input from the source driver 22 for one line, and data is written to the first line designated by the gate driver 21. After writing one line, YCLK enters one clock, and then a line is designated. RGB signals are written. This continues until all lines are written.

  Further, when a 540p signal is displayed by thinning out the 1080p signal, the first line is set as shown in FIG. 9 until OE becomes active and RGB is written in the first line in FIG. Same as described. After the completion of one line, one clock is input to YCLK, the second line is set, and RGB writing is performed. YCLK does not enter in the next line. Therefore, the gate driver 21 still designates the second line of the LCD. In this state, the third line of the video is overwritten on the second line of the LCD. As described above, the hatched line in FIG. 9 is overwritten by the next line. Similarly, since YCLK enters one clock once for two lines of video, it is substantially reduced by half.

  As described above, normally, writing is performed for each line by outputting one clock for each line from the liquid crystal controller 19 to the gate driver 21, and this clock is set to be one clock for two lines of the video signal. Thus, the thinning process can be easily performed by half. At this time, the panel drive frequency is 72.9 MHz, and the horizontal synchronization frequency is 56.25 KHz.

  Finally, a circuit configuration example of the video display device in FIG. 1 will be described with reference to FIG. The liquid crystal panel 20 is mounted on the front surface of the matrix type display device illustrated in FIG. 10, and the power supply substrate 51, the signal input substrate 52, the main substrate 53, the LCD control substrate 54, the inverter substrate 55 for the backlight, An operation switch board 56 is provided.

  The signal input board 52 is provided with an input switching IC 61 corresponding to the input switching unit 11. The main board 53 is provided with an AD converter IC 62 corresponding to the AD converter 12, a video signal conversion memory IC 63 corresponding to the video signal conversion memory 13, and an image processing IC 64. The image processing IC 64 is an IC corresponding to the video signal conversion unit 14, the image quality enhancement correction unit 15, the OSD control unit 16, and the OSD mixing unit 17. The LCD control board 54 is provided with a γ correction IC 65 corresponding to the γ correction unit 18 and a liquid crystal controller IC 66 corresponding to the liquid crystal controller 19. A gate driver 21 and a source driver 22 are further provided on the rear surface of the matrix display device.

  As described above, since the simple scaler 14 in the video display device according to the present invention is suitable for the video signal of the PAL system or the like, the standard (SD) video signal of the PAL system is displayed on the wide euro panel. In this case, the 576i signal is IP converted into a 576p signal and converted into a 540p signal. In addition to the overscan and horizontal scaling, the IP conversion can be performed by simply performing double scaling in the vertical direction. That's it. This video display device only needs to perform simple vertical scaling even when the 720p signal is displayed on the wide euro panel.

  In addition, when displaying an NTSC standard (SD) video signal on a PAL display panel such as a wide Euro panel, the horizontal scanning line of the NTSC video signal is provided by the scaler in the vertical direction. This can be handled by interpolating the horizontal scanning lines corresponding to the display panel. For example, after overscanning a 525i signal and converting it to a 480i signal, IP conversion is performed by simple vertical scaling based on the ratio of the number of scanning lines to the 540p signal with respect to the 480i signal, and other horizontal scaling is performed. It can be applied as needed. Further, when a 1080i signal is displayed on the display panel, simple vertical scaling is performed by changing the 1080i signal to a 540p signal.

  As described above, in the present invention, a simplified scaler that uses only a line memory having a memory capacity much smaller than that of a frame memory that has been conventionally used can be adopted, and the simplification of the circuit is beneficial in terms of scale and cost. In addition, power consumption can be reduced, and an environmentally friendly video display device can be provided. Further, by displaying the horizontal scanning line signal of the video signal so as to match the pixel of the panel, simple scaling is sufficient, and the influence of the image quality due to the scaling can be prevented as much as possible. As described above, according to the present invention, when a 720p signal is displayed on a display panel having a predetermined number of effective scanning lines such as 540, it is not necessary to use a frame memory, and the circuit scale, cost, and driving power are increased. It will not let you.

It is a figure which shows the principal part in the example of 1 structure of the video display apparatus concerning one Embodiment of this invention. FIG. 3 is a diagram for explaining an example of video signal conversion processing when displaying a PAL video signal in the video display device of FIG. 1. It is a figure for demonstrating the allocation method of the PAL video signal (even field) with respect to each line of a liquid crystal panel. It is a figure for demonstrating the allocation method of the PAL video signal (odd field) with respect to each line of a liquid crystal panel. It is a figure for demonstrating the example of a video signal conversion process at the time of displaying a 720p signal in the video display apparatus of FIG. It is a figure for demonstrating the allocation method of the 720p signal with respect to each line of a liquid crystal panel. It is a figure for demonstrating the other example of the video signal conversion process at the time of displaying a 720p signal in the video display apparatus of FIG. It is a figure which shows the timing chart at the time of a PAL signal display. It is a figure which shows the timing chart at the time of 720p signal display. It is a figure which shows the circuit structural example of the video display apparatus of FIG. It is a figure which shows the principal part of the structure of the video display apparatus for the video sources of the conventional PAL system. It is a figure for demonstrating the video signal conversion process of a PAL standard video signal in the conventional matrix type display apparatus of a W-XGA system. It is a figure for demonstrating the video signal conversion process of a high-definition video signal in the conventional matrix type display apparatus of a W-XGA system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Input switching part, 12 ... AD converter, 13 ... Scaling line memory, 14 ... Simple scaler, 15 ... Image quality emphasis correction part, 16 ... OSD control part, 17 ... OSD mixing part, 18 ... γ correction part, 19 ... Liquid crystal controller, 20 ... display panel, 21 ... gate driver, 22 ... source driver.

Claims (3)

  An image display device capable of displaying a progressive-type high-definition video signal having 720 effective scanning lines, the display panel having a predetermined vertical resolution different from the effective scanning lines, and the input high-definition video A scaler that scales a signal using a line memory, and interpolates a horizontal scanning line of the high-definition video signal to a horizontal scanning line corresponding to the display panel by the scaler. .   An image display device capable of displaying a progressive high-definition video signal having 720 effective scanning lines, a display panel having a vertical resolution of 540 pixels corresponding to the PAL or SECAM method, and the input high-definition image A scaler that scales the video signal using a line memory, and the display panel interpolates the horizontal scanning lines of the high-definition video signal into 540 horizontal scanning lines corresponding to the display panel. A video display device characterized by being displayed on the screen.   An image display apparatus capable of displaying a progressive high-definition video signal having 720 effective scanning lines, a display panel having a vertical resolution of 540 pixels, and a line memory for the input high-definition video signal And a scaler that scales using the, and interpolates the horizontal scanning lines of the high-definition video signal into 1080 horizontal scanning lines by the scaler, and then corresponds to the display panel among the 1080 horizontal scanning lines. An image display device, wherein 540 horizontal scanning lines are displayed on the display panel.

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