JP2003324695A - Video display and video format converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video format converter capable of displaying various interlace video signals or progressive video signals while converting the format suitably for a fixed pixel display. <P>SOLUTION: The video format converter comprises a circuit 102 for converting an input video signal from an interlace video signal into a progressive video signal, a circuit 104 for selectively delivering an output signal from the progressive conversion circuit when the input video signal is an interlace video signal or the input video signal when it is a progressive video signal, a scaling circuit 105 for enlarging/reducing a progressive video signal being delivered from the selection circuit to convert the number of vertical lines and the number of horizontal pixels suitably for a display, a circuit 107 for decimating progressive video signals being delivered from the scaling circuit to halve the number of vertical lines thus converting the progressive video signal into an interlace video signal, and a fixed pixel display 108 having an interlace structure for displaying the interlace video signal being delivered from the decimation circuit 107. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for displaying an image on a fixed pixel display device such as a plasma display panel (hereinafter referred to as PDP), and more particularly to an interlaced image signal or a progressive image signal having various formats. The present invention relates to a video display device having a configuration for converting a video signal into a format suitable for (a structure of) a fixed pixel display device, and a video format conversion device.

[0002]

2. Description of the Related Art In recent years, digitization of video sources has progressed, and a liquid crystal display monitor suitable for displaying digital video signals,
Fixed pixel display devices, such as PDPs and DLPs (Digital Light Processing), that perform digital signal processing and display are being commercialized one after another. Particularly in PDPs, progressive display is generally used, but in order to display high-definition broadcasting in high definition, it is necessary to increase the definition of the panel, which causes problems of lower brightness and higher cost. It was

On the other hand, interlace (jump)
ALIS (Alternate Lighting of Surfaces) that realizes high definition by suppressing the cost increase by displaying
Method) method. This method is also effective for increasing the brightness and extending the life of the panel. PDP using this ALIS method
As an example, a product capable of high-definition display having 1024 vertical lines and 1024 horizontal dots has been commercialized, and has been attracting attention in the market.

Further, in order to increase the added value, the fixed pixel display device is required to display a video signal having various formats such as a personal computer signal in addition to an ordinary television signal. Here, examples of video signals having various formats are shown in FIG. As shown in FIG. 6, TV signals, personal computer signals (hereinafter, P
There are various formats of video signals (referred to as C signal). Under such circumstances, it is necessary to convert the video format for displaying the interlaced video signal or the progressive video signal having various formats on the fixed pixel display device.

As a conventional video format conversion, as a video format conversion device for converting a TV signal of an interlaced video signal into an interlaced TV signal of a different format and outputting it, Japanese Patent Laid-Open No. 2000-11572.
An example as described in Japanese Patent Publication No. 2 is given. A conventional video format conversion device will be described below with reference to the drawings. FIG. 5 is a block diagram showing an outline of a configuration example of a conventional video format conversion device. In the conventional video format converter, 501
Is an interlaced video signal input terminal, and 102 is an i for converting the interlaced video signal into a progressive video signal
/ P conversion circuit, 502 is a scaling circuit for converting the number of effective vertical lines and the number of effective horizontal dots of the progressive video signal to enlarge or reduce in the vertical and horizontal directions,
Reference numeral 07 is a thinning circuit for converting a progressive video signal into an interlaced video signal by thinning out the number of effective vertical lines to 1/2, and 503 is an interlaced video signal output terminal.

[0006] As an example, an interlaced video signal of 480i format in which the number of effective vertical lines per field is 240 lines and the number of effective horizontal dots per line is 720 dots, the effective number of vertical lines per field is 540 lines. A case of converting into an interlaced video signal of 1080i format in which the number of effective horizontal dots per line is 1920 will be described.

The 480i format interlaced video signal input from the interlaced video signal input terminal 501 has 480 effective vertical lines per field in the i / p conversion circuit 102 and the effective horizontal dot number per line. Of 720 dots is converted into a progressive video signal of 480p format and output to the scaling circuit 502. Scaling circuit 5
02, the 480 input from the i / p conversion circuit 102
For a progressive video signal of p format, a signal of 480 lines in the vertical direction is interpolated and enlarged 108
Expand to line 0. Further, a signal of 720 dots in the horizontal direction is enlarged to 1920 dots by the same interpolation enlargement processing as in the vertical direction. In this way, the image is enlarged in the vertical direction and the horizontal direction so as to be a progressive video signal of the 1080p format, and is output to the thinning circuit 107. In the thinning circuit 107, the number of effective vertical lines of the 1080p format progressive video signal input from the scaling circuit 502 is halved, and the thinning lines are alternately switched for each field, and thinning is performed in an interlaced structure to form one field. The number of effective vertical lines per line is 540, and the number of effective horizontal dots per line is 1920 dots, which is converted into an interlaced video signal of 1080i format and output to the interlaced video signal output terminal 503. In this way, the 480i format interlaced video signal is converted into the 1080i format interlaced video signal.

[0008]

In the above prior art, the format of the input interlaced video signal is converted and the interlaced video signal is output.
80i, 1080i and other specific TV signals to different TV
Considering only converting to signal format,
No consideration is given to performing the format conversion according to the structure of the fixed pixel display device. Further, in the related art, as an input video signal, only an interlaced video signal which is a specific TV signal such as 480i or 1080i is considered, and a case where a progressive video signal such as a PC signal is input is not considered.

In view of the case where a fixed pixel display device is connected, the present invention converts various interlaced video signals or progressive video signals into a format suitable for a fixed pixel display device and enables display. It is what

[0010]

In order to achieve the above object, the present invention provides an i / p conversion circuit for converting an input video signal from an interlaced video signal to a progressive video signal, the input video signal and the i / p conversion circuit. When the output signal from the p conversion circuit is input and the input video signal is an interlaced video signal, the output signal from the i / p conversion circuit is selected, and when the input video signal is a progressive video signal, the input video signal is selected and output. Selecting circuit, a scaling circuit for performing a scaling process for converting the number of vertical lines and / or the number of horizontal pixels on the progressive video signal output from the selection circuit, and the progressive video scaled by the scaling circuit. And a p / i conversion circuit for converting a signal into an interlaced video signal. It is an butterfly.

Further, a second selection circuit for selecting and outputting either the output signal from the scaling circuit or the output signal from the p / i conversion circuit is provided, and the output signal from the second selection circuit is provided. May be supplied to the fixed pixel display device.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a video display device and a video format conversion device according to the present invention will be described with reference to FIG. In the first embodiment, 101 is a video signal input terminal to which an interlaced video signal or a progressive video signal is input, 102
Is an i / p conversion circuit for converting an interlaced video signal into a progressive video signal, 103 is an attribute of the input video signal (distinguishing between an interlaced structure or a progressive structure, the number of effective vertical lines per field, the number of effective horizontal dots per line) ) Is a video signal detection circuit, 104 is a selection circuit, 105 is a scaling circuit corresponding to a fixed pixel display device for converting the number of effective vertical lines and the number of effective horizontal dots to expand or reduce in the vertical and horizontal directions, and 106 is The microcomputer controls the selection circuit 104 and the scaling circuit 105 corresponding to the fixed pixel display device based on the attributes of the input video signal detected by the video signal detection circuit and the attributes of the interlaced fixed pixel display device. 10
Reference numeral 7 denotes a p / i conversion circuit that converts a progressive video signal into an interlaced video signal, and includes a thinning circuit that converts the progressive video signal into an interlaced video signal by thinning out the effective vertical lines of the progressive video signal to 1/2. Composed of. Reference numeral 108 has an interlaced structure. Interlaced display is realized by repeatedly displaying half of the total vertical lines in the first field in the vertical direction and displaying the remaining half of lines in the next field. It is an interlaced fixed pixel display device. The components designated by the same reference numerals as those in FIG. 5 have the same functions as those in FIG.

Below, an interlaced video signal or a progressive video signal input from the video signal input terminal 101 is interlaced fixed pixel display device 108.
The operation when it is displayed in is described.

First, the case where an interlaced video signal is input will be described. As an example, an interlaced video signal of 480i format, in which the number of effective vertical lines per field is 240 lines and the number of effective horizontal dots per line is 720 dots, the number of vertical lines is 1024 lines and the number of horizontal dots is 1024 dots. The case of displaying on the interlaced fixed pixel display device 108 having the interlaced structure will be described.

The interlaced video signal input from the video signal input terminal 101 is guided to the i / p conversion circuit 102. In the i / p conversion circuit 102, a high-quality 480p image is obtained by interpolating an interlaced video signal between a still image and a moving image between fields and within a field.
Outputs a progressive video signal in the format. i
The output of the / p conversion circuit 102 is led to one input of the selection circuit 104. The interlaced video signal input from the video signal input terminal 101 is input to the other input of the selection circuit 104. Further, the video signal input from the video signal input terminal 101 is input to the video signal detection circuit 103. The video signal detection circuit 103 detects the attribute of the input video signal to have an interlaced structure, the number of effective vertical lines per field is 240, and the number of effective horizontal dots per line is 720. It is detected as a dot. The attributes of these input video signals are transmitted to the microcomputer 106, and the control signal cont1 is transmitted so that the selection circuit 104 selects the output of the i / p conversion circuit 102 from the attributes of the input video signals. Therefore, the scaling circuit 105 includes the i / p conversion circuit 1
48 converted to progressive video signal by 02
Input 0p format progressive video signal.

The progressive video signal input to the scaling circuit 105 is vertically and horizontally expanded so as to fit the interlaced fixed pixel display device 108 at the vertical and horizontal expansion ratios transmitted by the control signal cont2 from the microcomputer 106. Done. The vertical enlargement ratio and the horizontal enlargement ratio are calculated by the microcomputer 106. For example, the microcomputer 106 uses the fixed pixel display device format as
For example, each parameter of the number of vertical lines 1024 and the number of horizontal dots 1024 is stored, and the number of vertical lines of the input video signal detected by the detection circuit 103, the number of horizontal pixels, the number of stored vertical lines and the number of horizontal dots are stored. You may make it calculate each ratio and obtain each expansion rate.

Therefore, if the 480 lines are set to 1024 lines, the microcomputer 106 sets the vertical enlargement ratio 1024.
/ 480 = 32/15 times, when 720 dots are 1024 dots, the horizontal enlargement ratio is 1024/720 = 64.
/ 45 times is calculated and output to the scaling circuit 105 as cont2. The scaling circuit 105 performs enlargement processing according to the horizontal / vertical enlargement ratio indicated by cont2. Therefore, the scaled video signal has 1024 effective vertical lines per field,
The progressive video signal has a 1024p format in which the number of effective horizontal dots per line is 1024. The progressive video signal converted by the scaling circuit 105 is a p / i conversion circuit, that is, a thinning circuit 1
The number of effective vertical lines is halved and the thinning lines are alternately switched for each field to perform thinning processing so as to form an interlaced structure. As a result, it is converted into an interlaced video signal in the 1024i format, which is the display format of the interlaced fixed pixel display device 108, and output, and displayed on the interlaced fixed pixel display device 108.

The conversion of the number of vertical lines when an interlaced video signal is input will be described in detail with reference to FIG. The figure shows the state of vertical lines in each process, the vertical direction shows the vertical direction of the image,
In the horizontal direction, the first field, the second field, and the third field in each process (in FIG. 2, f1, f2, and
It is shown as f3. ) Is shown. The table shown at the bottom of the figure shows 480i, 10 as an example of interlaced signals.
The conversion of the number of lines in the 80i format is shown.

For example, in the case of a 480i format video signal, the number of effective vertical lines is 240, and i /
480, which is progressively converted by the p conversion circuit 102
Become a line. Further, vertical scaling is performed by the scaling circuit 105 corresponding to the fixed pixel display device to make 480 lines to 1024 lines. In the thinning circuit 107, the number of effective vertical lines is halved, and the thinning lines are alternately switched for each field, and thinned out so as to form an interlaced structure, whereby the number of effective vertical lines becomes an interlaced video signal of 512 lines per field.

In the case of a 1080i format video signal, the number of effective vertical lines is 540, and i /
The p conversion circuit 102 performs progressive conversion 108.
It becomes 0 line. Further, vertical scaling is performed by the scaling circuit 105 corresponding to the fixed pixel display device to obtain 1080 lines to 1024 lines. In the thinning circuit 107, the number of effective vertical lines is halved, and the thinning lines are alternately switched for each field, and thinned out so as to form an interlaced structure, whereby the number of effective vertical lines becomes an interlaced video signal of 512 lines per field.

In order to display the input video signal on the interlaced fixed pixel display device as described above, the number of vertical lines is converted to the total number of vertical lines of the interlaced fixed pixel display device 108 by scaling processing, and the number of vertical lines is reduced by the thinning circuit 107 at the subsequent stage. By reducing the number to 1/2, the interlaced video signal can be converted into a signal having an interlaced structure most suitable for the fixed pixel display device.

Next, the case where a progressive video signal is input will be described. As an example, a progressive video signal of SVGA format in which the number of effective vertical lines per field is 600 lines and the number of effective horizontal dots per line is 800 dots, the number of vertical lines is 1024 lines and the number of horizontal dots is 1024 dots. The case of displaying on the interlaced fixed pixel display device 108 having the interlaced structure will be described.

The progressive video signal input from the video signal input terminal 101 has a progressive structure in which the attribute of the input video signal is detected by the video signal detection circuit 103 to determine that the progressive video signal is effective vertical lines per field. It is detected that there are 600 lines and that the number of effective horizontal dots per line is 800 dots.
The attributes of these input video signals are transmitted to the microcomputer 106, and in the selection circuit 104 from the attributes of the input video signals,
To select the input from the video signal input terminal 101,
The control signal cont1 is transmitted. Therefore, the input progressive video signal of the SVGA format is directly input to the scaling circuit 105. Microcomputer 10
6 uses the number of vertical lines and the number of horizontal dots of the detected input video signal to calculate the horizontal / vertical enlargement ratio and outputs it to the scaling circuit 105. The progressive video signal input to the scaling circuit 105 is vertically and horizontally enlarged to fit the interlaced fixed pixel display device 108 according to the vertical and horizontal enlargement ratios indicated by the control signal cont2 output from the microcomputer 106. .

Here, the vertical expansion ratio is 600 lines is 10
1024/600 = 128/7 to be 24 lines
Enlargement processing of 5 times and horizontal enlargement ratio of 1024/800 = 32/25 times is performed so that 800 dots becomes 1024 dots. Therefore, the scaled video signal is a progressive video signal of the 1024p format in which the number of effective vertical lines per field is 1024 lines and the number of effective horizontal dots per line is 1024 dots, and the processing after the thinning circuit 107 is performed as described above. This is the same as when inputting the interlaced video signal of.

The conversion of the number of vertical lines when a progressive video signal is input will be described in detail with reference to FIG. Similar to FIG. 2, the vertical lines in each process are shown. The table at the bottom of the figure shows VGA and SVG as an example of progressive video signals.
It shows conversion of the number of lines in A, XGA, and UXGA formats.

For example, in the case of an SVGA format video signal, the number of effective vertical lines is 600 lines, and the scaling circuit 105 corresponding to the fixed pixel display device performs vertical expansion to make 600 to 1024 lines.
In the thinning circuit 107, the number of effective vertical lines is halved, and the thinning lines are alternately switched for each field, and thinned out so as to form an interlaced structure, whereby the number of effective vertical lines becomes an interlaced video signal of 512 lines per field.

Also in the case of VGA, XGA, and UXGA format video signals, the effective vertical line number is set to 1024 by vertically enlarging or reducing by the scaling circuit 105 corresponding to the fixed pixel display device. Similarly, in the thinning circuit 107, the number of effective vertical lines is halved, and thinning lines are alternately switched for each field. By thinning out so as to form an interlaced structure, the number of effective vertical lines becomes an interlaced video signal of 512 lines per field. To do.

In this way, even when a progressive video signal is input, in order to display it on the interlaced fixed pixel display device, it is converted to the total number of vertical lines of the interlaced fixed pixel display device 108 by scaling processing,
The thinning circuit 107 in the subsequent stage reduces the number of vertical lines to 1 /
By setting the value to 2, the progressive video signal can be a signal having an interlace structure most suitable for the fixed pixel display device.

From the above, in the present embodiment,
Whether an interlaced video signal or a progressive video signal with various formats is input,
It is possible to convert to a video format most suitable for a fixed pixel display device having an interlaced structure, and it is possible to realize full-screen display at all times. In addition, the interlaced video signal can be displayed while maintaining high image quality by converting the interlaced video signal into interlace after scaling into a progressive video signal by i / p conversion.

In the present embodiment, the fixed pixel display device has been described with the number of vertical lines being 1024 lines and the number of horizontal dots being 1024 dots, but it is not particularly limited, and a fixed pixel display device having an interlaced structure is used. On the other hand, the same effect can be obtained.

A second embodiment of the video format conversion apparatus according to the present invention will be described with reference to FIG. In the second embodiment shown in FIG. 4, 401 is a second selection circuit, 402 is an attribute input terminal of a fixed pixel display device, and 403.
Is a microcomputer for controlling the selection circuit, the scaling circuit corresponding to the fixed pixel display device, and the second selection circuit from the attribute of the input video signal detected in the video signal detection circuit and the attribute of the fixed pixel display device, and 404 is an interlaced structure or a progressive structure It is a fixed pixel display device having. The components designated by the same reference numerals as those in FIG. 1 have the same functions as those in FIG.

In the first embodiment, only the interlaced fixed pixel display device having the interlaced structure is connected as the fixed pixel display device, but in the present embodiment, the fixed pixel display device having the interlaced structure or the progressive structure is connected. Either can be connected.

First, the case where the fixed pixel display device 404 has an interlaced structure will be described. The attributes of the fixed pixel display device (discrimination of interlaced structure or progressive structure, number of vertical lines, number of horizontal dots) input from the attribute input terminal 402 of the fixed pixel display device are given to the microcomputer 403. If the fixed pixel display device 404 has an interlaced structure,
The control signal cont3 is transmitted so that the selection circuit 401 selects the output of the thinning circuit 107. In this case, the operation is the same as that of the first embodiment, so detailed description will be omitted.

Next, a case where the fixed pixel display device 404 has a progressive structure will be described. When the fixed pixel display device 404 has a progressive structure, the microcomputer 403 controls the control signal cont3 so that the second selection circuit 401 selects the output of the scaling circuit 105.
To send. As an example, a case where an interlaced video signal of 480i format is displayed on a fixed pixel display device 404 having a progressive structure with 768 vertical lines and 1024 horizontal dots will be described.

The operation until the interlaced video signal input from the video signal input terminal 101 is input to the scaling circuit 105 is the same as that in the first embodiment. Therefore, whether the video signal input from the video signal input terminal 101 is an interlaced video signal or a progressive video signal, the scaling circuit 10
5, a progressive video signal of 480p format is input. The progressive video signal input to the scaling circuit 105 is vertically and horizontally enlarged so as to match the fixed pixel display device 404 at the vertical and horizontal enlargement ratios indicated by the control signal cont2 from the microcomputer 403. The calculation method of the horizontal / vertical enlargement ratio is the same as that of the first embodiment described above. Here, the vertical enlargement ratio is 76 so that 480 lines becomes 768 lines.
8/480 = 8/5 times, horizontal enlargement ratio 720 dots is 1
1024/720 = 64/4 so that it becomes 024 dots
Enlargement processing of 5 times is performed. Therefore, the scaled video signal has an effective vertical line count of 76 per field.
8, a progressive video signal of XGA format in which the number of effective horizontal dots per line is 1024 dots. As described above, the scaling method in the vertical direction is the same as when the fixed pixel display device 404 has the interlaced structure, and the number of effective vertical lines per field is converted into the total number of vertical lines of the fixed pixel display device. Furthermore, since the output of the scaling circuit 105 is selected in the second selection circuit 401, the progressive video signal output from the scaling circuit 105 is output to the fixed pixel display device 404 as it is and displayed. With the display method as described above, the input video signal can be converted into the optimum format for the fixed pixel display device having the progressive structure.

From the above, in the present embodiment, for various interlaced video signals or progressive video signal inputs, the fixed pixel display device is not limited to the fixed pixel display device having the interlaced structure, and the fixed pixel display device having the progressive structure. Even when the device is connected, the input video signal can be converted into the optimum format for the fixed pixel display device, and the optimum display can be always realized to fill the screen. In addition, the interlaced video signal is converted into interlace in the case of a fixed pixel display device having an interlace structure after scaling into a progressive signal by i / p conversion, and is output as it is in the case of a fixed pixel display device having a progressive structure. As a result, it is possible to display while maintaining high image quality.

As the fixed pixel display device, the number of vertical lines is 768 lines and the number of horizontal dots is 1024 dots, but the fixed pixel display device is not particularly limited, and the same effect can be obtained for a fixed pixel display device having a progressive structure. Can be obtained.

[0038]

As described above, according to the video format conversion apparatus of the present invention, even if various interlaced video signals or progressive video signals are input, the video format conversion apparatus converts the video format into the optimum video format for the fixed pixel display device. It is possible to realize full screen display. In addition, the interlaced video signal is converted into interlace in the case of a fixed pixel display device having an interlace structure after scaling into a progressive signal by i / p conversion, and is output as it is in the case of a fixed pixel display device having a progressive structure. As a result, it is possible to display while maintaining high image quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a change in the number of effective vertical lines of a video signal when an interlaced video signal is input according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a change in the number of effective vertical lines of a video signal when a progressive video signal is input according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing an outline of a configuration of a conventional video format conversion device.

FIG. 6 is a diagram showing an example of a signal format of a television signal or a PC signal.

[Explanation of symbols]

101 ... Video signal input terminal, 102 ... i / p conversion circuit,
103 ... Video signal detection circuit, 104 ... Selection circuit, 105
... Scaling circuit, 106 ... Microcomputer, 107 ... Thinning circuit, 108 ... Interlaced fixed pixel display device, 4
01 ... Second selection circuit, 402 ... Attribute input terminal of fixed pixel display device, 403 ... Microcomputer, 404 ... Fixed pixel display device, 501 ... Interlaced video input terminal, 502 ...
Scaling circuit, 503 ... Interlaced video output terminal.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 5/00 G09G 5/00 510S 510 H04N 5/66 101B 5/391 G09G 5/00 520V H04N 5/66 101 (72) Inventor Takaaki Matono 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Digital Media Division, Hitachi, Ltd. (72) Inventor Haruki Takada 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Hitachi, Ltd. Factory Digital Media Division (72) Inventor Katsunobu Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Digital Media Division (72) Inventor Ryo Hasegawa 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa F-term in Digital Media Division, Hitachi, Ltd. (Reference) 5C058 AA11 BA04 BA05 BB15 BB17 5C063 AA02 AA07 AA11 BA01 BA04 BA06 BA08 BA09 CA01 CA23 CA36 5C080 AA05 AA06 AA10 BB05 DD21 EE19 FF09 GG07 GG08 JJ02 5C082 AA01 AA02 BA02 BA12 BA41 BC06 BD02 CA81 CA84 CB01 MM06

Claims (9)

[Claims] 1. An i / p conversion circuit for converting an input video signal from an interlaced video signal to a progressive video signal, and an input signal to which the input video signal and an output signal from the i / p conversion circuit are input, and the input video signal is interlaced. In the case of a video signal, an output signal from the i / p conversion circuit is selected, and in the case of a progressive video signal, a selection circuit that selects and outputs the input video signal; and a progressive video signal output from the selection circuit. On the other hand, a scaling circuit that performs a scaling process for converting the number of vertical lines and / or the number of horizontal pixels, and a p / i conversion circuit that converts the progressive video signal that has been scaled by the scaling circuit into an interlaced video signal, An image displaying the interlaced video signal output from the p / i conversion circuit. A fixed pixel display device having an interlaced structure, and a video display device. 2. An i / p conversion circuit for converting an input video signal from an interlaced video signal to a progressive video signal, and an input signal to which the input video signal and an output signal from the i / p conversion circuit are input, and the input video signal is interlaced. A first selection circuit that selects the output signal from the i / p conversion circuit in the case of a video signal, and selects and outputs the input video signal in the case of a progressive video signal, and a progressive signal output from the selection circuit. A scaling circuit for performing a scaling process for converting the number of vertical lines and / or the number of horizontal pixels for a video signal, and a p / i conversion circuit for converting the progressive video signal scaled by the scaling circuit into an interlaced video signal And an output signal from the scaling circuit and from the p / i conversion circuit The second which selects and outputs one of the output signals
And a fixed pixel display device for displaying an output signal from the second selection circuit. 3. The scaling circuit performs the scaling processing by interpolating the number of vertical lines and / or the number of horizontal pixels of the progressive video signal output from the selection circuit. The image display device described. 4. The p / i conversion circuit includes a thinning circuit for performing a thinning process for reducing the number of vertical scanning lines of the progressive video signal scaled by the scaling circuit to ½. The video display device according to claim 1. 5. The image display device according to claim 1, wherein
Further, a detection circuit for detecting whether the input video signal is an interlaced video signal or a progressive video signal, and if the detection circuit detects an interlaced video signal, the i
A video display device, comprising: a control circuit for controlling the selection circuit so that the output signal of the / p conversion circuit selects the input video signal when a progressive video signal is detected. 6. The image display device according to claim 2,
Further, a detection circuit for detecting whether the input video signal is an interlaced video signal or a progressive video signal, and if the detection circuit detects an interlaced video signal, the i
The output signal of the / p conversion circuit has a control circuit for controlling the first selection circuit so as to select the input video signal when a progressive video signal is detected, and the control circuit further comprises: Attribute information indicating whether the fixed pixel display device has an interlace structure or a progressive structure is input, and when the attribute information indicates the interlace structure, the output signal of the p / i conversion circuit is output, and when the attribute information indicates the progressive structure. An image display device, wherein the second selection circuit is controlled so as to select an output of the scaling circuit. 7. The control circuit outputs a horizontal / vertical magnification ratio according to the format of the fixed pixel display device to the scaling circuit, and the scaling circuit responds to the horizontal / vertical magnification ratio from the control circuit. The image display device according to claim 5, wherein the scaling processing is performed by using the image display device. 8. An i / p conversion circuit for converting an input video signal from an interlaced video signal to a progressive video signal; an input video signal and an output signal from the i / p conversion circuit are input, and the input video signal is interlaced. In the case of a video signal, an output signal from the i / p conversion circuit is selected, and in the case of a progressive video signal, a selection circuit that selects and outputs the input video signal; and a progressive video signal output from the selection circuit. On the other hand, a scaling circuit for performing a scaling process for converting the number of vertical lines and / or the number of horizontal pixels, and a fixed pixel display device having an interlaced structure by converting the progressive video signal scaled by the scaling circuit into an interlaced video signal. And a p / i conversion circuit for supplying the Video format conversion device. 9. An i / p conversion circuit for converting an input video signal from an interlaced video signal to a progressive video signal, and an input video signal interlaced with the input video signal and an output signal from the i / p conversion circuit. A first selection circuit that selects the output signal from the i / p conversion circuit in the case of a video signal, and selects and outputs the input video signal in the case of a progressive video signal, and a progressive signal output from the selection circuit. A scaling circuit for performing a scaling process for converting the number of vertical lines and / or the number of horizontal pixels for a video signal, and a p / i conversion circuit for converting the progressive video signal scaled by the scaling circuit into an interlaced video signal And an output signal from the scaling circuit and from the p / i conversion circuit And a second selection circuit for selecting any one of the output signals and supplying it to the fixed pixel display device.