JP2006186958A - Video display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video display apparatus for displaying a video signal adopting the interlace system using a prescribed number of effective scanning lines such as a 1080i signal on a display panel with a vertical resolution equal to or close to a half the number of effective scanning lines without causing a blur to video information due to scaling in the vertical direction and without increasing the circuit scale, the cost and the drive power. <P>SOLUTION: The video display apparatus 1 includes: the display panel 20; and a scaler 14 that uses a line memory 13 for applying scaling to a received interlace signal with the prescribed number of effective scanning lines. The scaler 14 of the video display apparatus 1 applies no scaling to one field of the interlace signal but applies scaling to the other field by a scaling method of averaging intervals of adjacent horizontal scanning lines, and the resulting signal is displayed on the display panel 20. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a video display device, and more particularly, a video display for displaying an interlaced video signal having a predetermined number of effective scanning lines on a display panel having a vertical resolution close to half of the number of effective scanning lines or close thereto. Relates to the device.

  In order to display a video source, a video display device using a matrix type display panel such as a liquid crystal panel or a plasma panel is known. For such a video display device, a display panel according to the display standard of a personal computer is usually used. For example, in the case of a display panel of 4: 3 type VGA (640 dots × 480 dots), it consists of 480 rows of pixel columns, and in the case of a display panel of XGA (1024 dots × 768 dots), it consists of 768 rows of pixel columns. .

  On the other hand, the video source format defines 576i for PAL (phase alternation line) video signal, 1080i for HDTV (High Definition TeleVision) video signal, and the like. 576i is an interlace signal having 576 scanning lines, and 1080i is an interlace signal having 1080 scanning lines. That is, the number of scanning lines of the video source is different from the number of rows of pixels of the matrix display panel.

  Therefore, in order to display the video source on the matrix type display panel, it is necessary to perform vertical scaling. In this case, the vertical scaling means that a new horizontal line is calculated by adding / averaging horizontal scanning line signals adjacent to each other at a predetermined ratio in order to convert the number of video scanning lines into the number of vertical pixels of the panel. This is a process for generating a scanning signal. In addition, in order to display the video source on the matrix type display panel, horizontal scaling is performed in combination with vertical scaling.

  FIG. 10 is a diagram showing a main part of the configuration of a video display device for a PAL video source, FIG. 11 is a diagram for explaining scaling of a PAL standard (SD) video signal, and FIG. It is a figure for demonstrating the scaling of a (HD) video signal. FIG. 10 shows an example of a video display device that displays a PAL video source or a high-definition signal on a W-XGA liquid crystal display panel according to the 16: 9 PC standard. Scaling when displaying the standard video signal and the high-definition video signal will be described with reference to FIGS.

  An image display device 100 illustrated in FIG. 10 includes an input switching unit 101 that switches and inputs video signals A, B, and C from a plurality of video sources, an AD converter 102 that converts an analog signal into a digital signal, and a scaling frame memory. 103, a video signal conversion unit 104 that is a scaler that performs video signal conversion processing such as scaling and IP conversion, an image quality enhancement correction unit 105 that performs image quality enhancement correction processing, and an OSD (On Screen Display) control unit 106 that controls on-screen signals. An OSD mixing unit 107 that mixes on-screen signals, a γ correction unit 108 that performs γ correction, a liquid crystal controller 109 that controls a liquid crystal panel, a liquid crystal panel 110, a gate driver 111, and a source driver 112.

  The video signal conversion unit 104 performs video signal conversion processing such as IP conversion, and also uses a scaling frame memory 103 to generate an interlace video signal (hereinafter referred to as 576i signal) having 576 scanning lines if it is a PAL video signal. Are vertically scaled to 768 progressive signals (hereinafter referred to as 768p signals), and, if a high-definition signal, 1080 interlaced video signals (hereinafter referred to as 1080i signals) to 768p signals. . When displaying a PAL video signal by an NTSC video source or a display panel in accordance with a PC display standard, a scaling frame memory 103 is required as a working memory for scaling.

  With reference to FIG. 11, the vertical scaling of the PAL standard video signal will be described. In FIG. 11, reference numeral 123 denotes a pixel column of a 16: 9 type W-XGA (1366 dots × 768 dots) display panel (corresponding to the liquid crystal panel 110 of FIG. 10). This display panel is simply referred to as a W-XGA panel.

  First, the 576i signal 120 is converted into a progressive signal 121 having 547 scanning lines. Hereinafter, the signal thus generated is simply referred to as a 547p signal 121. Here, the number of scanning lines is changed from 576 interlaces to 547 progressives. One line signal is converted from one line to 2 lines by a line memory and converted to a 576p signal. This is because 29 lines were cut for scanning. Next, the 547p signal 121 is converted into a progressive signal (768p signal) 122 having 768 scanning lines by vertical scaling. Since the number of scanning lines is 768, the 768p signal 122 can be displayed on a W-XGA panel having 768 rows of pixel columns. Since the 576i video signal 120 is a 4: 3 type, horizontal scaling is also required to display it on a 16: 9 type display panel.

  Next, vertical scaling of a high-definition (HD) video signal will be described with reference to FIG. In FIG. 12, reference numeral 133 schematically represents a pixel column of the W-XGA panel. First, the 1080i signal 130 is converted into a progressive signal 131 having 540 scanning lines. Hereinafter, the signal thus generated is simply referred to as a 540p signal 131. Here, the reason why the number of scanning lines is reduced from 1080 interlaces to progressive 540 lines is that one of the signals in the even field or the odd field is used as one screen signal. Next, the 540p signal 131 is converted into a progressive signal (768p signal) 132 having 768 scanning lines by vertical scaling. Since the number of scanning lines is 768, the 768p signal 132 can be displayed on a W-XGA panel having 768 rows of pixel columns. Since the 1080i video signal is 16: 9 type, when it is displayed on a 16: 9 type display panel, horizontal scaling is not necessary.

  The vertical scaling for the 1080i signal will be described with reference to FIG. The vertical scaling for the high-definition signal is executed using the frame memory 103 of FIG. 10 when the method of using one of the even-field signal and the odd-field signal as one screen signal is not adopted. When generating the 540p signal 131 as shown in FIG. 12, the odd field and even field of the 1080i signal are mixed on the frame memory 103. The 540p signal generated here is, for example, an average value of both fields. If the even field is composed of 540 scanning lines of n to n + 539 and the odd field is composed of 540 scanning lines of m to m + 539, the generated 540p signal is generated from above the pixel column of the display panel (( n) + (m)) / 2, ((n + 1) + (m + 1)) / 2, ((n + 2) + (m + 2)) / 2,. . . It becomes. That is, the content of the display line at 540p is the average of the even field and odd field lines of the 1080i signal. Here, (n + 1) or the like indicates the video signal of that line.

As a conventional technique related to a video display device, there is a video signal processing circuit that includes a bell table having an amplitude defined by a SECAM (sequential a memory) system for color difference signals and is compatible with the PAL system, NTSC system, and SECAM system. It has been proposed (see, for example, Patent Document 1). In addition, liquid crystal in which the phase of the gate pulse is controlled so that the holding period of the voltage accumulated in the signal line is constant based on the period of the horizontal synchronizing signal, and the difference in display quality between the NTSC system and the PAL system is eliminated. A display device has also been proposed (see, for example, Patent Document 2).
JP 2002-185975 A JP-A-5-127621

  However, in such a conventional W-XGA display panel, it is necessary to perform vertical scaling when displaying a PAL video source or a high-vision signal. In this case, the vertical scaling is performed by adding / averaging the horizontal scanning line signals adjacent to each other at a predetermined ratio in order to convert the number of video scanning lines into the number of vertical pixels of the panel. This is a process for generating a signal, and there is a problem that the image is always more blurred than the original video signal.

  Further, when performing such vertical scaling, it is necessary to develop an image for at least one frame on the memory, so that a frame memory is required and the configuration of the scaler is complicated. For example, when a PAL video signal is displayed on a W-XGA display panel, as illustrated in FIG. 10, a video having a relatively large circuit scale for converting an image using the scaling frame memory 103 and the frame memory 103. The signal conversion unit 104 is necessary, which causes an increase in cost.

  In addition, recent video display devices display not only conventional video signals with an aspect ratio of 4: 3 but also wide video signals with an aspect ratio of 16: 9 in any system such as the NTSC system and the PAL system. Also need to respond. The number of vertical pixels is optimally the number corresponding to the number of scanning lines in which 4: 3 video signal display signals exist, but by setting the number of horizontal pixels to 16/9 times the number of vertical pixels, It is appropriate to set the aspect ratio of the display panel to 16: 9. Conventionally, there is no PAL display panel corresponding to such a wide video signal having an aspect ratio of 16: 9. For this reason, larger scaling is required, resulting in the influence of the above-described image quality and an increase in cost.

  Furthermore, since the VGA resolution of the PC is close to the number of scanning lines on which the display signal of the NTSC video signal exists, the NTSC signal can easily match the display signal and the panel pixel, but the PAL signal or SECAM can be used. Since signals have different numbers of scanning lines, vertical scaling using a frame memory is required. For this reason, there is a need for a device that displays a display signal and a pixel that are matched by a display panel having the same number of pixels in the vertical direction as that of a PAL or SECAM video signal.

  Further, when a display panel having the number of vertical pixels optimized for 540 PAL signals or SECAM signals (also referred to as vertical resolution or number of lines) is employed, the number of effective scanning lines in the display panel is When displaying a larger number of 1080i signals, since the resolution is downscaling, vertical scaling using a frame memory is necessary, and an increase in circuit scale, an increase in cost, and an increase in driving power are inevitable. Further, when an attempt is made to display a 1080i signal with 540 lines (or a number close to it) without using a frame memory, the display is possible because both the even field and the odd field of 1080i are 540 lines. The odd field is displayed at the same position with respect to the even field, and the image displayed on the display panel is blurred in the vertical direction.

  Such a problem is not limited to a display panel having the number of vertical pixels optimized for a PAL signal or a SECAM signal. An interlaced video signal having a predetermined number of effective scanning lines is converted to the number of effective scanning lines. The same occurs when an attempt is made to display on a display panel having a vertical resolution half or close to that.

  The present invention has been made in view of the above circumstances, and an interlaced video signal having a predetermined number of effective scanning lines, such as a 1080i signal, has a vertical resolution close to half or half of the number of effective scanning lines. It is an object of the present invention to provide a video display device that does not blur video information due to vertical scaling and does not increase circuit scale, cost, and driving power when displayed on a display panel.

  In order to solve the above-described problems, the video display device according to the present invention is a video display device capable of displaying an interlaced video signal having a predetermined number of effective scanning lines, and the effective scanning lines of the video signal. A display panel having a vertical resolution close to half or half of the number, and a scaler that scales the input video signal using a line memory, and scales and displays the scale on the display panel using the scaler. It is a feature. Here, one field of the video signal is displayed on the display panel without being scaled by the scaler, and the other field of the video signal is adjacently scanned by the scaler. You may make it display on the said display panel by giving the scaling which averages between lines.

  According to the present invention, when an interlaced video signal having a predetermined effective scanning line number such as a 1080i signal is displayed on a display panel having a vertical resolution close to half or half the effective scanning line number, The video information is not blurred by scaling, and the circuit scale, cost, and driving power are not increased.

  The video display device according to the present invention is a device capable of displaying an interlaced video signal having a predetermined number of effective scanning lines, and is input to a display panel having a vertical resolution close to half of the number of effective scanning lines or close thereto. The video signal is provided with a scaler that scales the video signal using a line memory, and is mainly for inputting and displaying a video signal suitable for the vertical resolution. For example, when a 1080i signal is applied as an interlace signal having such a predetermined number of effective scanning lines, a display panel having a vertical resolution close to 540 or close to that can be applied. The display panel in this example may be a display panel optimized for a PAL or SECAM video signal. In that case, the video display device according to the present invention mainly displays a PAL signal or a SECAM signal. In addition, the 1080i signal can be displayed without using a frame memory and without causing blurring of the image.

  The video display apparatus according to the present invention displays one field of the interlace video signal having the predetermined effective scanning line number on the display panel without performing scaling with the scaler, These fields are displayed on the display panel after being scaled for averaging between adjacent horizontal scanning lines by the scaler. This scaler uses a line memory, and the screen size can be easily scaled.

  FIG. 1 is a diagram illustrating a main part in a configuration example of a video display apparatus according to an embodiment of the present invention. Hereinafter, the video display device according to the present embodiment is a device capable of displaying an interlaced video signal (1080i signal) having 1080 effective scanning lines, and has a vertical resolution close to or half the effective scanning lines. A display panel having a liquid crystal panel for a PAL video source as an example will be described. However, for other matrix type display devices such as a plasma panel, the SECAM method and other Even if it corresponds to the video signal of a system, it is applicable similarly. The video display device according to the present invention is also applicable to a PAL or SECAM broadcast receiving device that can receive and display HD signals such as 1080i signals.

  1 includes an input switching unit 11, an AD converter 12, a scaling line memory 13, a simple scaler 14, an image quality enhancement correction unit 15, an OSD control unit 16, an OSD mixing unit 17, and a γ correction unit. 18, a liquid crystal controller 19, a liquid crystal panel 20, a gate driver 21, and a source driver 22. It should be noted that the configuration and connection relationship of each part constituting the video display device 1 is not limited to this.

  The input switching unit 11 includes video signals A, B, C,. . . Change the input. The video signal input here is a video signal having a predetermined number of scanning lines, for example, a PAL system, an NTSC system, an HD system, etc., and one of them is selected and sent to the subsequent stage. The video signal of each system is selected by a tuner, and an arbitrary signal is selected by input switching. Here, an example is given in which the video signal is an analog signal, and the AD converter 12 converts the analog signal selected by switching into a digital signal.

  The simple scaler 14 performs video signal conversion processing such as IP conversion using the scaling line memory 13 and performs simple scaling (to be described later) using the scaling line memory 13 according to the size of the liquid crystal panel 20. Convert the data to a resolution. Although the clock frequency varies depending on the input video signal, the clock frequency is also changed according to this data conversion. Further, when displaying not only the PAL standard signal but also the NTSC standard signal, the PAL method can be displayed by the simple scaler 14 using the scaling line memory 13. When the HD video signal (1080i signal) is displayed on the video display device 1, the PAL display is performed using the simple scaler 14 and the scaling line memory 13.

  The image quality enhancement correction unit 15 performs image quality enhancement correction processing such as edge enhancement of a video by using a digital filter using only the line direction or several pixels in the vertical and horizontal directions. The OSD control unit 16 performs control to generate an on-screen signal (GUI signal) using built-in font data or bitmap data. The OSD mixing unit 17 mixes on-screen signals representing the fonts and graphics created by the OSD control unit 16 in order to superimpose them on the screen. The γ correction unit 18 adjusts the tone of the video by changing the γ characteristic of the video according to the γ table. The liquid crystal controller 19 controls the liquid crystal panel 20 by converting the video data into signals for driving the liquid crystal panel 20 and outputting the signals to the gate driver 21 and the source driver 22. The gate driver 21 determines which line is to be written by controlling the gate signal of the active matrix of the liquid crystal panel 20. The source driver 22 controls an active matrix source signal of the liquid crystal panel 20.

  The liquid crystal panel 20 has an X and Y matrix structure in which the vertical and horizontal intervals of pixels are equal, and is a matrix type display panel that inputs a scaled video signal and displays a progressive video. is there. The liquid crystal panel 20 has the number of vertical pixels corresponding to the number of horizontal scanning lines in which display signals are present among the PAL horizontal scanning lines. The number of horizontal pixels is, for example, 16 for the number of vertical pixels. The number of pixels corresponding to the number of ratios of / 9 is given. The X direction control is performed by the source driver 22, and the Y direction control is performed by the gate driver 21. The source driver 22 receives RGB signals to be written to the liquid crystal and a liquid crystal drive clock (XCLK). The gate driver 21 receives an OE signal for controlling whether or not to write, and YCLK for moving the writing line. When a PAL signal (converted to 540p) is input, YCLK enters 1 clock at the start of 1-field display, the first line is designated as the write line, OE becomes active, and a writable state is entered. An RGB signal is input from the source driver 22 for one line, and data is written to the first line designated by the gate driver 21. After writing one line, YCLK enters one clock, and then a line is designated. RGB signals are written. This continues until all lines are written.

  Hereinafter, the video signal conversion processing in the simple scaler 14 of the video display device configured as described above will be described.

  FIG. 2 is a diagram for explaining an example of video signal conversion processing when displaying a PAL video signal in the video display apparatus of FIG. 1, and FIG. 3 shows a PAL video signal (even field) for each line of the liquid crystal panel. FIG. 4 is a diagram for explaining a method for assigning a PAL video signal (odd field) to each line of the liquid crystal panel.

  The PAL (or SECAM) video signal is an interlaced video signal having 625 scanning lines, of which 576 scanning lines are used for the video signal. In order to display the video signal (576i signal) 30 on the liquid crystal panel 20 composed of 540 pixel columns, the 576i signal 30 in one field is first subjected to IP conversion using the line memory 13 and scanned. The signal is converted into a progressive signal (hereinafter referred to as a 576p signal) 31 having 576 lines. This IP conversion example is simple vertical scaling for the 576i signal 30 that uses the scaling line memory 13 to increase the number of scanning lines in the field from 288 to 576. Here, the interlace signal is changed to a progressive signal, but the number of scanning lines is not changed, so that complicated vertical scaling is not necessary.

  The 576i signal 30 has 540 effective scanning lines (270 single fields), and the 576p signal 31 also has 540 effective scanning lines. Therefore, it is necessary to perform an overscan process that limits the number of scanning lines input to the line memory 13 to the number of scanning lines (540 lines) that matches the liquid crystal panel 20. By this overscan processing, the 576p signal 31 is converted into a progressive signal (hereinafter referred to as a 540p signal) 32 having 540 scanning lines. The reason why the number of scanning lines is decreased from 576 to 540 is because the overscan of 6.25% is performed, and vertical scaling is not necessary here either.

  The 540p signal 32 can be displayed on the liquid crystal panel 20 composed of 540 pixel columns as indicated by reference numeral 33 in FIG. Reference numeral 33 schematically represents a pixel column of a 16: 9 type European standard display panel (960 dots × 540 dots). Hereinafter, this display panel is simply referred to as a wide euro panel. The video display device according to the present invention is not limited to the provision of the wide euro panel. Further, since the 576i signal 30 is a 4: 3 type, in order to display it on a 16: 9 type wide euro panel, horizontal scaling is required.

  In this way, the PAL video signal is subjected to the IP conversion process and the overscan process using the line memory 13. Also, here, as the simplest IP conversion example, an example in which video signals corresponding to each scanning line are input to a plurality of pixel columns in the liquid crystal panel 20 is shown. In this IP conversion example, the even-field video signal is displayed by two pixel columns in the liquid crystal panel 20 as shown in FIG. 3, and the odd-field video signal is shown in FIG. As shown in FIG. 3, since it is necessary to lower the video signal of the first scanning line by one line, it is necessary to display the video signal corresponding to each scanning line in the liquid crystal panel 20. Are displayed in two pixel columns. Since the video signal of the same scanning line is supplied to the three pixel columns in the odd field, the line memory 13 used in this IP conversion is two lines that can be read and written simultaneously, and 288 lines in the 576i signal. By capturing one line and outputting it at a double clock frequency after capturing, the number of lines is doubled to 576 lines. At this time, the horizontal period of one line is set to half the horizontal period of the 576i signal.

  Here, the panel drive frequency in the liquid crystal panel 20 will be described by taking an euro panel (the number of panel horizontal dots is 960 and the number of panel vertical dots is 540) as an example. A PAL video signal is composed of one field of 270 lines, with a vertical synchronization frequency of 50 Hz and a horizontal synchronization frequency of 15.62 KHz. On the other hand, the liquid crystal panel 20 suitable for the PAL system including the euro panel is configured to display with one field of 540 lines, and has a vertical synchronization frequency of 50 Hz and a horizontal synchronization frequency of 31.25 KHz. Clock) is 40.5 MHz. The total number of vertical clocks is 625.

  The panel drive frequency is determined by the horizontal synchronization frequency and the total number of horizontal clocks. The horizontal total clock number is the number of drive clocks when the horizontal line includes the blanking period, and in the case of the liquid crystal panel 20 suitable for the PAL system, it is 1296 clocks. At the time of the PAL signal (at the time of 576p), the horizontal synchronization frequency is 31.25 KHz, so the panel drive frequency in this case is 31.25 KHz × 1296 = 40.5 MHz.

  FIG. 5 is a diagram for explaining an example of video signal conversion processing when a 1080i signal is displayed in the video display device of FIG. 1, and FIG. 6 is a method of assigning a 1080i signal (even field) to each line of the liquid crystal panel. FIG. 7 is a diagram for explaining a method for assigning 1080i signals (odd fields) to the respective lines of the liquid crystal panel, and FIG. 8 is a diagram for displaying the 1080i signals on a 540-line liquid crystal panel (PAL panel). It is a figure for demonstrating the positional relationship of the 1080i signal and 540 lines at the time of doing.

  The 1080i signal is an interlaced video signal (hereinafter referred to as 1125i signal) having 1125 scanning lines, of which 1080 effective scanning lines exist. In order to display the 1080i signal 40 on the liquid crystal panel 20 composed of 540 pixel columns, the line memory 13 is used to convert the 1080i signal 40 into a progressive signal (referred to as a 540p signal) 41 having 540 scanning lines. IP conversion is performed by performing simple vertical scaling. By this simple vertical scaling processing, the 1080i signal 40 is finally converted to a 540p signal 41, and display on the liquid crystal panel 20 composed of 540 pixel columns is possible as indicated by reference numeral 43 in FIG. Reference numeral 43 schematically represents a pixel column of the euro panel. Since the 1080i signal 40 is a 16: 9 type, horizontal scaling is not required when it is displayed on a 16: 9 type wide euro panel.

  Next, simple vertical scaling, which is a feature of the present invention, will be described by taking the display of a 1080i signal on a PAL panel as an example. Conventionally, as shown in FIG. 13, when a 1080i signal is displayed on a 540-line liquid crystal panel, a frame memory must be used or vertical blurring must be allowed. However, according to the present invention, it is possible to display a 1080i signal on the PAL panel without using a frame memory and without blurring of an image in the vertical direction.

  In the present invention, in order to prevent such blurring of the image, when an odd field is displayed, if it is considered with 540 lines, it is apparently lowered by 0.5 lines (1 line when considered with a 1080i signal). When the odd field is displayed, the average of the line to be displayed and the next lower line is taken to obtain the effect of being lowered by 0.5 lines. At this time, the even field does not pass through the simple scaler 14 or passes through without processing, so that simple scaling is not performed.

  The line assignment for the even field and odd field video signals is illustrated in FIGS. 6 and 7, and will be described with reference to this. First, the n-line (first line) of the video signal of the even field is displayed as it is on each pixel column of the liquid crystal panel 20 as in the first column of the pixel column of the liquid crystal panel 20. On the other hand, the odd-field video signals m, m + 1, m + 2,. . . On the other hand, since the pixel column of the liquid crystal panel 20 originally needs to be lowered by 0.5 lines with respect to the even field as shown in FIG. 8, m, ( (M) + (m + 1)) / 2, ((m + 1) + (m + 2)) / 2, ((m + 2) + (m + 3)) / 2,. . . In other words, the scaling for averaging between adjacent horizontal scanning lines except for the first pixel column is performed. Thus, the contents of the display line at 540p are alternately displayed with the even field of the 1080i signal and the average value in the odd field of the 1080i signal. Here, (m + 1) or the like indicates the video signal of that line. For IP conversion performed by such simple vertical scaling, two line memories 13 can be read and written simultaneously. Note that the process for the even field and the process for the odd field may be reversed.

  When a 1080i signal is displayed on the PAL liquid crystal panel 20, the display clock of the liquid crystal panel 20 must be increased in order to absorb the difference in horizontal synchronization frequency. The 1080i signal is composed of one field of 540 lines, and has a vertical synchronization frequency of 60 Hz and a horizontal synchronization frequency of 33.75 KHz. On the other hand, since the total number of panel horizontal clocks is 1296 as described above, the panel drive frequency is 33.75 KHz × 1296 = 43.7 MHz. As described above, the liquid crystal panel 20 raises the display clock to 40.5 MHz when the PAL signal is displayed and 43.7 MHz when the 1080i signal is displayed.

  Finally, a circuit configuration example of the video display device of FIG. 1 will be described with reference to FIG. The liquid crystal panel 20 is mounted on the surface of the matrix type display device illustrated in FIG. 9, and the power supply board 51, the signal input board 52, the main board 53, the LCD control board 54, the backlight inverter board 55, An operation switch board 56 is provided.

  The signal input board 52 is provided with an input switching IC 61 corresponding to the input switching unit 11. The main board 53 is provided with an AD converter IC 62 corresponding to the AD converter 12, a video signal conversion memory IC 63 corresponding to the video signal conversion memory 13, and an image processing IC 64. The image processing IC 64 is an IC corresponding to the video signal conversion unit 14, the image quality enhancement correction unit 15, the OSD control unit 16, and the OSD mixing unit 17. The LCD control board 54 is provided with a γ correction IC 65 corresponding to the γ correction unit 18 and a liquid crystal controller IC 66 corresponding to the liquid crystal controller 19. A gate driver 21 and a source driver 22 are further provided on the rear surface of the matrix display device.

  As described above, since the simple scaler 14 in the video display device according to the present invention is suitable for the video signal of the PAL system or the like, the standard (SD) video signal of the PAL system is displayed on the wide euro panel. In this case, the 576i signal is IP converted into a 576p signal and converted into a 540p signal. In addition to overscan and horizontal scaling, the IP conversion can be performed by simply performing double scaling in the vertical direction. That's it. On the other hand, this video display device only needs to perform simple vertical scaling to convert a 1080i signal into a 540p signal even when displaying a high-definition (HD) video signal on a wide euro panel.

  In addition, when displaying an NTSC standard (SD) video signal on a PAL display panel such as a wide Euro panel, the horizontal scanning line of the NTSC video signal is provided by the scaler in the vertical direction. This can be handled by interpolating the horizontal scanning lines corresponding to the display panel. For example, after overscanning a 525i signal and converting it to a 480i signal, IP conversion is performed by simple vertical scaling based on the ratio of the number of scanning lines to the 540p signal with respect to the 480i signal, and other horizontal scaling is performed. It can be applied as needed.

  As described above, conventionally, a frame memory has to be used for the scaler or image blurring has been tolerated. However, in the present invention, a simplified scaler in which only a line memory having a much smaller memory capacity than the frame memory is used. It can be adopted, and not only is the circuit simple, which is beneficial in terms of scale and cost, but also enables power consumption to be reduced, thereby providing an environmentally friendly video display device. Further, by displaying the horizontal scanning line signal of the video signal so as to match the pixel of the panel, simple scaling is sufficient, and the influence of the image quality due to the scaling can be prevented as much as possible. Thus, according to the present invention, when displaying an interlaced video signal having a predetermined number of effective scanning lines, such as a 1080i signal, on a display panel having a vertical resolution close to half or half the number of effective scanning lines. The vertical scaling does not blur the video information, and the circuit scale, cost, and driving power are not increased.

It is a figure which shows the principal part in the example of 1 structure of the video display apparatus concerning one Embodiment of this invention. FIG. 3 is a diagram for explaining an example of video signal conversion processing when displaying a PAL video signal in the video display device of FIG. 1. It is a figure for demonstrating the allocation method of the PAL video signal (even field) with respect to each line of a liquid crystal panel. It is a figure for demonstrating the allocation method of the PAL video signal (odd field) with respect to each line of a liquid crystal panel. It is a figure for demonstrating the example of a video signal conversion process at the time of displaying 1080i signal in the video display apparatus of FIG. It is a figure for demonstrating the allocation method of the 1080i signal (even field) with respect to each line of a liquid crystal panel. It is a figure for demonstrating the allocation method of the 1080i signal (odd field) with respect to each line of a liquid crystal panel. It is a figure for demonstrating the positional relationship of a 1080i signal and a 540 line at the time of displaying a 1080i signal on a 540-line liquid crystal panel. It is a figure which shows the circuit structural example of the video display apparatus of FIG. It is a figure which shows the principal part of the structure of the video display apparatus for the video sources of the conventional PAL system. It is a figure for demonstrating the video signal conversion process of a PAL standard video signal in the conventional matrix type display apparatus of a W-XGA system. It is a figure for demonstrating the video signal conversion process of a high-definition video signal in the conventional matrix type display apparatus of a W-XGA system. It is a figure for demonstrating the vertical scaling with respect to the 1080i signal in the conventional matrix type display apparatus of a W-XGA system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Input switching part, 12 ... AD converter, 13 ... Scaling line memory, 14 ... Simple scaler, 15 ... Image quality emphasis correction part, 16 ... OSD control part, 17 ... OSD mixing part, 18 ... γ correction part, 19 ... Liquid crystal controller, 20 ... display panel, 21 ... gate driver, 22 ... source driver.

Claims (3)

  A video display device capable of displaying an interlaced video signal having a predetermined number of effective scanning lines, the display panel having a vertical resolution close to half or half of the number of effective scanning lines of the video signal, and the input A video display device comprising: a scaler that scales a video signal using a line memory, and scaled by the scaler and displayed on the display panel.   One field of the video signal is displayed on the display panel without being scaled by the scaler, and the other field of the video signal is displayed between adjacent horizontal scanning lines by the scaler. The image display apparatus according to claim 1, wherein the display panel displays the image by performing scaling that averages the above.   The video display apparatus according to claim 1, wherein the predetermined number of effective scanning lines is 1080 of an interlace method.

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