JP3469596B2 - Matrix type display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display device such as a liquid crystal display device, and more particularly to a matrix type display device capable of displaying a plurality of television signals. It relates to a display device. 2. Description of the Related Art In recent years, high-definition television broadcasting has been started and high-vision receivers have been developed.
In place of T (cathode ray tube), a high-definition television receiver using a matrix type display device such as a liquid crystal display device having a feature of being lightweight and thin has been developed. In such a high-vision receiver having an aspect ratio of 16: 9, a plurality of systems such as a conventional television signal having an aspect ratio of 4: 3 (NTSC system, PAL system, EDTV system, etc.) or a video signal of a personal computer are used. There is a demand for a receiver capable of displaying a television signal of the following type. In a CRT system high-vision receiver, a method of displaying television signals of a plurality of systems by converting an input television signal into a system conforming to the standard of the receiver has already been announced. I have. However, it is considered that a matrix type display device such as a liquid crystal display device can display television signals of a plurality of systems having different aspect ratios or the like without performing system conversion by a specific scanning method. However, at present, no effective proposal has been made. In the above-mentioned current situation, for example, when displaying an input television signal having a different aspect ratio and a different number of scanning lines, the television signal itself is set to the standard of the receiver. A method of converting to a method that is compatible with the standard is used, but such a method requires interpolation processing of the number of scanning lines and conversion processing of horizontal and vertical frequencies, and requires a large-scale memory such as a field memory, In addition, a plurality of clocks for signal processing are required, so that the circuit scale and method become large. For example, when a signal such as a television having an aspect ratio of 4: 3 is displayed on a high-quality wide aspect matrix type display device, the vertical direction of the video display screen is fully displayed in the vertical direction of the matrix type display device. If this is done, non-image portions are formed on the left and right sides of the video display screen due to the difference in aspect ratio as shown in FIG. 7, but time compression is not performed on video signals for one line of the matrix type display device including the non-image portions. When writing is performed to all the pixels in one line, there arises a problem that the time exceeds one horizontal period of the input television signal. [0008] In order to solve the above problems, a matrix type display device of the present invention comprises: a type determining means for determining a type of an input television signal; and a control signal according to a result of the determination. A control signal generating means for generating, a time compression processing means for time-compressing the input television signal by a factor of an integer according to the result of the determination, and a DC level control for a time period other than the effective video period of the time-compressed video signal. A non-image portion processing means for inserting a signal, and a video display means for displaying the signal-processed video signal by a control signal according to the determination result. With the above arrangement, even when a television signal whose number of scanning lines, aspect ratio, number of pixels or the like of a matrix type display device such as a liquid crystal display is not suitable is input,
An image display screen corresponding to the aspect ratio of the input television signal can be realized. In addition, since the method has a simple configuration that does not perform complicated processing such as system conversion, an increase in circuit scale can be suppressed. An embodiment of a matrix type display device according to the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing one embodiment of the matrix type display device of the present invention. In FIG. 1, a television signal input from an input terminal 101 is sent to an input signal processing circuit 102. The input signal processing circuit 102 performs a filtering process for removing unnecessary noise and the like included in the input television signal, a gain adjustment necessary for signal processing in a subsequent stage, a clamp process, and the like. The video signal that has been subjected to these processes is sent to the time compression processing circuit 103, the synchronization separation circuit 104, and the system determination circuit 105, respectively. The sync separation circuit 104 detects a horizontal sync signal and a vertical sync signal in the input television signal. The detected horizontal synchronizing signal and vertical synchronizing signal are sent to the input signal processing circuit 102 and the system identification circuit 105. The two types of synchronization signals are used in the input signal processing circuit 102 to form, for example, a clamp pulse. On the other hand, the system discrimination circuit 105 discriminates the type of the input television signal by examining the characteristics of each television signal from these synchronization signals and the video signal supplied from the input signal processing circuit 102. . The result of the determination is sent to the control signal generation circuit 10 in the next stage.
6 to generate a clock for performing signal processing in this system, a control signal for signal processing and video display, and the like. The time compression processing circuit 103 time-compresses the video signal processed by the input signal processing circuit 102. Here, the time compression processing is performed using one horizontal period of each input television signal as a unit, and the horizontal frequency in video display is not changed. FIG. 2 is a signal waveform diagram after the time compression processing and after the non-image portion processing in FIG. In the case of FIG. 2, as an example, 1/2 time compression is performed on the basis of the horizontal synchronizing signal of the input television signal. In this example, the period from when the time-compressed video signal is output to when the next horizontal synchronization signal comes is not particularly defined as the video signal. However, in the non-picture part processing circuit 107 at the subsequent stage, there is no problem because the parts other than the effective video signal part in FIG. 2 are replaced with DC levels for displaying the non-picture part. The horizontal frequency of the finally time-compressed video signal is not changed from the horizontal frequency of the input television signal. Here, the compression ratio for the input television signal is set to 1/2, but this is not particularly limited. However, it is desirable to make it 1 / integer from the viewpoint that it can be easily obtained in the circuit configuration. As described above, the non-picture part processing circuit 107 performs a process of inserting a DC level signal in order to display a non-picture part in a part other than the effective video signal part. The video signal that has been processed in the non-image portion is then subjected to filter processing and signal processing for display according to the type of display device in the display signal processing circuit 108, for example, one horizontal period or one vertical period in a liquid crystal display. Processing for AC drive for inverting the polarity of the video signal supplied to the pixel in units, and is performed on the video signal supplied according to the input / output characteristics representing the relationship between the potential supplied to the pixel and the luminance when displayed. Video signal correction processing and the like are performed. In the video display section 109, the input television signal is supplied by a video signal from the display signal processing circuit 108 at the preceding stage and a control signal corresponding to the input television signal from the control signal generation circuit 106. Reproduce the video display screen according to the method. The overall signal processing flow of the matrix type display device of the present invention has been described above. In order to facilitate understanding of the matrix type display device of the present invention, a more concrete block diagram is shown. An embodiment of the matrix type display device of the present invention will be described in a specific form also for a type display device and an input television signal. First, as the image display unit 109, for example, the aspect ratio is 16: 9, and the number of pixels is 1000 * 1200.
Assume a liquid crystal panel that complies with the Hi-Vision standard.
When an HDTV signal (1125 scanning lines, aspect ratio 16: 9, interlace ratio 2: 1, field frequency 60 Hz) is supplied as an input television signal to this liquid crystal panel, the entire screen of the liquid crystal panel is hi-vision. Can display video. The configuration of the video display unit 109 is shown in FIG.
It becomes as shown in. In brief, the input terminal 301 receives a video signal that has been subjected to signal processing up to the previous stage. A clock corresponding to the type of the input television signal and the number of pixels of the liquid crystal panel is input to the input terminal 302. With this clock, the shift register 303
Operates, and the latch 304 latches the potential of the video signal for one pixel every one clock. An H reset pulse of the shift register is input to the input terminal 314 in order to determine a start position of video display in a horizontal period of the video signal. With this H reset pulse, the shift register starts latching the potential of the video signal for the leftmost pixel of the video display screen. The input terminal 305 has 1200 lines for one line.
After the latching of the potential of the video signal to the pixels is completed, a transfer pulse is input, and the potential of the video signal to 1200 pixels of one line of the liquid crystal panel is transferred from the latch 304 to the signal electrode driving circuit 306 at a time. After being further buffered, the potential of the video signal is supplied to each pixel electrode line 307. On the other hand, a scanning pulse is supplied to the input terminal 308 every horizontal period. The scanning electrode selection circuit 309 selects a scanning electrode for displaying an image. Scan electrode drive circuit 310
Supplies to the scanning electrode line 311 a signal for writing the potential of the video signal supplied to the pixel electrode line 307 to all the pixels in the selected scanning electrode.
A TFT is provided at the intersection of the pixel electrode line 307 and the scanning electrode line 311.
The liquid crystal is connected via a switch element such as the above, and the potential of the video signal is supplied to each selected pixel to be displayed. By performing this for all the scanning electrodes, a television image for one field is displayed on the display panel 312. A V reset pulse is supplied to the input terminal 313 every vertical period to notify the start of one vertical period.
This V reset pulse causes the scan electrode selection circuit 309
Is selected in order from the scanning electrode at the upper end of the video display screen.
By repeating the above operation, a television image is displayed. First, signal processing when a high-vision signal is supplied to this system will be described. In FIG. 1, a video signal that has been subjected to signal processing by an input signal processing circuit 102 is sent to a time compression processing circuit 103 at the next stage. FIG. 4 shows the time compression processing circuit 103.
3 is a configuration example of a non-image processing circuit 107. A video signal is input to an input terminal 401 of FIG.
Control signals corresponding to the high-definition signals are supplied from the control signal generation circuit 106 in FIG. The AD converter 411 performs AD conversion of the input video signal by a write clock from the input terminal 406. The frequency of the write clock is determined by the number of pixels of the matrix type display device, the horizontal frequency of the input television signal, the aspect ratio, and the like. Since the number of pixels is 1,200, the frequency is about 50 MHz. Thereafter, digitized video signals are supplied to the line memories 412 and 413. These line memories read and write video data every one horizontal period, and one of the line memories reads and writes the video data. In the state, the other is switched to be in the writing state and used. This is to prevent the overwriting of the write and read addresses of the line memory in the time compression processing. Therefore, the input terminals 402, 404, 407,
The timing of each reset pulse 408 and the memory select pulse of the input terminal 405 are as shown in FIG. 5, for example. The line memory used here has a data capacity of one line of a television signal in a system having the largest number of pixels in one horizontal period among the input television signals at least, and its address is a reset pulse. Only to return to address 0. The write address and the read address operate independently of each other. Although a read clock is input to the input terminal 403, when a high-definition signal is input, there is no need to perform time compression processing. Therefore, video data is read at a clock of about 50 MHz which is the same frequency as the write clock. Do. In the data selector 414, each line memory 41 is input by a memory select pulse from the input terminal 405.
The video data from the line memory in the read state is selected for each horizontal period from among 2, 413 and is sent to the non-picture part processing circuit 107 at the next stage. In the non-picture part processing circuit 107, the data selector 415 is for inserting non-picture parts on the left and right sides of the video display screen when displaying video signals having different aspect ratios. The input terminal 409 is supplied with DC level data for displaying a non-picture part, and the input terminal 410 is supplied with a video / non-picture part selection pulse for determining a period for inserting the non-picture part. However, when a high-definition signal is input, there is no need to insert a blank portion. And DA converter 4
The D / A conversion is performed by the D / A converter 16 using the same clock as the read clock of the line memory, and output from the output terminal 417. The video signal is supplied to the display signal processing circuit 1 shown in FIG.
At 08, the video signal for AC driving of the liquid crystal panel is subjected to a process such as AC conversion and supplied to the video display unit 109. When a high definition signal is input, the clock of the input terminal 302 in FIG.
The H reset pulse of No. 4 is supplied at the time when the effective video signal section starts. In the scanning electrode selection circuit 309, since the number of lines of the liquid crystal panel is 1,000, for example, the same signal is applied to the conventional interlaced scanning in which the scanning electrodes are skipped every other line, or two lines of the scanning electrodes. At the same time, writing is performed, and in the next field, video display is performed by a scanning method based on a selection that shifts the combination of the two lines by one line. Next, signal processing when a conventional NTSC signal is input will be described. The NTSC signal is a television signal having 525 scanning lines, an aspect ratio of 4: 3, an interlace ratio of 2: 1, and a field frequency of 59.94 Hz. The video signal processed by the input signal processing circuit 102 is sent to the time compression processing circuit 103.
In the embodiment of the present invention, as a method of displaying an NTSC signal having an aspect ratio of 4: 3 on a liquid crystal panel having an aspect ratio of 16: 9, the vertical direction of the video display screen is displayed to fill the entire vertical direction of the liquid crystal panel. FIG. 7 shows a state of video display in that case. When the NTSC signal is input, the write clock in FIG. 4 is approximately 17 MHz calculated from the number of pixels in one line and the aspect ratio. But actually NT
Since the video band of the SC signal is narrower than that of the Hi-Vision signal, the same video signal may be displayed for two pixels on the scanning electrodes of the liquid crystal panel. In this case, the write clock is reduced by half to about 8.5 MHz. Become. Here, it is assumed that the video data is sampled for each pixel.
Hz. The input terminal 403 is supplied with a read clock having a frequency capable of displaying all the video data of 1200 pixels on one line of the liquid crystal panel including the non-image portion within one horizontal period of the NTSC signal. That is, 17MH
When the video data of the effective video signal portion is read out without time compression by the read clock of z and the non-picture portion is added to display 1200 pixels of one line by the clock of 17 MHz, it takes about 70 μsec. The horizontal period is about 63.5 μsec, which is impossible in terms of time. In the embodiment of the present invention, a read clock having a frequency of about 34 MHz, which is twice the write clock, is used because of the simplicity of the circuit. By performing reading with this read clock, the video signal is time-compressed to 1/2. In the non-picture part processing circuit 107 at the next stage,
When the vertical direction of a video display screen with an aspect ratio of 4: 3 is fully displayed in the vertical direction of a liquid crystal panel with an aspect ratio of 16: 9, no picture corresponding to the left and right extra portions of the video display screen caused by the difference in aspect ratio 1 /
DC level data is inserted by the data selector 415 during periods other than the effective video signal portion of the video signal time-compressed to 2. The video data is DA-converted by the DA converter 416 according to the same clock as the read clock of the line memory. Thereafter, the video signal is subjected to signal processing such as AC conversion of the video signal in the liquid crystal display by the display signal processing circuit 108, and is sent to the video display unit 109. The input terminal 302 in FIG.
Clock is supplied. An H reset pulse is input to the input terminal 314, which determines where in the horizontal direction the liquid crystal panel having the aspect ratio of 16: 9, including the non-image area, displays the video of the NTSC signal having the aspect ratio of 4: 3. You. A transfer pulse is input to the input terminal 305 after the potential of the video signal for 1200 pixels is latched. The timing of these signals is as shown in FIG. In the scanning electrode selection circuit 309, the number of scanning lines of the NTSC signal is 525, the interlace ratio is 2: 1, and the number of lines of the liquid crystal panel according to the embodiment of the present invention is 1,000. The same signal is simultaneously written to two lines of the scanning electrode, and the next two lines are interlaced scanning in which the two lines are skipped, or four lines of the scanning electrode are selected.
The same signal is simultaneously written to the lines, and in the next field, video display is performed by a scanning method based on a selection that shifts the combination of the four lines by two lines. Other input television signals, for example E
DTV and various personal computer signals can be displayed in the same manner. Needless to say, the present invention is not limited by specific numerical values, circuit configurations, display devices and the like shown in the embodiments. Since the matrix type display device such as a liquid crystal display device of the present invention has the above-mentioned configuration, the television set of the display device is not suitable for the number of scanning lines, the aspect ratio, the number of pixels and the like. Even when a television signal is input, a display screen corresponding to the aspect ratio of the input television signal can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a matrix type display device of the present invention. FIG. 2 is a signal waveform diagram after a time compression process and a non-image portion process of the time compression processing circuit of FIG. 1; FIG. 3 is a block diagram illustrating a main part of a video display unit in FIG. 1; FIG. 4 is a block diagram showing a main part of a time compression processing circuit and a non-picture part processing circuit of FIG. 1; FIG. 5 is a timing chart of a write reset and a read reset of the line memory of FIG. 4 and a memory select pulse. FIG. 6 is a timing chart of signals in the video display unit of FIG. 4; FIG. 7 is an explanatory diagram of a display in a case where the display device and the television signal have different aspect ratios. [Description of Signs] 102 Input signal processing circuit 103 Time compression processing circuit 104 Synchronization separation circuit 105 Type discrimination circuit 106 Control signal generation circuit 107 Non-image part processing circuit 108 Display signal processing circuit 109 Video display unit 303 Shift register 304 Latch 306 Signal electrode drive circuit 307 Pixel electrode line 309 Scan electrode selection circuit 310 Scan electrode drive circuit 311 Scan electrode line 312 Display panel 411 AD converters 412, 413 Line memories 414, 415 Data selector 416 DA converter

Claims (1)

(57) [Claims] [Claim 1] For a television signal of a specific standard,
The number of scanning lines, the aspect ratio, the number of pixels, etc. are suitable, and in a matrix type display device such as a liquid crystal display capable of displaying, the type determination means for determining the type of the input television signal and the determination result by the type determination means. Control signal generating means for generating a corresponding control signal; time compression processing means for time-compressing the input television signal to a fraction of an integer in accordance with the result of the discrimination by the method discrimination means; Non-picture part processing means for inserting a DC level signal in a period other than the effective video period of the processed video signal,
A matrix-type display device comprising: a video display unit that displays the signal-processed video signal by a control signal according to a determination result.