JP2687346B2 - Video processing method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a video processing method in which picture-in-picture processing is performed simultaneously with scan conversion. [Summary of the Invention] The present invention relates to a video processing method, in which the capacity of a frame memory for main scanning conversion of a main video signal is made to correspond to a scanning line after scan conversion, and a sub video signal is written in this frame memory. The present invention is capable of performing good picture-in-picture processing without image quality deterioration. [Prior Art] For example, so-called picture-in-picture processing is performed in which a video signal from a VTR is inserted into a part of a video signal from a tuner. In such a process, conventionally, for example, the video signal from the tuner is written in the field memory, and the video signal from the VTR is thinned and compressed in the main scanning line and written in a part of the above field memory. Is read out to form a picture-in-picture processed video signal. On the other hand, in connection with the development of so-called high-definition televisions and high-resolution monitors for computers, it was considered that, for example, NTSC video signals were subjected to main scanning conversion and displayed on the above-mentioned high-resolution monitors. In this case, conventionally, a pair of NTSC interlaced fields are written in a frame memory, the frame memory is sequentially read, and scanning lines interpolated from the upper and lower scanning lines are formed every other scanning line read out. Then, main scanning conversion is performed. Therefore, it is conceivable to combine the above-described picture-in-picture processing and scan conversion to display the picture-in-picture processed video signal on a high-resolution monitor or the like. In that case, if the conventional techniques are simply combined, the configuration is as shown in FIG. That is, in the figure, main and sub video signals are supplied to the input terminals (31a) and (31b), respectively, and these signals are supplied to the AD conversion circuits (32a) and (32b), respectively. This AD
The signal from the conversion circuit (32a) is supplied to the signal switching circuit (38), and the signal from the AD conversion circuit (32b) is supplied to the circuit (34) that performs thinning compression and the like, and the thinned and compressed signal is output. It is supplied to the 1/4 field memory (33). Further, the synchronizing signal of the video signal supplied to the above-mentioned input terminals (31a) (31b) is supplied to the memory control circuit (36) through the terminals (35a) (35b), and the signal from this control circuit (36) is supplied. Is supplied to the field memory (33), and the signal from the circuit (34) is written in the memory (33). Further memory (33)
The signal written in the signal is read from the memory (33) at such a timing as to be located in a predetermined range of the image from the input terminal (31a), and at this timing, the signal switching circuit (3
8) is switched. The signal from the control circuit (36) is AD
It is also supplied to the conversion circuits (32a) (32b) and the circuit (34). Picture-in-picture processing is performed by the above configuration. Further, the signal from the signal switching circuit (38) is supplied to the frame memory (37). Further, the synchronization signal from the terminal (35a) is supplied to the memory control circuit (39), and the signal from this control circuit (39) is supplied to the frame memory (37) to write the signal from the signal switching circuit (38). Is done. Further, a synchronizing signal of a monitor (not shown) is supplied to the control circuit (39) through the terminal (40) to form various signals such as a memory writing start and a memory writing position.
These signals are supplied to the frame memory (37) for reading. The read signal is supplied to the DA conversion circuit (42) through the interpolation circuit (41), and the signal from the DA conversion circuit (42) is taken out to the output terminal (44) through the low pass filter (43). The signal from the control circuit (39) is also supplied to the interpolation circuit (41) and the DA conversion circuit (42). FIG. 4 shows the memory area of the frame memory (37) in correspondence with the drawings. The vertical direction in the figure indicates the memory address. In the above device, the signal switching circuit (3
The signal as shown in FIG. 4A is taken out from 8). That is, in the field memory (33), for example, every other field, for example, every other scanning line is thinned out and a compressed signal is written in it as shown in a range b in FIG. This signal is read so as to be located in a predetermined range of the image from the input terminal (31a) and written in the frame memory (37). On the other hand, the signal from the AD conversion circuit (32a) is directly written in the frame memory (37). As a result, a signal as shown in FIG. 9B is formed on the memory (37). Then, this signal is interpolated to form a signal as shown in FIG. However, in this device, the signal in the range b of the signals output to the output terminal (44) has a part where information is lost by the circuit (34) as shown in the figure, so the image quality is deteriorated. ing. That is, as shown in the figure, the number of scanning lines in the range b in this case is 525, which corresponds to NTSC.
It is equal to the number of scanning lines in one frame of the method. Therefore, the original video signal supplied to the input terminal (31b) contains the information of all 525 scanning lines. However, in the above-described apparatus, since the video signal is thinned out and compressed for picture-in-picture processing and then interpolated, the image quality is significantly impaired. Further, in the above-mentioned device, the configuration is complicated because two memories are used, and its control is not easy. [Problems to be Solved by the Invention] As described above, the conventional techniques have a problem that image quality is significantly deteriorated when scan-converting a picture-in-picture processed signal. [Means for Solving Problems] According to the present invention, scanning is performed by AD-converting a video signal, writing the video signal in the frame memory (4), and reading the video signal from the frame memory at a reading speed faster than the writing speed. In the video processing method for conversion, the capacity of the frame memory is set to a capacity corresponding to the number of scanning lines after the scan conversion, and the main video signal (input terminal (1a)) is AD-converted (circuit (2a)), The AD-converted main video signal is entirely written in the frame memory, and is generated using the main video signal read from the frame memory and the AD-converted main video signal (interpolation circuit ( 3)) writing the interpolated video signal to the frame memory, AD-converting the sub-video signal (input terminal (1b)) (circuit (2b)) and writing it to a predetermined range of the frame memory, and the main video signal And above By reading the interpolated video signal and the sub video signal at a read speed higher than the write speed (memory control circuit (6)), the main video signal (a) is formed by the main video signal and the interpolated video signal. And a sub-picture (b) is displayed according to the sub-picture signal to form a picture-in-picture picture signal without reducing the information amount of the sub-picture signal. Is. [Operation] According to this, since the frame memory corresponding to the scanning line after scan conversion is provided and the sub-picture signal is directly written in this frame memory, there is no fear of deterioration of the sub-picture signal and it is extremely excellent. A scan-converted picture-in-picture video signal can be obtained. [Embodiment] In FIG. 1, main and sub video signals are supplied to input terminals (1a) and (1b), respectively, and these signals are respectively supplied.
It is supplied to the AD conversion circuits (2a) and (2b). The signal from the AD conversion circuit (2a) is supplied to the frame memory (4) having a storage capacity of two frames through the interpolation circuit (3), and the signal from the frame memory (4) is also supplied to the interpolation circuit (3). The scanning lines are fed back to, for example, scanning lines interpolated from the upper and lower scanning lines are formed, and the signals of these scanning lines are also supplied to the frame memory (4). The signal from the AD conversion circuit (2b) is also supplied to the frame memory (4). Further, the synchronizing signal of the video signal supplied to the above-mentioned input terminals (1a) and (1b) is supplied to the memory control circuit (6) through the terminals (5a) and (5b), and various kinds of information such as memory write start and memory write position are provided. Signals are supplied to the frame memory (4), the signals from the interpolation circuit (3) are written in the entire memory (4), and the necessary signals are read from the memory (4). And is fed back to the interpolation circuit (3). A signal from the A / D conversion circuit (2a) is written in a predetermined range of the memory (4). The signal from the control circuit (6) is also supplied to the AD conversion circuits (2a) and (2b) and the interpolation circuit (3). Further, a synchronizing signal of a monitor (not shown) is supplied to the control circuit (6) through the terminal (7), and the signal from the control circuit (6) is supplied to the frame memory (4) for reading. The read signal is supplied to the DA conversion circuit (8), and the signal from the DA conversion circuit (8) is taken out to the output terminal (10) through the low pass filter (9). The signal from the control circuit (6) is also supplied to the DA conversion circuit (8). FIG. 2 shows the memory area of the frame memory (4) in association with the screen. The vertical direction in the figure indicates the memory address. In the above-described device, as shown in FIG. 2B, in the frame memory (4), in a range a in which a signal from the terminal (1a) is written, an odd field scanning line (solid line) and an even field scanning line ( In the range b in which the signal interpolated between the scanning lines (chain lines) interpolated between the dotted lines is written and the signal from the terminal (1b) is written, the odd field scanning lines (solid lines) and even fields are written. Scanning lines (dotted lines) are alternately written to form scan-converted picture-in-picture video signals. That is, in the above device, the terminal (1b) is in the range b.
Since the information of all the scanning lines of the video signal supplied to is stored, it is possible to form a video signal without image quality deterioration. Further, in the above-described device, since only one memory is used, the configuration is simple and its control can be easily performed. The scan-converted picture-in-picture video signal is formed in this way. According to the above-described apparatus, a frame memory corresponding to the scan line after scan conversion is provided, and the sub-video signal is directly supplied to this frame memory. Since it is written, there is no fear of deterioration of the sub-picture signal,
A very good scan-converted picture-in-picture video signal can be obtained. In the above apparatus, when the monitor is a so-called double speed non-interlaced display, the apparatus is configured so that the capacity of the frame memory (4) is set to one frame and the interpolation circuit (3) is not provided. can do. In this case, in the memory (4), as shown in FIG. 2A, the odd-field scanning lines and the even-field scanning lines are alternately written in the range a, and the odd-field all scanning lines are written in the range b. All the scanning lines in the even field are written in each field, and in this case also, a video signal without deterioration in image quality can be formed. That is, according to this device, when scan conversion is performed at 2x speed or 4x speed to perform picture-in-picture processing of 1/4 screen or more, further scan conversion is performed at 3x speed or 6x speed and picture-in of 1/9 screen or more is performed. It is possible to form a video signal without deterioration of image quality when performing picture processing. Further, according to the above apparatus, even if the scanning rates of the input video signals are different, the picture-in-picture processing of these signals can be performed. [Effect of the Invention] According to the present invention, since the frame memory corresponding to the scanning line of the scan conversion is provided and the sub-picture signal is directly written in this frame memory, there is no fear of deterioration of the sub-picture signal, It has become possible to obtain a very good scan-converted picture-in-picture video signal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example of an apparatus to which the present invention is applied, and FIG.
The figure is a diagram for explaining it, and FIGS. 3 and 4 are diagrams for explaining a conventional technique. (1a) and (1b) are input terminals, (2a) and (2b) are AD conversion circuits,
(3) is an interpolation circuit, (4) is a frame memory, (5a)
(5b) (7) is a terminal, (6) is a memory control circuit, (8)
Is a DA conversion circuit, (9) is a low-pass filter, and (10) is an output terminal.

Claims (1)

(57) [Claims] A video processing method for performing AD conversion of a video signal, writing the video signal in a frame memory, and performing scan conversion by reading the video signal from the frame memory at a reading speed faster than the writing speed. With the capacity corresponding to the number of subsequent scanning lines, the main video signal is AD-converted, the AD-converted main video signal is entirely written in the frame memory, and the main video signal read from the frame memory is read. Video signal and above AD
The interpolated video signal generated by using the converted main video signal is written in the frame memory, the sub video signal is AD converted and written in a predetermined range of the frame memory, the main video signal and the interpolated video signal And by reading the sub-video signal at a read speed faster than the writing speed, the main video is displayed by the main video signal and the interpolated video signal, and the sub-video is displayed by the sub-video signal. A video processing method, wherein a picture-in-picture video signal is formed without reducing the information amount of the sub-video signal.