JP2690790B2 - Television receiver - Google Patents

Description

The present invention relates to a television receiver capable of switching and displaying a plurality of non-interlaced television signals.

[Prior Art] The recent development of digital technology is remarkable, and IDTV (Im
proved Definition TV), EDTV (Extendid Definition)
Many high-definition television receivers (hereinafter referred to as "high-definition television") such as TVs) have been proposed.

In this high definition television, for example, 525 / 29.97 / 5
9.94 / 2: 1 signal (525 scanning lines per frame, frame frequency 29.97Hz, field frequency 59.94Hz
2: 1 interlace signal), 525 / 59.94 / 59.94 / 1: 1 signal (525 scanning lines per frame, frame frequency 59.
It is converted into a non-interlaced signal of 94 Hz and displayed (eg, Nikkei Electronics 1986 September 1986).
See the 8th of May issue, "High-definition televisions using digital technology, which are expected to become the pillars of the next home appliances," etc.)

In high-definition television, non-interlaced display is performed in order to improve image quality deterioration due to interference such as line flicker and line scroll.

In order to perform this non-interlaced display, an interpolated scan line signal is formed by, for example, motion adaptive scan line interpolation processing, and this interpolated scan line signal is inserted between main scan line signals to form a non-interlaced video signal. To be done.

For example, in a still image, the average value of the main scanning line signals in the preceding and following fields is used as an interpolating scanning line signal, while in a moving image, a large time difference cannot be used for the signals in the preceding and following fields, so the average of the main scanning line signals in the upper and lower lines The value is used as the interpolation scan line signal.

FIG. 14 shows an example of the configuration of a high-definition television in which non-interlaced display is performed as described above.

In the figure, for example, NTSC is supplied to the input terminal 1.
The system color video signal SV is converted into a digital signal by the A / D converter 2 and then supplied to a motion adaptive Y / C separation circuit (luminance signal / color signal separation circuit) 3.

The Y / C separation circuit 3 performs Y / C separation by inter-line processing by using a signal of one horizontal period (1H) before, and Y / C by inter-frame processing by using a signal of one frame period before. Separation takes place.

The output signal of the A / D converter 2 is supplied to the motion detection circuit 4. In this motion detection circuit 4, for example, motion information K is formed from a one-frame difference signal. The motion information K has a high level “1” in the still image portion and a low level “0” in the moving image portion.

The motion information K from the motion detection circuit 4 is supplied to the Y / C separation circuit 3, and from this Y / C separation circuit 3, when the motion information K is at a high level "1", the luminance signal separated by the inter-frame processing. Y and the color signal C are output. On the other hand, when the motion information K is at the low level "0", the luminance signal Y and the color signal C separated by the interline processing are output.

The luminance signal Y output from the Y / C separation circuit 3 is supplied to the main complementary signal forming circuit 5, and an interpolation scanning line signal is formed from the main scanning line signal of the luminance signal Y. In this case, the interpolated scan line signal is formed by the intra-field processing and the inter-field processing. In the intra-field processing, for example, the average value of the main scanning line signals of the upper and lower lines of the same field is used as the interpolating scanning line signal, while in the inter-field processing, for example, the average value of the main scanning line signals at the same vertical position of the preceding and following fields. Are interpolated scan line signals.

FIG. 15 shows such a main complementary signal forming circuit 5. This FIG. 15 shows only the portion related to the luminance signal Y.

In the figure, the luminance signal Y from the Y / C separation circuit 3 is
A field memory 51 forming a delay element having a delay time of 1 field period (262 horizontal periods), a line memory 52 forming a delay element having a delay time of 1 horizontal period, and a delay having a delay time of 1 field period (262 horizontal periods) It is supplied to the series circuit of the field memory 53 forming the element.

The output signals of the field memory 51 and the line memory 52 are added and averaged by an adder 54, and the added and averaged signal is changed over to a changeover switch 55 as an interpolated scanning line signal by intra-field processing.
Is supplied to the fixed terminal on the m side.

The luminance signal Y from the Y / C separation circuit 3 and the output signal of the field memory 53 are added and averaged by the adder 56, and the added and averaged signal is an interpolated scanning line signal by inter-field processing and is a fixed terminal on the s side of the changeover switch 55. Is supplied to.

The changeover switch 55 receives the motion information K from the motion detection circuit 4.
Is supplied and the motion information K is connected to the s side in the still image portion having the high level “1”, while it is connected to the m side in the moving image portion having the motion information K being the low level “0”. That is,
When the motion information K is at high level "1", the interpolated scan line signal formed by the inter-field processing is selected, while
When the motion information K is at low level "0", the interpolated scanning line signal formed by the intra-field processing is selected.

The output signal of the changeover switch 55 is the interpolation scanning line signal.
Output as Yi. The output signal of the field memory 51 is output as the main scanning line signal Yr.

Returning to FIG. 14, the color signal C output from the Y / C separation circuit 3 is supplied to the color demodulation circuit 6. The red color difference signal RY and the blue color difference signal BY output from the color demodulation circuit 6 are supplied to the main complementary signal forming circuit 5 to form a dot-sequential signal RY / BY of these color difference signals. It

The signals Yr, Yi and RY / B-Y output from the main complementary signal forming circuit 5 are supplied to the sequential scan conversion circuit 7. The progressive scan conversion circuit 7 performs a sequential scan conversion process using the main scan line signal Yr and the interpolated scan line signal Yi. That is, the interpolation scanning line signal Yi is inserted between the main scanning line signals Yr to form the luminance signal Y'of the progressive scanning method (525 lines / field) in which the horizontal period is H / 2.

In the progressive scan conversion circuit 7, the dot sequential signal RY / B
The red color difference signal RY and the blue color difference signal BY are separated from -Y, and the same scan line signal is consecutively repeated twice in each.
Sequential scanning type color difference signal R'- whose horizontal period is H / 2
Y ', B'-Y' are formed.

In this case, in a certain field, for example, an odd field, the signal of the first scanning line becomes the main scanning line signal as shown in FIG. 16A, and is output from the main complementary signal forming circuit 5 at the same time as this main scanning line signal. The interpolated scanning line signal becomes the signal of the second scanning line. The signal of the third scanning line becomes the main scanning line signal, and the interpolation scanning line signal output from the main complementary signal forming circuit 5 at the same time as this main scanning line signal becomes the signal of the fourth scanning line. Hereinafter, this procedure is repeated.

In the next field, for example, the even field, as shown in FIG. 16B, the signal of the first scanning line forms the main complementary signal simultaneously with the main scanning line signal which becomes the signal of the 525th scanning line of the previous field. The interpolated scan line signal is output from the circuit 5. The signal of the second scanning line becomes the main scanning line signal, and the interpolation scanning line signal output from the main complementary signal forming circuit 5 at the same time as this main scanning line signal becomes the signal of the third scanning line. The signal of the fourth scanning line becomes the main scanning line signal, and the interpolation scanning line signal output from the main complementary signal forming circuit 5 at the same time as this main scanning line signal becomes the signal of the fifth scanning line. Hereinafter, this procedure is repeated.

The luminance signal Y'and the color difference signals R'-Y ', B'-Y' from the progressive scan conversion circuit 7 are supplied to the matrix circuit 8 and are outputted from the matrix circuit 8 in the progressive scan system of red, green and blue. Of the primary color signals R ', G', B'of the D / A converter 9
Then, it is converted into an analog signal and then supplied to the color picture tube 10.

Also, the video signal SV supplied to the input terminal 1 is supplied to the sync separation circuit 11, and the horizontal sync signal PH and the vertical sync signal are supplied.
PV is separated, and these synchronizing signals PH and PV are supplied to the deflection circuit 12. The horizontal and vertical deflection control of the picture tube 10 is performed by the deflection circuit 12, and a non-interlaced image is displayed on the screen of the picture tube 10.

Thus, in high-definition television, for example, 525 / 29.97 / 5
It has the function of converting 9.94 / 2: 1 signals to 525 / 59.94 / 59.94 / 1: 1 signals and displaying them.

By the way, in such a high definition television, there is a demand for switching and displaying a plurality of television signals.

Hereinafter, as a most general example of switching a plurality of television signals, a case of switching and displaying two television signals will be described.

When switching and displaying two television signals, two methods have been conventionally considered.

The method shown in FIG. 17 is a method of switching a television signal supplied to a high definition television. This method is the most basic method for switching and displaying two television signals on a high definition television.

In the figure, the first supplied to the input terminals 21 and 22
And the second television signals SV1 and SV2 are supplied to the fixed terminals on the a side and the b side of the changeover switch 23, respectively. The television signal selected by the changeover switch 23 is supplied to the high definition television 24.

The method shown in FIG. 18 is a method that has two systems of circuits up to the progressive scan conversion process and switches between two signals after the progressive scan conversion process.

In the same figure, the first supplied to the input terminals 31 and 32.
The second television signals SV1 and SV2 are supplied to the signal processing circuits 33 and 34, respectively. These signal processing circuits 33 and 34 include up to the progressive scan conversion circuit 7 in FIG.

The luminance signal Y'1 and the color difference signals R1'-Y1 ', B1'-Y1' of the progressive scanning system output from the signal processing circuit 33 are supplied to the fixed terminal on the a side of the changeover switch 35, and at the same time, the signal processing circuit. The luminance signal Y2 'and the color difference signals R2'-Y2', B2'-Y2 'of the progressive scanning system output from 34 are supplied to the fixed terminal on the b side of the changeover switch 35. And this changeover switch 35
The signal of the progressive scanning system selected by is supplied to the signal processing circuit 36. The signal processing circuit 36 includes the matrix circuit 8 and thereafter in FIG.

[Problems to be Solved by the Invention] By the way, the switching in FIGS. 17 and 18 includes a case where switching is performed at high speed at the synchronization timing of any television signal.

As an example of switching two television signals at high speed, there is a two-screen television. FIG. 19 is a configuration example of a dual-screen television according to the connection method of the example of FIG.

In the figure, the first television signal SV1 supplied to the input terminal 21 is used as the main screen video signal and the changeover switch 2
3 is supplied to the fixed terminal on the a side.

Also, the second television signal SV2 supplied to the input terminal 22 is supplied to the two-screen processor 25.

In the two-screen processor 25, for example, 525 / 29.97 / 59.94 /
2: 1 signal to 160 / 29.97 / 59.94 / 2: 1 signal (2: 1 interlace signal with 160 scanning lines per frame, frame frequency 29.97Hz, field frequency 59.94Hz) A signal is formed (see, for example, the April 14, 1980 issue of Nikkei Electronics).

That is, an image memory for absorbing the time difference between the main screen video signal and the sub screen video signal is provided, and the sub screen video signal with the number of scanning lines thinned is written to the image memory according to the synchronization, It is configured to read according to the synchronization of the video signal.

The sub-screen video signal from the dual-screen processor 25 is supplied to the fixed terminal on the b side of the changeover switch 23.

The changeover switch 23 is changed over in accordance with the synchronization of the main screen video signal, and the changeover switch 23 outputs a two-screen television video signal in which the child screen video signal is inserted into the main screen video signal. Then, the video signal for the dual-screen television is supplied to the high-definition television 24, and the small screen is displayed at a predetermined position on the line screen.

By the way, if you connect it like the example in Fig. 19 and configure a two-screen TV, the 525 / 29.97 / 59.94 / 2: 1 signal will change to 160
After being converted to a sub-screen video signal such as /29.97/59.94/2:1 signal, it is input to the high-definition TV and this high-definition TV
160 / 59.94 / 59.94 / 1: 1 signal (the number of scanning lines in one frame is 160
Non-interlaced signal with a frame frequency of 59.94Hz).

The first conversion process will be described in terms of the change in the amount of information.

FIG. 20 is a spatiotemporal frequency plane in which the vertical axis represents the vertical spatial frequency and the horizontal axis represents the time frequency.
It shows the pass band of a high-definition television that displays 525 / 59.94 / 59.94 / 1: 1 signals. The information in this band is displayed by a high-definition television (see, for example, the Institute of Television Engineers, May 1986, pp. 357-365, "Signal Processing in EDTV, IDTV" Bleaching).

The shaded area in FIG. 21 indicates the band in which the information of the 525 / 29.97 / 59.94 / 2: 1 signal exists.

By the way, 525 / 29.97 / 59.94 / 2: 1 signals are sent to 160 / 29.97 / 59.
Dual screen processor 25 of the example in FIG. 19 for converting to a 94/2: 1 signal
Has a pass band in the shaded area in FIG. In the figure,
The band in which the information of the 525 / 29.97 / 59.94 / 2: 1 signal exists, which is indicated by the diagonal lines in FIG. 21, is indicated by the dotted line. In this way, the dual-screen processor 25 deletes most of the information indicated by the area from the 525 / 29.97 / 59.94 / 2: 1 signals.

Even if such a signal from which information is greatly deleted is input to a high-definition television having the pass band shown in FIG.
Only the information in the shaded area in Fig. 22 is displayed, and a high-quality child screen cannot be displayed.

As described above, in the configuration of the dual-screen television according to the connection method of FIG. 17, the signal in which information is largely deleted is input to the high-definition television to display the child screen, so that the image quality of the child screen is significantly deteriorated. .

Such a problem does not occur only in the two-screen processing. As long as the connection is made as in the example of FIG. 17, if any signal processing is performed on the television signal at the input end of the high definition television, the information is always reduced.

Of course, the present invention is not limited to two television signals, and the same applies when handling many television signals.

On the other hand, with the configuration of the example of FIG. 18, no matter what kind of processing is performed, a large amount of information reduction as in the example of the example of FIG. 17 does not occur. This is because in this configuration, two sets of the most important signal processing units of the high-definition television, such as the motion adaptive Y / C separation circuit 3, the main complementary signal forming circuit 5, and the progressive scan conversion circuit 7, are independently provided. .

That is, this configuration is equivalent to having two sets of high-definition televisions, and each processing section is configured to perform optimum signal processing as a high-definition television.

Also, paying attention to the point of signal switching, the method of the example in FIG. 18 is characterized in that the non-interlaced scan-converted signal is switched regardless of what signal processing is performed.

From such a standpoint, the configuration of the example in FIG. 18 is
It can be seen that the present invention can be applied to a case where information (for example, character data such as channel sign) read from a memory stored in a non-interlaced state is multiplexed and displayed in the first television signal.

For example, if you want to display the channel sign,
The signal is read from the ROM in which the character signal is stored in a non-interlaced form, and the first television signal subjected to the non-interlaced scan conversion is replaced with only the character portion for display.

In this way, it is a method that is extremely easy to understand in terms of application.

However, there are technical problems as compared with the configuration shown in FIG. This is because the frequency band of the signal subjected to progressive scan conversion is twice that of the input signal. Compared to the configuration of the example in FIG. 17, a large number of circuit elements having twice the operating speed are required to handle such signals.

To actually realize this configuration, memory etc.
All must be able to work with non-interlaced high speed signals. That is, a high-speed memory which is expensive for the signal channels to be switched is required.

As described above, the configuration shown in FIG. 18 has many technical restrictions such as the operating speed.

As described above, it is difficult to configure a high-definition television capable of switching and displaying a plurality of television signals with the configurations of the examples of FIGS. 17 and 18.

An object of the present invention is to provide a television receiver that does not have the above-mentioned drawbacks.

[Means for Solving the Problems] A television receiver according to a first aspect of the present invention forms a plurality of main complementary signals for processing each of a plurality of television signals to form a main scanning line signal and an interpolation scanning line signal. Means and
A switch means for selecting one of a plurality of main scanning line signals and an interpolation scanning line signal output from the plurality of main complementary signal forming means, and a main scanning line signal and an interpolation scanning line signal selected by the switch means. And a scan conversion means for performing non-interlaced conversion.

A television receiver according to a second aspect of the present invention includes memory means for storing a non-interlaced television signal,
Delay means having a delay time substantially equal to the time for displaying an image by the television signal read from the memory means, and determining means for determining the field attribute of the synchronization signal used for reading the television signal from the memory means And a first control for controlling the reading from the memory means based on the field attribute judged by the judging means, and for making the input signal and the output signal of the delay means the interpolation scanning line signal and the main scanning line signal, respectively. A control means for switching the combination and a second combination which is a main scanning line signal and an interpolating scanning line signal, respectively, and a scan converting means for performing non-interlace conversion using the main scanning line signal and the interpolating scanning line signal. It will be.

A television receiver according to a third aspect of the present invention is a television receiver capable of switching and displaying a plurality of television signals, wherein one of the plurality of television signals is a television signal system. Memory means for storing in a non-interlaced manner, a delay means having a delay time substantially equal to a time for displaying an image by a television signal read from the memory means, and a television signal for reading the television signal from the memory means. The determining means for determining the field attribute of the synchronizing signal to be used, and the reading from the memory means are controlled based on the field attribute determined by this determining means, and the input signal and output signal of the delay means are respectively interpolated scanning line signal and A control means for allocating to the main scanning line signal is provided, and another television of a plurality of television signals is provided. In the system of the television signal, main auxiliary signal forming means for processing the television signal to form the main scanning line signal and the interpolating scanning line signal is provided, and a plurality of main signals obtained from one and other television signal systems are provided. Switch means for selecting one of the scan line signal and the interpolated scan line signal, and scan conversion means for performing non-interlace conversion using the main scan line signal and the interpolated scan line signal selected by the switch means. It is a thing.

[Operation] As described above, if any signal processing is applied to the television signal at the input terminal of the high definition television, the information is always reduced and the image displayed after switching is deteriorated in image quality. Further, it is not appropriate from a technical point of view to switch signals after scan conversion.

According to the configurations of the first and third inventions, a plurality of sets of important signal processing units of a high-definition television such as a motion adaptive Y / C separation circuit, a main complementary signal forming circuit, and a scan conversion circuit are provided.
Since the optimum signal processing is performed in each of them, the information reduced in the processing process can be reduced.

For example, in the example of the pass band of a two-screen television, the output signal is 160 / 59.94 / 59.94 / 1: 1 signal (the number of scanning lines in one frame is 160, the frame frequency is 59.
Non-interlaced signal that is 94Hz). The pass band related to this processing is shown by the diagonal lines in FIG. 23, and the area portion is increased as compared with that shown in FIG. 22, and the amount of information is approximately doubled.

Considering the area where the information of the 525 / 29.97 / 59.94 / 2: 1 signal exists, the information passed by this processing is
It becomes as shown by the diagonal lines in Figure 24.

As described above, according to the configurations of the first invention and the second invention, the amount of information to be reduced can be minimized.

According to the configurations of the first invention and the second invention,
Non-interlace conversion is performed using a main scanning line signal and an interpolation scanning line signal selected from a plurality of main scanning line signals and an interpolation scanning line signal. Processing is performed at twice the operating speed. That is, according to the configurations of the first invention and the second invention, the number of expensive circuit elements having twice the operating speed can be reduced.

Next, the second invention is a component for constituting the television receiver according to the third invention in combination with the first invention, and uses a lot of memory means or the like which needs to operate at high speed. It becomes possible to obtain high image quality for all television signals even without them.

That is, the signal read from the memory means is input to the delay means having a delay time substantially equal to the time to be displayed, and the input signal and the output signal are used for reading the signal from the memory means. Based on the above, there is provided control means for allocating to the interpolated scanning line signal and the main scanning line signal, and it operates so as to perform non-interlace conversion using the obtained main scanning line signal and interpolated scanning line signal.

With this configuration, it is not necessary to use high-speed memory means corresponding to the high speed after scan conversion in order to obtain the main scanning line signal and the interpolation scanning line signal. That is, it is not necessary to handle a high speed non-interlaced signal, and it is technically easy to realize. Therefore, the effect of cost reduction can be expected.

Embodiment An embodiment of the present invention will be described below with reference to FIG. The present example is an example of a two-screen television that switches and displays the main-screen video signal and the sub-screen video signal. In FIG. 1, parts corresponding to those in FIG. 14 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the figure, the television signal supplied to the input terminal 1 is processed in the same manner as in the example of FIG. 14, and the main complementary signal forming circuit 5 supplies the main scanning line signal Yr of the luminance signal and the interpolation scanning line signal Yi.
And the dot-sequential signal RY / BY of the color difference signals is output. These signals Yr, Yi and RY / B-Y are supplied to the fixed terminal on the m side of the changeover switch 13 as a parent screen video signal.

Further, the color video signal SVs of, for example, the NTSC system, which is supplied to the input terminal 14, is supplied to the two-screen television signal processing unit 15. The main scanning line signal yr of the luminance signal, the interpolation scanning line signal yi, and the dot-sequential signal r-y / by of the color difference signals output from the signal processing unit 15 are output. These signals yr, yi and r-y / by are supplied to the fixed terminal on the s side of the changeover switch 13 as a sub-picture video signal.

Switching of the changeover switch 13 is controlled by a changeover control signal SW output from the signal processing unit 15. That is, the changeover switch 13 is connected to the s side during the period when the child screen is to be displayed, and is connected to the m side during the period when the parent screen is to be displayed. In this way, since the change-over switch 13 is connected to the s side only during the display period of the small screen, the small screen video signal is inserted into the main screen video signal.

Then, the output signal of the change-over switch 13 is supplied to the progressive scan conversion circuit 7, and the same processing as that of the example in FIG. 14 is performed thereafter, and a child screen is displayed on the screen of the picture tube 10 at a predetermined position of the parent screen. The inserted image is displayed non-interlaced.

 FIG. 2 shows a specific configuration of the signal processor 15.

In the figure, the video signal SVs is supplied to the input terminal 151. The video signal SVs is converted into a digital signal by the A / D converter 152 and then supplied to the Y / C separation circuit 153. Y / C
The luminance signal Y separated by the separation circuit 153 is supplied to the thinning circuit 154. The color signal C separated by the Y / C separation circuit 153 is demodulated by the color demodulation circuit 155. From this color demodulation circuit 155, the dot difference signal R-Y of the red color difference signal RY and the blue color difference signal BY is obtained.
Y / BY is output, and the dot-sequential signal RY / BY is supplied to the thinning circuit 154. The operation of the thinning circuit 154 is controlled by the thinning control circuit 156.

Then, the output signal of the thinning circuit 154 is supplied as a write signal to the frame memory 157 composed of, for example, a RAM. The write operation in the frame memory 157 is controlled by the write control circuit 158.

Further, the video signal SVs supplied to the input terminal 151 is supplied to the sync separation circuit 159, and the vertical sync signal WVD and the horizontal sync signal WHD separated by the separation circuit 159 are thinned-out control circuit.
It is supplied to the write control circuit 158.

Reference numeral 160 denotes a write clock generation circuit including a PLL circuit, for example, and the clock WCK output from the generation circuit 160 is the A / D converter 152 and the Y / C separation circuit 15
3, color demodulation circuit 155, thinning circuit 154, thinning control circuit 15
6, supplied to the frame memory 157 and the write control circuit 158.

In the thinning circuit 154 described above, the sample rate in the vertical direction is reduced according to the display area ratio of the child screen to the parent screen. In this case, the scan lines are thinned out. In addition,
When reducing the sample rate, a low-pass filter corresponding to the reduced rate is inserted in advance so that there is no signal component above the Nyquist frequency.

In the thinning circuit 154, in addition to the above-described sample rate reduction processing, processing for interpolating scanning line signals to form non-interlaced signals is performed, and signals to be written in the frame memory 157 are created. This processing is performed for each of the luminance signal Y and the dot-sequential signal R-Y / B-Y.

By the way, FIG. 3A shows the scanning line position for each field f1, f2, ... Of the interlaced signal. In the figure, a mark “○” represents a scanning line, and the position is shifted by one line in the vertical direction for each field. FIG. 9B shows the scanning line position for each field of the non-interlaced signal. In the figure, "○" mark,
The "x" mark represents the scanning line, the "○" mark is the scanning line corresponding to the interlaced signal, the "x" mark is the scanning line interpolated from the interlaced signal, and it is the same position in all fields. There are scan lines.

In FIG. 3, the horizontal axis represents the time direction in field cycle units, and the vertical axis represents the vertical direction in scanning line intervals.

Next, the sample rate reduction process and the non-interlaced signal formation process will be described. Hereinafter, a case where the display area ratio of the small screen is 1/9 will be described as an example.

The number of lines in one field of the video signal SVs is represented by ln for convenience.
If the number of lines is one, the number of lines in one field of the non-interlaced signal to be written in the frame memory 157 is ln / 3 × 2 = 2ln / 3 [lines]. Here, “÷ 3” means that the display area ratio is 1/9, so that the vertical screen height of the child screen is 1/3.
“× 2” means that the number of scanning lines is 2 due to non-interlacing.
It means that it becomes double.

As described above, the number of lines in one field to be written in the frame memory 157 is 2/3 of the number of lines in one field of the video signal SVs. Therefore, depending on the number of lines in one frame of the video signal SVs, Is scan converted.

FIG. 4A shows the video signal SVs, and the mark “◯” indicates the scanning line of the input signal. Further, FIG. 9B shows a non-interlaced signal which is scan-converted and written in the frame memory 157, and “x” marks are scanning lines. In this case, each scanning line signal of the non-interlaced signal is formed by calculating from a plurality of scanning line signals of the video signal SVs.

For example, the number of lines in one frame of the video signal SVs is 6k +
If there are three (525 etc.), the vertical sync signal WVD
The control is repeated every three lines in each frame period with reference to the frame pulse obtained by dividing the frequency by 1/2 to form the scanning line signal of the non-interlaced signal.

For example, the following control is repeated every three lines in each frame period.

That is, 3n + 0 (0, 3, 6, ...
In the) line, the current scan line signal and the scan line signal one line before, which are surrounded by a broken line in FIG. 5A, are added at a rate of 1/2 to obtain a scan line signal of a non-interlaced signal. Is formed.

In the 3n + 1 (1, 4, 7,...) -Th line, a scanning line signal of a non-interlace signal is not formed.

Also, in the 3n + 2 (2,5,8, ...) th line, the current scanning line signal, the scanning line signal one line before and the scanning line signal two lines before, which are surrounded by a solid line in FIG. Are added at a rate of 1/4, 1/2, and 1/4, respectively, to form a scanning line signal of a non-interlaced signal.

In FIG. A, “(x = 0 to 14)” is a scanning line.

Further, FIG. 9B shows a non-interlaced signal formed by repeating the above control, and the mark "x" indicates a scanning line. In this case, the positions of the scanning lines in the vertical direction are aligned in FIG.
Then, it is easy to understand which position corresponds to.

In other words, the l1 scanning line of the non-interlaced signal corresponds to the l2 position of the video signal SVs, the l2 scanning line of the non-interlaced signal corresponds to the l3 ′ position of the video signal SVs, and so on. And a non-interlaced signal is formed.

By the way, although the frame pulse is used as the reference as described above, when the phase of the frame pulse is inverted,
The processing is performed as shown in FIG. 6A, and a non-interlaced signal is formed as shown in FIG. 6B. In this case, the l1 scan line of the non-interlaced signal is the video signal.
The scanning line of l2 of the non-interlaced signal at the position of l1 of SVs corresponds to the position of l2 ′ of the video signal SVs at the same position below, which is equivalent to two lines as compared with the case of FIG. However, the scanning line position for each field is constant, and non-interlaced signals are similarly formed.

In addition, in FIGS. 4 to 6, the number of scanning lines of the video signal SVs is 1
Although the description has been made with reference to five lines, for example, when the number of scanning lines is 6k + 3, such as 525 lines, 627 lines, and 1125 lines, a non-interlace signal is formed in the same manner.

FIG. 7 shows a specific configuration example of the thinning circuit 154 and the thinning control circuit 156.

In the figure, the luminance signal Y obtained from the Y / C separation circuit 153 is supplied to a series circuit of line memories 531 and 532 which constitute a delay element having a delay time of one horizontal period. The output signals of the line memories 531 and 532 are supplied to the adder 533, added at a rate of 1/2, and then supplied to the fixed terminal on the c side of the changeover switch 534. Further, the luminance signal Y from the Y / C separation circuit 153, the output signal of the line memory 531 and the output signal of the line memory 532 are supplied to the adder 535, and have a ratio of 1/4, 1/2 and 1/4, respectively. After being added in, it is supplied to the fixed terminal on the b side of the changeover switch 534.
Further, the luminance signal Y from the Y / C separation circuit 153 and the output signal of the line memory 531 are supplied to the adder 536 and added at a rate of 1/2 respectively, and then the fixed terminal on the a side of the changeover switch 534. Is supplied to.

Note that FIG. 7 shows a thinning circuit for the sake of simplicity.
As 154, only the portion related to the luminance signal Y is shown. Although not described, the portion related to the dot-sequential signal R-Y / B-Y has the same configuration and performs the same processing.

Further, the vertical sync signal WVD from the sync separation circuit 159 is supplied to the frame ranking circuit 561 including, for example, a T flip-flop and a gate circuit. In the frame ranking circuit 561, the vertical synchronizing signal WVD is divided into 1/2 to form a frame pulse WFP.

The frame pulse WFP is supplied to the line timing display circuit 562 including, for example, a counter, and the timing display circuit 562 is supplied with the horizontal synchronization signal WHD from the synchronization separation circuit 159. Then, the timing display circuit 562 counts the number of the current line counted from the frame pulse WFP, and outputs the remainder obtained by dividing the value by 3.

The above frame pulse WFP and the remaining data from the timing display circuit 562 are supplied to the changeover switch 534 of the thinning circuit 154, and the line address control circuit 5
It is supplied to 63 and the switching control of the changeover switch 534 and the writing to the frame memory 157 are controlled.

 This control is performed as follows.

In the 3n + 0th line from the frame pulse WFP, the changeover switch 534 is connected to the side a, the line address control circuit 563 outputs the increment signal INC, and the output signal of the changeover switch 534 is written in the frame memory 157, and the frame pulse In the 3n + 1th line from WFP, the changeover switch 534 is indefinite, the increment signal INC is not output from the line address control circuit 563, and writing to the frame memory 157 is prohibited.
In the second line, the changeover switch 534 is connected to the b side, the line address control circuit 563 outputs the increment signal INC, and the output signal of the changeover switch 534 is written in the frame memory 157.

By the way, in the above control, a non-interlaced signal is favorably formed regardless of the phase of the frame pulse.
This means that control may start from any field, even or odd. As a result, the interlaced signal can be converted to the non-interlaced signal without performing the field determination of the video signal SVs on the writing side.

Returning to FIG. 2, each scanning line signal of the non-interlaced signal related to the luminance signal Y and the dot-sequential signal RY / B-Y output from the thinning circuit 154 is written in the frame memory 157.

FIG. 8 is a diagram showing a specific configuration example of the write control circuit 158.

In the figure, the write clock WCK is supplied to the counter 581, and the horizontal sync signal WHD from the sync separation circuit 159 is supplied to this counter 581 as a reset signal. Then, the count output of the counter 581 is supplied to the frame memory 157 as a horizontal address.

The horizontal sync signal WHD from the sync separation circuit 159 is supplied to the counter 582 as a clock, and the vertical sync signal WVD from the sync separation circuit 159 is supplied to the counter 582 as a reset signal. Also, this counter 58
2 is the increment signal INC from the thinning control circuit 156.
Is supplied as a counter enable signal. And
The MSB-1 to LSB of the count output of the counter 582 are supplied to the frame memory 157 as the MSB-1 to LSB of the line address (vertical address).

The MSB of the count output of the counter 582 is supplied to one input terminal of the exclusive OR circuit 583, and the inverted signal INV from the outpacing determination circuit 161 is supplied to the other input terminal of the exclusive OR circuit 583. Then, the output signal of the exclusive OR circuit 583 is supplied to the frame memory 157 as the MSB of the line address.

In this case, when the inverted signal INV is supplied from the overtaking control circuit 161, the output signal of the exclusive OR circuit 583, and thus the state of the MSB of the line address is inverted,
This inverts the field on the write side. Further, when the increment signal INC is supplied from the thinning control circuit 156, the counter 582 becomes a countable state and the line address is incremented. At this time,
Since the write enable signal WE is supplied to the frame memory 157, the frame memory 157 becomes a writable state.

Further, the MSB of the count output of the counter 582 is supplied to the outpacing determination circuit 161, and in the outpacing determination circuit 161, the inverted signal INV is formed by comparison with the MSB of the read line address, as described later.

The write control circuit 158 in the example of FIG. 8 is an example in which the frame memory 157 is configured by using a normal RAM, but the frame memory 157 may be configured by using an IC dedicated to the field memory. In that case, it can be configured more easily.

By the write address thus formed by the write control circuit 158, a non-interlaced signal is written in each field portion of the frame memory 157 as shown in FIG. FIG. 9 shows a case where the number of lines in one field is nine for simplification.

Next, how to read the non-interlaced signal relating to the luminance signal and the dot-sequential color difference signal written in the frame memory 157 in this way will be described. At the same time, how to create the main scanning line signal and the interpolation scanning line signal will be described.

In FIG. 2, reference numeral 162 is a read clock generation circuit configured by using a PLL circuit or the like. The frequency of the read clock RCK generated by the clock generation circuit 162 affects the horizontal length of the child screen. For example, as described here, if you want to set the display area ratio to 1/9,
The frequency may be set to about 3 times the write clock WCK.

The read clock RCK is preferably the same as the clock used in the circuit that processes the color video signal SV in FIG.

The read clock RCK is supplied to the frame memory 157. Here, the frame memory 157 operates as a time base compression means.

Further, in FIG. 1, the vertical sync signal PH and the horizontal sync signal PV of the color video signal SV separated by the sync separation circuit 11 are supplied to the field determination circuit 163. The field determination circuit 163 determines the even / odd field of the parent screen video signal based on the phases of the synchronization signals PV and PH.

For example, a field in which the phases of the horizontal synchronizing signal PH and the vertical synchronizing signal PV match as shown in FIGS. 10A and 10B, respectively, is determined to be an odd field, while the horizontal synchronizing signal PH and the vertical synchronizing signal PV are A field whose phase is deviated by 1/2 horizontal period (H / 2) as shown in C and D of FIG. In this case,
As shown in FIG. 11, it is assumed that the scan lines in the even field are above the same scan line in the odd field.
Note that FIG. 11 shows a case where the number of scanning lines in one frame is nine.

The determination signal FD from the field determination circuit 163 is supplied to the read control circuit 164. This read control circuit 1
The synchronizing signals PV and PH are supplied to 64, and the read clock RCK from the clock generation circuit 162 is also supplied. Then, a read address of the frame memory 157 is formed based on these, and the non-interlaced signal written in the frame memory 157 is converted into an interlaced signal that matches the interlaced order of the parent screen video signal and read. The meaning of the interlaced rank will be described later.

The sub-picture video signal relating to the luminance signal and the dot-sequential color difference signal read from the frame memory 157 is delayed by the delay circuit 165.
Supplied to The delay circuit 165 has a sub-screen display area ratio of 1
In the case of / 9, it is composed of a delay line having a delay time of about 1/3 of one horizontal period.

The input signal and the output signal of the delay circuit 165 relating to the luminance signal are supplied to the output terminals 166 and 167 as the interpolation scanning line signal yi and the main scanning line signal yr of the luminance signal, respectively.
The output signal of the delay circuit 165 relating to the dot-sequential color difference signal is supplied to the output terminal 168 as a dot-sequential signal r-y / by.

These signals yi, yr and ry / by are supplied to the fixed terminal on the s side of the changeover switch 13 shown in FIG. 1 as described above, and the parent screen video signals Yi, Yr and R- are supplied. Y / B-
After being inserted in Y, it is sequentially supplied to the insertion scanning conversion circuit 7.

By the way, the progressive scan conversion in the progressive scan conversion circuit 7 is performed as described with reference to FIG. Here, how to read the non-interlaced signal written in the frame memory 157 so as to match the interlaced order of the main screen video signal will be described.

Here, in the interlaced order, in the parent screen video signal, the first main scanning line signal of a certain field is converted into the first scanning line and displayed, or is converted into the second scanning line. It is the distinction that is displayed.

In the field in which the first scan line of the parent screen video signal is the main scan line signal, the operation of matching the interlaced ranks is also the main scan line signal for the first scan line of the child screen video signal. In a field in which the second scanning line of the parent screen video signal is the main scanning line signal, the second scanning line of the child screen video signal is operated to be the main scanning line signal. It means to do.

Further, it is assumed that the progressive scan conversion circuit 7 is configured such that the conversion of FIG. 16A is performed in the odd field and the conversion of FIG. 16B is performed in the even field.

When reading a signal from the frame memory 157, as shown in FIG.
It should be noted that the scan line signal corresponding to the first scan line of the even field in FIG. 11 is not written.

That is, in order to match the interlaced order with the parent screen video signal, the child screen video signal is set to the main scanning line signal yr in the odd field, and 1, 3, 5 ,.
, And the scanning line signals of 2, 4, 6, ... Must be read as the interpolation scanning line signal yi.
On the other hand, in the even field, the main scanning line signal yr
It is necessary to read out the scanning line signals 2, 4, 6, ... In the figure, and read out the scanning line signals 3, 5, 7, ... As the interpolating scanning line signals yi.

That is, the main scan line signal yr read first in the odd field
Is the first scanning line in FIG. 9, and the main scanning line signal yr read first in the even field is controlled to be the second scanning line in FIG.

In this case, since the non-interlaced signal for two fields is written in the frame memory 157, either field portion may be assigned to either field of the parent screen video signal. That is, the frame memory 157
The signals may be read out alternately from the two field portions according to the field determination result of the parent screen video signal as described above.

Here, a specific configuration example of the read control circuit 164 will be described with reference to FIG.

In the figure, the read clock RCK from the read clock generation circuit 162 is supplied to the counter 641. The horizontal synchronizing signal PH is supplied to the counter 621 as a reset signal via the delay circuit 642, the delay circuit 643, and the OR circuit 644. Then, the count output of the counter 641 is supplied to the frame memory 157 as a horizontal address.

In this case, the counter 641 has the sub-screen horizontal position adjustment circuit 6
Read start signal Hs1 delayed by the time set in 45
And the read start signal Hs1 is further reduced to about 1/3 by the delay circuit 643.
It is reset by the read start signal Hs2 delayed by the horizontal period. That is, horizontal reading from the frame memory 157 is started from these two reset timings.

As will be described later, the timing of the read start signal Hs2 delayed by the delay circuit 643 becomes the horizontal display start position of the small screen.

The delay amount of the delay circuit 642 is configured so that it can be adjusted in units of, for example, one cycle of the read clock RCK. Here, as the delay amount increases, for example, the display position of the small screen is on the right side.

The output signal of the OR circuit 644 is supplied to the counter 646 as a clock. The vertical synchronizing signal PV is supplied to the counter 646 as a load signal via the delay circuit 647. The field determination signal FD from the field determination circuit 163 is supplied to the counter 646 as the LSB of the load data. The other bits of the load data are set to low level “0”, for example. Field decision signal FD
Is set to a low level "0" in an odd field, and is set to a high level "1" in an even field. Then, the count output of the counter 646 is supplied to the frame memory 157 as MSB-1 to LSB of the line address (vertical address).

Further, the field determination signal FD from the field determination circuit 163 is supplied to the inverter 648, and this inverter 648
Is output to the frame memory 157 as the MSB of the line address.

In this case, since the state of the MSB of the line address changes according to the field determination signal FD, the two field portions of the frame memory 157 are alternately read according to the even / odd field of the parent screen video signal.

In the case of odd fields, the line address
Since the LSB first becomes “0”, 1, 3, 5, ... At the timing of the read start signal Hs1 output from the delay circuit 642.
, The scanning line signals are sequentially read, and at the timing of the read start signal Hs2 output from the delay circuit 643, 2, 4, 6 ,.
.. The scanning line signals of are sequentially read.

On the other hand, in the case of an even field, the line address
Since the LSB first becomes "1", at the timing of the read start signal Hs1 output from the delay circuit 642, 2, 4, 6, ...
, The scanning line signals are sequentially read, and at the timing of the read start signal Hs2 output from the delay circuit 643, 3, 5, 7, ...
.. The scanning line signals of are sequentially read.

In this case, the vertical sync signal PV is delayed by the time set by the sub-screen vertical position adjustment circuit 649 and then the counter 6
It is supplied to 46 and the load data is loaded to the counter 646. That is, the reading of the frame memory 157 in the vertical direction is started from this load timing, and the vertical display start position of the small screen is determined.

In addition, the read start signal H output from the delay circuit 643
s2 is supplied to the child screen length creation circuit 650. From the small screen length creating circuit 650, for example, the high level “1” is set only during the period for displaying the small screen from the timing of the read start signal Hs2 (for example, 1/3 horizontal period when the display area ratio is 1/9). In other periods, a signal that is low level "0" is output. The output signal of the creating circuit 650 is the AND circuit 6
Supplied to 51.

Further, the vertical synchronizing signal PV delayed by the delay circuit 647 is supplied to the child screen height creating circuit 652, and from this creating circuit 652, the child screen is displayed from the timing of the vertical synchronizing signal PV (for example, the display area ratio). Is 1/9, the signal is high level "1" only for 1/3 field period, etc.) and is low level "0" in other periods. And
The output signal of the creating circuit 652 is supplied to the AND circuit 651.

The AND circuit 651 outputs a signal having a high level "1" during the display period of the small screen and a low level "0" during the other periods. The output signal of the AND circuit 651 is supplied to the changeover switch 13 of FIG. 1 as the changeover control signal SW via the output terminal 169 shown in FIG.

The MSB of the read line address output from the inverter 648 is supplied to the outpacing determination circuit 161. Even if not mentioned above, in the overtaking judgment circuit 161, the MSB of the read line address and the MSB of the write line address (see FIG. 8) are constantly monitored, and when they have the same polarity, a high level "1" for inverting the write field is obtained. The inverted signal INV of is output.

Note that the read control circuit 164 in the example of FIG. 12 shows an example in which a normal RAM is used as the frame memory 157, but the frame memory 157 is configured using an IC dedicated to the field memory. Of course, in that case, a simpler configuration can be adopted.

Now, the signals read out so that the interlaced ranks match as described above are the main scanning line signals as follows.
It is output to the changeover switch 13 as a pair of yr and the interpolation scanning line signal yi.

That is, in an even field, scanning line signals of 1, 3, 5, ..., Which are read as main scanning line signals yr, and scanning of 2, 4, 6, ..., Which are read as interpolation scanning line signals yi The line signals are simultaneously supplied to the changeover switch 13 as a pair of 1 and 2, 3 and 4, 5 and 6, and in the odd field,
The scanning line signals of 2, 4, 6, ..., Which are read as the main scanning line signal yr, and the scanning lines signals of which are read as the interpolating scanning line signal yi 3, 5,
The scanning line signals of 7, ... Must be supplied to the changeover switch 13 at the same time in pairs of 2 and 3, 4 and 5, 6 and 7.

In this way, as a pair, the sequential scanning conversion circuit 7 of FIG. 1 outputs the non-interlaced scanning conversion as shown in FIG. 16 for the main scanning line signal and the interpolating scanning line signal inputted at the same time. It is configured to do so.

Here, the delay circuit 165 converts the scanning line signals of 1, 2, 3, 4, 5, ... It is used for the purpose of creating pairs such as 6.

 This situation will be described with reference to FIG.

FIG. 13 shows a read start signal Hs1 (shown in FIG. A).
3 is a timing chart based on the read start signal Hs2 (shown in FIG. 4B).

 In the figure, an odd field is shown as an example.

As described above, in the case of odd fields, the scanning line signals 1, 3, 5, ... Are sequentially read at the timing of the read start signal Hs1, and the read start signal output from the delay circuit 623 starts. The scanning line signals of 2, 4, 6, ... Are sequentially read at the timing of the signal Hs2. Then, the read signal is supplied to the delay circuit 165 shown in FIG. 2 (see C in the same figure).

As described above, the delay amount of the delay circuit 165 is made equal to the difference between the read start signal Hs1 and the read start signal Hs2, that is, the delay amount of the delay circuit 643 (about 1/3 horizontal period). Therefore, the read start signal H
Based on the timing of s2, the read start signal is read at the same timing as the scanning line signals of 2, 4, 6, ...
Input according to the timing of Hs1, 1,3,5, ...
The scanning line signal of is obtained (see D in the same figure).

Therefore, if the input signal and the output signal of the delay circuit 165 are supplied to the fixed terminal on the s side of the changeover switch 13 as the interpolating scanning line signal yi and the main scanning line signal yr of the sub-screen video signal, respectively, the interlaced order is obtained. , Main scan line signal
A signal in which the pair of yr and the interpolation scanning line signal yi is correctly controlled is output.

It should be noted that the signal is output correctly at T0 during about 1/3 horizontal period from the read start signal Hs2, as is clear from FIG.

Therefore, the child screen length creation circuit 650 of FIG. 12 supplies the AND circuit 651 with, for example, a high level “1” signal for about 1/3 horizontal period from the timing of the read start signal Hs2. That is, the change-over switch 13 is switched to the s side only during this period, and the sub-screen video signal is inserted into the recording surface video signal.

The signal switched in this way is supplied to the progressive scan conversion circuit 7 of FIG. 1 and is sequentially converted as described above, so that the parent screen and the child screen inserted at a predetermined position on the parent screen are displayed. Displayed in non-interlaced.

In the signal processing unit 15 of the above-described embodiment, the line-sequential signals r-y / by are output with respect to the color difference signals, and those corresponding to the interpolation scanning line signal yi related to the luminance signal are not output. However, the progressive scan conversion circuit 7 may be configured to perform the progressive scan conversion similarly to the luminance signal by outputting the signal corresponding to the interpolation scanning line signal similarly to the luminance signal.

As described above, in this example, the video signal SVs
Is interlaced and written in each field portion of the frame memory 157 in a non-interlaced manner. Then, based on the field determination result of the parent screen video signal, the child screen video signal is read from the frame memory 157 while performing interlace conversion so that the parent screen video signal has the correct interlaced rank. Furthermore, the output signal is a main scan line signal created with attention to such interlaced rank.
It is controlled to be yr and the interpolation scanning line signal yi.

By the way, the pass band related to this processing is as shown in FIG. 23, and the area portion is increased as compared with that shown in FIG. As a result, the amount of information displayed can be doubled as compared with the example shown in FIG.

As described above, in this example, higher image quality can be expected than in the configuration of FIG. The same operation is not limited to the two-screen processing. Figure 17 Compared to the one that tries to perform some signal processing on the television signal at the input terminal of the high-definition television by connecting as in the example in Fig. 17, the amount of information that is necessarily reduced will be reduced and high image quality will be realized. it can.

This is because the configuration of this example has two sets of signal processing units that are important for a high-definition television, such as the Y / C separation circuit and the interpolation scanning line signal forming unit, so each processing unit is optimal for the purpose. This is because signal processing can be performed.

In addition, if it is desired to read out signals from a memory written in a non-interlaced manner and switch and display them, even in cases other than the example of the two-screen television described here (for example, when displaying characters such as channel signs). The purpose can be achieved by creating the main scanning line signal and the interpolating scanning line signal by the method described in this example and switching them separately.

Further, in this example, since the signal switching is performed by using the main scanning line signal and the interpolating scanning line signal before the sequential scanning conversion, it is not necessary to use many expensive high-speed operation parts.
Technical problems can be reduced.

[Effects of the Invention] As described above, according to the present invention, since a plurality of sets of main complementary signal processing units, which are basic signal processing units of high-definition televisions, are provided, the purpose of each main complementary signal generation unit is It is possible to perform optimum signal processing suitable for As a result, the amount of information reduced in the signal processing process can be minimized. Therefore, according to the present invention, it is possible to provide a high-definition television having a multi-function and the highest image quality.

Further, since the signals are switched using the main scanning line signal and the interpolating scanning line signal before the sequential scanning conversion, it is not necessary to use many expensive parts, and the cost reduction effect can be expected.

As described above, according to the present invention, not only the function of improving the image quality but also the effect of cost reduction can be expected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 to FIG. 6 are configuration diagrams of the screen television signal processing unit, and FIG. 7 is an explanatory diagram of interlacing when the display area ratio is 1/9.
FIG. 8 is a block diagram of the thinning circuit and the thinning control circuit when the display area ratio is 1/9, FIG. 8 is a block diagram of the write control circuit, and FIG. 9 is a diagram showing the write state of the frame memory.
FIG. 10 and FIG. 11 are explanatory views of determination of even and odd fields,
FIG. 12 is a configuration diagram of a read control circuit, FIG. 13 is an explanatory diagram of pair creation of main interpolation scanning line signals, FIG. 14 is a configuration diagram of an example of a high definition television, and FIG. 15 is a main auxiliary signal forming circuit. Configuration diagram, No.
FIG. 16 is an explanatory diagram of the progressive scan conversion process, FIGS. 17 to 19 are configuration diagrams of a conventional example, and FIGS. 20 to 24 are explanatory diagrams of a signal band in the space-time domain. 1,14 ...... Input terminal 2 ...... A / D converter 3 ...... Y / C separation circuit 4 ...... Motion detection circuit 5 ...... Main auxiliary signal forming circuit 6 ...... Color demodulation circuit 7 ...... Sequential scanning conversion circuit 8 ... Matrix circuit 9 ... D / A converter 10 ... Color picture tube 11 ... Synchronous separation circuit 12 ... Deflection circuit 13 ... Changeover switch 15 ... Two-screen TV signal processing unit

Claims (2)

(57) [Claims] 1. A plurality of main complementary signal forming means for processing each of a plurality of television signals to form a main scanning line signal and an interpolation scanning line signal, and a plurality of outputs from the plurality of main complementary signal forming means. Switch means for selecting one of the main scanning line signal and the interpolating scanning line signal, and scan converting means for performing non-interlace conversion using the main scanning line signal and the interpolating scanning line signal selected by the switching means. Television receiver. 2. A television receiver capable of switching and displaying a plurality of television signals, wherein one television signal system among the plurality of television signals stores the television signals in a non-interlaced manner. Memory means, a delay means having a delay time substantially equal to a time for displaying an image by the television signal read from the memory means, and a field of a synchronization signal used for reading the television signal from the memory means. The determination means for determining the attribute and the reading from the memory means are controlled based on the field attribute determined by the determination means, and the input signal and the output signal of the delay means are interpolated scanning line signal and main scanning line, respectively. And a control means for allocating the signal to another television signal among the plurality of television signals. The signal system is provided with main complementary signal forming means for processing a television signal to form a main scanning line signal and an interpolated scanning line signal, and a plurality of main scannings obtained from the one and other television signal systems. A television comprising a switch means for selecting one of a line signal and an interpolated scan line signal, and a scan conversion means for performing non-interlace conversion using the main scan line signal and the interpolated scan line signal selected by the switch means. John receiver.