JPH11308550A - Television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide multi-picture display with high picture quality by performing optimum video composite and scan conversion corresponding to the scanning system of respective video signals in the case of simultaneously displaying plural videos on one display device. SOLUTION: In the case of two-picture display, a main picture video signal from an A/D converter ADC1 is written in a video reduction memory 3 while limiting its band corresponding to the reduction rate through an LPF1 2 and a sub picture video signal from an ADC2 is written in a frame sync memory 5. Afterwards, the signals are read out while using the synchronism, synchronous converting processing is performed and the signals are written in a video reduction memory 7 while limiting the band corresponding to the reduction rate through an LPF2 6. A control circuit 9 reads the video signals out of the respective memories 3 and 7 and controls the input select signal of a selector 8 so as to provide a two-picture composite video, a scanning video operating circuit 20 calculates an interpolated line scanning video signal adaptive for the motion, that signal is inputted to a double speed scan converting circuit 40 together with a current line scanning video signal and after scanning is made into double speed, a double speed video signal is prepared by compositing two signals while switching them for every double speed scanning.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a television receiver for simultaneously displaying images of different scanning systems on one display device.

[0002]

2. Description of the Related Art In recent years, as television receivers have become larger, have higher image quality, and have diversified video media, the demand for simultaneously viewing and enjoying these various video media has been increasing. In order to respond to this, technology development for simultaneously displaying these various kinds of video media on one display device with high image quality has been actively performed.

A conventional television receiver capable of two-screen display with double-speed scanning conversion capable of simultaneously displaying two screens while improving image quality will be described.

[0004] Figs.
FIG. 1 is a block diagram of a conventional television receiver capable of simultaneously displaying screens. FIG. 10 is a block diagram showing an embodiment of the present invention. In FIG. 10, 1
Is an A / D converter for inputting and A / D converting a reference video signal serving as a reference for display synchronization when performing two-screen display,
A low-pass filter that limits the bandwidth of the video as a pre-process in order to reduce the output video of the D converter 1, a video reduction image memory 3 that reduces the output video of the low-pass filter 2 by thinning-out processing, and 4 an A / A An A / D converter for inputting and A / D converting an image to be displayed simultaneously with an image signal to be input to the D converter 1, and an output image of the A / D converter 4 converts the output image of the A / D converter 4 into a reference image signal and a frame frequency period of the image. An image memory for frame synchronization that performs synchronous conversion processing for synchronization, 6 is a low-pass filter that limits the band of an image as pre-stage processing to reduce the output image of the A / D converter 2, and 7 is a low-pass filter 6 A video reduction image memory for reducing the output video of the video memory by thinning-out processing; 8 receives the output video of the video reduction image memories 3 and 7 and selects both signals to display the video during the video display A selector 9 performs a video synthesis by switching, a control circuit 9 generates a control signal for writing and reading data to and from the image memories 3, 5 and 7, and a switching control signal of the selector 8, and 20 denotes a video synthesized by the selector 8. 1 using a memory as a signal input
A scanning video arithmetic circuit for calculating a video signal for double-speed scanning by generating and calculating signals such as a scanning delay, a field delay, and a frame delay, and 40 are two types of double-speed scanning calculated by the scanning video arithmetic circuit 20 A double-speed scanning conversion circuit that doubles the scanning of the video signals (the current line video signal and the interpolated line video signal) and then combines the two signals.
This is a D / A converter for A-to-A conversion. FIG. 11 is a block diagram showing the internal configuration of the scanning video arithmetic circuit 20 of FIG. 7. In FIG. 11, reference numeral 21 denotes an image memory which receives a video signal synthesized by the selector 8 of FIG. 10 and delays it by one scanning period. , 22 are adders for adding the input video and the output video of the image memory 21 and then correcting the amplitude to 、.
Is an image memory that receives the output video signal of the image memory 22 and delays 262 scanning periods, 24 is an image memory that receives the output video signal of the image memory 23 and delays 263 scanning periods, and 25 is an image memory that inputs the video signal to the image memory 23. A motion detecting circuit which receives a video signal output from the image memory 24 as input and performs a moving image / still image discrimination with respect to a previous frame in units of display pixels based on a difference between the two signals. Motion detection circuit 2
5 is a MIX circuit that performs an addition process on both signals on a pixel-by-pixel basis while controlling the addition ratio of both signals with the control signal from the control signal 5.
FIG. 12 is a block diagram showing the internal configuration of the double-speed scanning conversion circuit 40 shown in FIG.
Reference numeral 1 denotes an image memory for converting the scanning of the current line scan video output from the scanning video arithmetic circuit 20 having the input video information as it is to a double speed, and 42 denotes the same circuit calculated by the calculation in the scanning video arithmetic circuit 20 , An image memory for converting the scanning of the interpolated line-scanned video to 2 × speed, a control circuit 43 for generating a write reset signal, a read reset signal, and a read enable signal which are control signals for the image memories 41 and 42, and 44 for an image. An inverting circuit for inverting the read enable signal to the memory 41 and inputting the inverted signal to the read enable signal input of the image memory 42. The inverting circuit 52 uses the signal from the control circuit 43 as an input switching selection signal.
A selector for selecting and outputting the output video signals 1 and 42.

[0005] The operation of the television receiver configured as described above will be described below.

[0006] 1. Screen Display When a single screen display and a type of display video are designated by the user, a corresponding video signal is input from the A / D converter 1 and written into the image memory 3. The selector 8 always selects and outputs the video signal from the image memory 3.
The output video signal of the selector 8 is supplied to the post-scanning video conversion circuit 2
0, and an interpolated line scanning video signal that has been subjected to scan conversion that is motion-adapted to the current line scanning video signal is calculated.
More specifically, referring to FIG. 11, the output video signal of the selector 8 is first delayed by the image memory 21 by one scanning period. The output video signal of the image memory 21 becomes the current line scanning video signal. On the other hand, the motion detection circuit 25 receives the output video signal of the image memory 21 and the output video signal of the image memory 24 obtained by further delaying the same output video signal by one frame scanning period. Calculation is performed in pixel units, and the motion amount of each pixel with respect to the image of the previous frame is detected. At this time, when the difference value is large, it is determined that the motion is large, and when the difference value is small, it is determined that the motion is small. On the other hand, in the MIX circuit 26, the output video signal of the image memory 23 and the output video signal of the adder 22 are fixed according to the motion detection signal, which is the output signal of the motion detection circuit 25, as a control signal. Add by ratio. Here, the output video signal of the adder 22 is stored in the image memory 2
After adding the input and output video signals of 1, the amplitude is reduced to 1 /
It is obtained by correcting to 2. That is, by the above processing, the interpolated scanning video signal is converted into a still image video by converting the output video signal of the image memory 23 delayed by one field with respect to the output video signal of the image memory 21 at the time of a still image, that is, the video signal interpolated between the fields. In the case of a moving image, the output image of the adder 22, in which the input and output video signals of the image memory 21 are added and the amplitude of which is corrected, that is, the video signal interpolated in the field (interpolated between lines) is interpolated as a moving image.
The current line scanning video signal and the interpolated line scanning video signal output from the scanning video conversion circuit 20
0, the scanning is doubled using the image memory.
Thereafter, the above two signals are switched and synthesized by the internal selector at every double-speed scanning, thereby generating a double-speed scanning video signal. More specifically, referring to FIG. 12, the current line scanning video signal and the interpolated line scanning video signal output from the scanning video conversion circuit 20 are both written in the image memories 41 and 42 in one scanning cycle. Reading is performed at twice the speed and cycle of writing. Further, for read, output enable control is performed, and the control signal is a signal whose cycle is equal to the write reset signal to the image memories 41 and 42 and whose change point at a duty of 50% is equal to the read reset signal. The polarity of the enable signal is inverted in the image memories 41 and 42.
That is, in the double-speed scanning, the output of the image memory 41 is enabled during the current line scanning, and the output of the image memory 42 is enabled during the interpolation line scanning. In the subsequent selector 52, the image memory 4 in the enabled state is
1 and 42 are selected as input signals and the current line video,
It is output as a double-speed scanning video signal in which the interpolation line video is synthesized.

[0007] 2. Screen Display When the user specifies the type of reference video (display video on the main screen) as a reference for two-screen display and display synchronization, and the type of video (display video on the sub-screen) displayed simultaneously with the reference video signal , The corresponding main screen video signal is input from the A / D converter 1, and after being subjected to band limitation according to the reduction ratio by the low-pass filter 2, is written into the image memory 3.
Further, the corresponding sub-screen video signal is input from the A / D converter 4 and written into the image memory 5. The image memory 5 writes the video signal to the memory using the synchronization of the sub-screen video, and reads the video signal from the memory using the synchronization of the main screen video. Synchronous conversion processing for synchronizing with the main screen video is performed in the frequency cycle (frame synchronization processing). At this time, if the frame frequency is different between the main screen image and the sub-screen image, the phase of the vertical synchronization signal between the main screen image and the sub-screen image is detected, and the display sub-screen image is shifted by one or more fields. The control circuit 9 controls the write / read control signal of the image memory 5 so that the phase difference does not occur (overtaking / overtaking control). The output sub-screen image of the image memory 5 synchronized with the main screen image by the image memory 5 is subjected to band limitation according to the reduction ratio by the low-pass filter 6, and then written to the image memory 7. Thereafter, the control circuit 9 controls the display phase of the main screen video and the sub-screen video, and the display boundary line phase, by controlling the video signal read-out phase of the image memories 3 and 7 and the input selection control signal of the selector 8 to form a two-screen composite video. To achieve. Further, the output video signal of the selector 8 is thereafter input to the scanning video conversion circuit 20, and the sequential scanning conversion process is performed. However, the subsequent processes are the same as those in the case of displaying one screen, and will not be described. FIG. 13 shows the video signal of each unit at this time. Further, the main screen video input is called a non-standard signal. For example, a frame of 262 lines of a progressive scanning signal output from a certain game, and the sub-screen video signal input is an image of each part when an NTSC interlaced scanning signal is input. The signals are described in FIG.

[0008]

However, after the composition of the main and sub-screens is performed as in the above-described conventional example, the image is converted into a single image and the uniform double-speed scan conversion processing is performed on the entire screen. For example, when a terrestrial broadcast and a partial VTR are blue-backed, when a terrestrial broadcast is a game video, and the like, the main screen video and the sub-screen video are scanned in a vertical direction when the interlaced scanning method and the sequential scanning method are mixed. It is said that image quality deterioration such as overlapping of images occurs, and that a screen having a high image scanning frequency such as HDTV must be subjected to a signal format conversion to a pseudo NTSC system as a pre-process and then combined with a screen. There is a problem regarding image quality deterioration during multi-screen display.

In view of the above problems, the present invention detects an image and a synchronization signal of an input image at the time of multi-screen display, and controls a scan conversion method in accordance with the detection result, thereby achieving an optimum high image quality for the input image. It is an object of the present invention to provide a television receiver capable of realizing multi-screen display that has been subjected to double-speed scanning conversion.

[0010]

According to the present invention, there is provided a television receiver comprising: a line memory for delaying a synthesized video signal by one scanning period; an input video signal; And a second selector for selecting and outputting an input video signal and an output video signal of the line memory based on an output signal of the scanning scheme discriminating circuit. Controls whether or not to perform processing for switching whether or not to delay the synthesized video signal before double-speed scan conversion by one scanning period at the field frequency of the reference video signal in accordance with the result of scanning method determination of the input video signal in If the scanning method of the input video before synthesis is progressive scanning, the subsequent double-speed scanning conversion is switched from motion-adaptive progressive scanning to simple double-write double-speed scanning. This is a process for switching.

According to the present invention, for example, at the time of terrestrial broadcasting and partial VTR blue-back, at the time of terrestrial broadcasting and game video,
Television that enables multi-screen display without image degradation such as overlapping of images in the vertical direction even when interlaced scanning and progressive scanning are mixed as the main and sub-screen video scanning methods. A receiver can be provided.

(2) The present invention provides a scanning method discriminating circuit for detecting and discriminating a scanning method of an input video signal, and delaying each video signal reduced in the horizontal direction and displayed on a multi-screen by an independent delay amount. A video synthesizing / scan converting circuit which performs a video synthesizing process and a scan converting process by using the memory signal to be output and the video signal which has been delayed in the memory and which has been subjected to the horizontal reduction process as an input signal as an output signal of the scanning type discriminating circuit as a control signal In accordance with the result of the scanning method discrimination of the input video signal in the scanning method discriminating circuit, the amount of delay of each input video signal by the memory is independently switched and controlled, and the video synthesis of each input video signal for multi-screen display is performed. The processing for switching the method and the scan conversion method is performed.

According to the present invention, it is possible to display a multi-screen image having a high image scanning frequency such as an HDTV without performing a signal format conversion to the pseudo NTSC system which is conventionally required as a pre-stage process. It is possible to prevent deterioration in image quality and resolution due to down-conversion of the scanning rate for images having a high image scanning frequency, and to scan in the conventional configuration such as the NTSC system which simultaneously displays images having a high image scanning frequency. It is possible to provide a television receiver that realizes a high-quality multi-screen display, which can generate a possibility of further improving the image quality by up-conversion of the scanning rate even for an image that can be displayed without down-conversion of the rate.

(3) The present invention analyzes the video information of the input video signal and sets the image start scanning line in the field for the interlaced input video and the frame in the progressive scan input video. By a video start line detection circuit and an effective video scanning line detection circuit that detects the phase with the vertical synchronization signal and the number of effective video scanning lines for the input video signal and outputs the detection result to a control circuit that controls the video reduction process, According to the phase detection result between the video start scanning line and the vertical synchronization signal of the input video signal in the video start line detection circuit, the readout phase of the video signal from the video reduction processing memory and the switching phase of the selector for performing the video synthesis processing are changed. Control of the image reduction processing memory in accordance with the result of detection of the number of effective image scanning lines of the input image signal in the effective image scanning line number detection circuit. It is intended to switch the magnification.

According to the present invention, even when the number of scanning lines is the same, but the effective phase of the image or the number of effective scanning lines are different, the input video signal is analyzed, and based on the analysis result, the display during multi-screen display is performed. Calculate phase and scan conversion method, scan conversion,
It is possible to provide a television receiver capable of automatically performing optimal multi-screen display by synthesizing images.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, when a plurality of video signals are scan-converted to a reference video signal and the plurality of video images are simultaneously displayed on one display device, they are displayed simultaneously. Detecting the scanning method of each video signal, switching the synthesizing method and scan conversion method at the time of video synthesis based on the detection result, and performing optimal video synthesis and scan conversion according to the scanning method of the input video to achieve high image quality. A television receiver capable of realizing multi-screen display. For example, at the time of terrestrial broadcasting and blue-back of some VTRs,
When terrestrial broadcasting and game images are used, when the interlaced scanning method and the sequential scanning method are mixed as the scanning method of the main screen image and the sub-screen image, image quality deterioration such as overlapping of images in the vertical direction does not occur. This has the effect of enabling screen display.

According to a second aspect of the present invention, a first memory for reducing a reference video signal and a video signal displayed simultaneously with the reference video signal are synchronized with a frame frequency of the video. A second memory for performing processing for
A third memory for reducing a video signal displayed simultaneously with the reference video signal; a reference video signal reduced by the first memory and a reference video signal reduced by the third memory; A selector for performing a synthesizing process with a video signal to be displayed, a control circuit for generating a control signal for the first to third memories and a selection signal for the selector, and a scanning method for the reference video signal and a video signal to be simultaneously displayed And a scanning method discriminating circuit for detecting and discriminating a video signal synthesized by the selector and detecting a motion amount between frames of the signal when the motion amount is small. Calculates the interpolated line scanning video signal by field interpolation and delays the input video to make the current line scanning video signal the same phase as the interpolated line scanning video signal A scanning video calculation circuit for outputting the current line scanning video signal and the interpolated line scanning video signal output from the scanning video calculation circuit. A double-speed scan conversion circuit for performing composition by the scanning method discrimination circuit. A television receiver that can control whether or not to perform a process of switching whether or not to delay the scanning period. For example, at the time of terrestrial broadcasting and a partial VTR blueback, at the time of terrestrial broadcasting and game video,
Even when the interlaced scanning method and the sequential scanning method are mixed as the scanning method of the main screen image and the sub-screen image, it is possible to perform multi-screen display without image deterioration such as overlapping of images in the vertical direction. Having.

According to a third aspect of the present invention, a first memory for reducing a reference video signal and a video signal displayed simultaneously with the reference video signal are synchronized with a frame frequency of the video. A second memory for performing processing for
A third memory for reducing a video signal displayed simultaneously with the reference video signal; a reference video signal reduced by the first memory and a reference video signal reduced by the third memory; A selector for performing a synthesizing process with a video signal to be displayed, a control circuit for generating a control signal for the first to third memories and a selection signal for the selector, and a scanning method for the reference video signal and a video signal to be simultaneously displayed And a scanning method discriminating circuit for detecting and discriminating a video signal synthesized by the selector and detecting a motion amount between frames of the signal when the motion amount is small. Calculates the interpolated line scanning video signal by field interpolation and delays the input video to make the current line scanning video signal the same phase as the interpolated line scanning video signal And a scan video calculation circuit for outputting the current scan image signal and the interpolated line scan video signal output from the scan video calculation circuit. A double-speed scan conversion circuit for performing a double-speed scan conversion and a motion-adaptive sequential scan conversion as double-speed scan conversion in accordance with a result of the scan method determination of the reference video signal and the video signal to be simultaneously displayed in the scan mode determination circuit. A television receiver that can switch between writing double-speed scanning conversion and
For example, in the case of terrestrial broadcasting and some VTR blue-back, in the case of terrestrial broadcasting and game video, etc., the interlaced scanning method and the sequential scanning method are mixed as the scanning method of the main screen image and the sub-screen image. When displaying the input video at double speed scanning, the video display by the motion adaptive progressive scanning conversion,
During double-speed scanning display of progressive scanning input video, video is displayed by simple twice writing progressive scanning conversion without deteriorating frequency characteristics even for motion video, and optimal scanning is performed for each input video of multi-screen display By switching the processing so that conversion can be performed, there is an effect that high-quality multi-screen display can be performed.

According to a fourth aspect of the present invention, a first memory for reducing a reference video signal and a video signal displayed simultaneously with the reference video signal are synchronized with a frame frequency period of the video. A second memory for performing processing for
A third memory for reducing a video signal displayed simultaneously with the reference video signal, a control circuit for generating control signals for the first to third memories, and scanning of the reference video signal and a video signal displayed simultaneously A scanning method discriminating circuit for detecting and discriminating a method, and a video signal simultaneously displayed with the reference video signal reduced by the first memory and the reference video signal reduced by the third memory, respectively. A fourth memory for delaying by a delay amount, a video synthesis process and scanning using the output signal of the scanning mode discrimination circuit as a control signal, the reference video signal delayed by the fourth memory and the video signal to be displayed simultaneously as inputs, A video synthesizing / scan converting circuit for performing a conversion process, wherein the scanning mode discriminating circuit determines the scanning mode discrimination result of the reference video signal and the video signal to be displayed simultaneously. Controlling the delay amount of the reference video signal and the video signal to be simultaneously displayed by the fourth memory, and switching the video synthesizing method and the scan conversion method of the video signal to be simultaneously displayed with the reference video signal. Is a television receiver that can perform the above-described processing, and has a pseudo-N which is conventionally required as a pre-stage processing when displaying a multi-screen image having a high image scanning frequency such as an HDTV.
Multi-screen display can be performed without performing signal format conversion to the TSC system. For images having a high video scanning frequency, deterioration in image quality and resolution due to down-conversion of the scanning rate is prevented, and high video scanning frequency is used. It is said that even in a conventional configuration such as the NTSC system that simultaneously displays an image having an image, the image that could be displayed without down-conversion of the scanning rate can be further improved by improving the scanning rate. This has the effect that high-quality multi-screen display can be realized.

According to a fifth aspect of the present invention, a first memory for reducing a reference video signal and a video signal displayed simultaneously with the reference video signal are synchronized with a video frame frequency period. A second memory for performing processing for
A third memory for reducing a video signal displayed simultaneously with the reference video signal; a reference video signal reduced by the first memory and a reference video signal reduced by the third memory; A selector for performing a synthesizing process with a video signal to be displayed, a control circuit for generating a control signal for the first to third memories and a selection signal for the selector, and video information for the reference video signal and a video signal to be simultaneously displayed The input video of the interlaced scanning method is analyzed in the field, and the phase of the video start scanning line and the vertical synchronizing signal in the frame of the input video of the progressive scanning method are input in the field. A video start line detection circuit for detecting a signal and outputting the detection result to the control circuit; Controlling the readout phase of the video signal from the first and third memories and the switching phase of the selector according to the phase detection result between the video signal and the video start scanning line and the vertical synchronization signal of the video signal to be displayed simultaneously. This is a television receiver that can analyze the input video signal even when the number of scanning lines is the same but the effective phase of the video is different, and calculates the display phase during multi-screen display from the analysis result By performing scan conversion and video synthesis, an optimum multi-screen display can be automatically performed.

According to a sixth aspect of the present invention, a first memory for reducing a reference video signal and a video signal displayed simultaneously with the reference video signal are synchronized with a frame frequency of the video. A second memory for performing processing for
A third memory for reducing a video signal displayed simultaneously with the reference video signal; a reference video signal reduced by the first memory and a reference video signal reduced by the third memory; A selector for performing a synthesizing process with a video signal to be displayed, a control circuit for generating a control signal for the first to third memories and a selection signal for the selector, and video information for the reference video signal and a video signal to be simultaneously displayed And analyzing the number of effective video scanning lines in the field for the interlaced scanning input video and the number of effective video scanning lines in the frame for the progressive scanning input video for the reference video signal and the video signal to be displayed simultaneously. An effective video scanning line number detection circuit for outputting the detection result to a control circuit; This is a television receiver capable of switching the reduction magnification of the reduction processing performed in the third memory in accordance with the result of detecting the number of effective video scanning lines of a video signal to be displayed. Even if the number of effective scanning lines is different, the input video signal is analyzed, the scan conversion method for multi-screen display is calculated from the analysis result, and the optimum multi-screen display is automatically performed by scan conversion and video synthesis. It has the effect that it becomes possible. Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 9.

(Embodiment 1) FIGS. 1 to 3 show block diagrams of an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an A / D converter for inputting and A / D converting a reference video signal serving as a reference for display synchronization when performing two-screen display;
Is a low-pass filter that limits the band of an image as a pre-process to reduce the output image of the A / D converter 1;
Is an image memory for image reduction for reducing the output image of the low-pass filter 2 by thinning processing, and 4 is an A / D converter 1
Input the video to be displayed simultaneously with the video signal to be input to
A / D converter for D-conversion, 5 is an image memory for frame synchronization which performs synchronous conversion processing for synchronizing the output video of A / D converter 4 with the reference video signal and the frame frequency cycle of the video, and 6 is A A low-pass filter that limits the band of the video as a pre-stage process in order to reduce the output video of the / D converter 2, 7 is a video reduction image memory that reduces the output video of the low-pass filter 6 by thinning processing, and 8 is a video A selector 9 which receives the output images of the image memories 3 and 7 for reduction, selects both signals, and switches the image in the middle of the image display, performs image synthesis, and 9 is a control signal for writing and reading data to and from the image memories 3, 5 and 7. The control circuit 20 generates a switching control signal for the selector 8. The control circuit 20 receives the video signal synthesized by the selector 8 as an input and delays one scanning by using a memory. A scanning video arithmetic circuit for calculating a double-speed scanning video signal by generating and calculating a delay signal such as a field delay, a one-frame delay, etc., and 40 are two types of double-speed scanning video signals calculated by the scanning video arithmetic circuit 20 (Current line video signal, interpolation line video signal)
A double-speed scanning conversion circuit that combines the two signals after the double-speed scanning, 61 is a scanning type determination circuit that detects and determines the scanning type of the reference video signal and the video signal to be displayed simultaneously, and 71 is an output video signal of the double-speed scanning conversion circuit 40. Is a D / A converter that performs D / A conversion by using as input. FIG. 2 is a block diagram showing the internal configuration of the scanning video arithmetic circuit 20 of FIG. 1. In FIG. 2, reference numeral 21 denotes an image memory which receives a video signal synthesized by the selector 8 of FIG. 1 and delays it by one scanning period. ,
22 is an adder for adding the input video and the output video of the image memory 21 and then correcting the amplitude to 、, 23 is an image memory which receives the output video signal of the image memory 22 and delays it for 262 scanning periods, and 24 is an image memory An image memory 25 which receives an output video signal from the memory 23 and delays it by 263 scanning periods;
Is a motion detection circuit which receives a video signal input to the image memory 23 and a video signal output from the image memory 24 and performs a moving image / still image discrimination for the previous frame in units of display pixels based on a difference between the two signals. Video signal and adder 2
2 is a MIX circuit that receives two output video signals as inputs, and performs an addition process on both signals in pixel units while controlling the addition ratio of both signals by a control signal from the motion detection circuit 25. FIG.
3 is a block diagram showing the internal configuration of the double-speed scanning conversion circuit 40 shown in FIG. 1. In FIG. 3, reference numeral 41 denotes scanning of the current line scanning video output from the scanning video arithmetic circuit 20 having the input video information as it is. Is an image memory that converts the scanning of the output interpolated line scanning video from the circuit calculated by the calculation in the scanning video arithmetic circuit 20 into a double speed, and 43 is an image memory 41 and 4
A control circuit 44 for generating a write reset signal, a read reset signal, and a read enable signal, which are two control signals, inverts the polarity of the read enable signal to the image memory 41 and inputs the polarity to the read enable signal input of the image memory 42. Circuit 45, an inverting circuit for inverting the polarity of the memory read enable signal from the control circuit 43, 46, a selector for selecting and outputting one of an input signal and an output signal of the inverting circuit 45, and 47, an image from the control circuit 43 An inverting circuit for inverting the polarity of the output selection control signal of the memories 41 and 42; 48, a selector for selecting and outputting one of an input signal and an output signal of the inverting circuit 47;
Is a selector for selecting and outputting output video signals of the image memories 41 and 42 according to an input selection control signal output from the selector 48. The operation of the television receiver configured as described above will be described below.

[Single-Screen Display] When a single-screen display and a type of display image are designated by a user, a corresponding video signal is input from the A / D converter 1 and written into the image memory 3. The selector 8 always selects and outputs the video signal from the image memory 3. The output video signal of the selector 8 is thereafter input to the scanning video conversion circuit 20, and an interpolated line scanning video signal that has been subjected to scan conversion that is motion-adapted to the current line scanning video signal is calculated. More specifically, referring to FIG. 2, the output video signal of the selector 8 is
1 delays by one scanning period. The output video signal of the image memory 21 becomes the current line scanning video signal. On the other hand, the motion detection circuit 25 receives the output video signal of the image memory 21 and the output video signal of the image memory 24 obtained by further delaying the same output video signal by one frame scanning period. Calculation is performed in pixel units, and the motion amount of each pixel with respect to the image of the previous frame is detected. At this time, when the difference value is large, it is determined that the motion is large, and when the difference value is small, it is determined that the motion is small. On the other hand, in the MIX circuit 26, the output video signal of the image memory 23 and the output video signal of the adder 22 are fixed according to the motion detection signal, which is the output signal of the motion detection circuit 25, as a control signal. Add by ratio. Here, the output video signal of the adder 22 is obtained by adding the input and output video signals of the image memory 21 and then correcting the amplitude to 1/2. That is, by the above processing, the interpolation scanning video signal is output from the image memory 23 delayed by one field with respect to the output video signal from the image memory 21 at the time of a still image,
That is, the video signal interpolated between the fields is interpolated as a still image video, and in the case of a moving image, the output video of the adder 22 in which the input and output video signals of the image memory 21 are added and the amplitude is corrected, that is, the field interpolation (line interpolation) ) Is interpolated as a moving image. The current line scanning video signal and the interpolated line scanning video signal output from the scanning video calculation circuit 20 are input to the double speed scanning conversion circuit 40, and double the scanning speed using an image memory. Thereafter, the above two signals are switched and synthesized by the internal selector at every double-speed scanning, thereby generating a double-speed scanning video signal. More specifically, referring to FIG. 3, both the current line scanning video signal and the interpolated line scanning video signal output from the scanning video arithmetic circuit 20 are written to the image memories 41 and 42 in one scanning cycle. Reading is performed at twice the speed and cycle of writing. Further, output enable control is performed for reading, and the control signal has a cycle equal to the write reset signal to the image memories 41 and 42 and a duty of 5
A change point of 0% becomes a signal equal to the read reset signal. The polarity of the enable signal is inverted in the image memories 41 and 42. That is, in the double-speed scanning, the output of the image memory 41 is enabled during the current line scanning, and the output of the image memory 42 is enabled during the interpolation line scanning. In the subsequent selector 52, the enabled image memories 41 and 42 are selected as input signals, and output as a double-speed scanning video signal in which the current line video and the interpolated line video are combined. At this time, the selection input signals of the selectors 46 and 48 always select the same signals from the control circuit 43 that have not been inverted.

"Two-screen display" The type of reference video (display video on the main screen) serving as a reference for two-screen display and display synchronization by the user and the video (display video on the sub-screen side) displayed simultaneously with the reference video signal When the type is specified, A / D
The corresponding main screen video signal is input from the converter 1, is subjected to band limitation according to the reduction ratio by the low-pass filter 2, and is then written to the image memory 3. A / D converter 4
And the corresponding sub-screen video signal is input and written to the image memory 5. The image memory 5 writes the video signal to the memory using the synchronization of the sub-screen video, and reads the video signal from the memory using the synchronization of the main screen video. Synchronous conversion processing for synchronizing with the main screen video is performed in the frequency cycle (frame synchronization processing). At this time, if the frame frequency is different between the main screen image and the sub-screen image, the phase of the vertical synchronization signal between the main screen image and the sub-screen image is detected, and the display sub-screen image is shifted by one or more fields. The control circuit 9 controls the write / read control signal of the image memory 5 so that the phase difference does not occur (overtaking / overtaking control). Image memory 5 synchronized with main screen image by image memory 5
Is output to the image memory 7 after the band is limited by the low-pass filter 6 in accordance with the reduction ratio. Thereafter, the control circuit 9 controls the display phase of the main screen video and the sub-screen video, and the display boundary line phase, by controlling the video signal read-out phase of the image memories 3 and 7 and the input selection control signal of the selector 8 to form a two-screen composite video. To achieve. Further, the output video signal of the selector 8 is thereafter input to the scanning video arithmetic circuit 20, and an interpolated line scanning video signal that has been subjected to scan conversion that is motion-adapted to the current line scanning video signal is calculated. The detailed description is the same as that for one screen, and thus will not be repeated. The current line scanning video signal and the interpolated line scanning video signal output from the scanning video arithmetic circuit 20 are input to the double speed scanning conversion circuit 40, and double the scanning speed using an image memory as in the case of one screen. Thereafter, the above two signals are switched and synthesized by the internal selector at every double-speed scanning, thereby generating a double-speed scanning video signal. More specifically, referring to FIG. 3, both the current line scanning video signal and the interpolated line scanning video signal output from the scanning video arithmetic circuit 20 are written to the image memories 41 and 42 in one scanning cycle. Reading is performed at twice the speed and cycle of writing. Further, output enable control is performed for reading, and the control signal has a cycle equal to the write reset signal to the image memories 41 and 42 and a duty of 5
A change point of 0% becomes a signal equal to the read reset signal. The polarity of the enable signal is inverted in the image memories 41 and 42. That is, in the double-speed scanning, the output of the image memory 41 is enabled during the current line scanning, and the output of the image memory 42 is enabled during the interpolation line scanning. In the subsequent selector 52, the enabled image memories 41 and 42 are selected as input signals, and output as a double-speed scanning video signal in which the current line video and the interpolated line video are combined. Here, the input selection control of the selectors 46 and 48 is performed by the scanning method determination circuit 61.
To determine the scanning mode of the main screen video input and the sub-screen video signal, and perform the determination based on the obtained results. When the NTSC interlaced scanning signal is input for both the main screen video input and the sub-screen video signal input, the selection input signals of the selectors 46 and 48 are the same signals from the control circuit 43 whose polarity is not inverted as in the case of one screen. , Always choose. At this time, the video signal of each part is the same as that shown in FIG. 10 of the conventional example. If the main screen video input is a non-standard signal, for example, a frame of 262 progressive scanning signals output from a certain game, and the sub-screen video signal input is an NTSC interlaced scanning signal, the scanning method discrimination is performed. The circuit 61 discriminates this and switches the input selection signals of the selectors 48 and 49 in frame units of the main screen image input. When the sub-screen image displays an odd field image, the selector 46
And a control circuit 43 which does not invert the polarity as input signals of 48
Is selected as it is, and when an even-field image is displayed, control is performed such that a signal obtained by inverting the polarity of the control signal from the control circuit 43 as an input signal to the selectors 46 and 48 is selected. FIG. 4 shows the video signal of each part at this time.

(Embodiment 2) FIGS. 1, 2 and 5 show block diagrams of an embodiment of the present invention. The description of FIGS. 1 and 2 is the same as that of the first embodiment, and will not be repeated. In FIG. 5, reference numeral 41 denotes an image memory for converting the scan of the current line scan image output from the scan image arithmetic circuit 20 having the input image information as it is to a double speed;
42 is an image memory for converting the scanning of the output interpolated line scanning video from the circuit calculated by the calculation in the scanning video arithmetic circuit 20 to double speed, 43 is a write reset signal which is a control signal for the image memories 41 and 42, A control circuit for generating a read reset signal and a read enable signal,
44, an inverting circuit for inverting the polarity of the read enable signal to the image memory 41 and inputting it to the read enable signal input of the image memory 42; 45, an inverting circuit for inverting the polarity of the memory read enable signal from the control circuit 43;
46 is a selector for selecting and outputting either the input signal or the output signal of the inverting circuit 45; 47 is an inverting circuit for inverting the polarity of the output selection control signal of the image memories 41 and 42 from the control circuit 43; A selector 47 selects and outputs one of an input signal and an output signal. 49 to 51 perform a logical OR operation of the control signal output from the control circuit 43 and the scanning method determination result output from the scanning method determination circuit 61. The OR gate 52 is a selector for selecting and outputting the output video signals of the image memories 41 and 42 according to the input selection control signal output from the selector 48. The operation of the television receiver configured as described above will be described below.

When the NTSC interlaced scanning signal is input for both the main screen video input and the sub-screen video signal input for the one-screen display and the two-screen display, the same processing as in the first embodiment is performed. A description will be given of a case where the main screen video input is a non-standard signal, for example, a 262 progressive scanning signal per frame output from a certain game, and the sub-screen video signal input is an NTSC interlaced scanning signal. . Further, since the processing up to the output of the scanning video arithmetic circuit 20 is the same, the operation of the double-speed scanning conversion circuit 40 will be described with reference to FIG. Both the signal and the interpolated line scanning video signal are written to the image memories 41 and 42 in one scanning cycle, respectively. Reading is performed at twice the speed and cycle of writing. Further, for read, output enable control is performed, and the control signal is a signal whose cycle is equal to the write reset signal to the image memories 41 and 42 and whose change point at a duty of 50% is equal to the read reset signal. The polarity of the enable signal is inverted in the image memories 41 and 42. That is, in the double-speed scanning, the output of the image memory 41 is enabled during the current line scanning, and the output of the image memory 42 is enabled during the interpolation line scanning. In the subsequent selector 52, the enabled image memories 41 and 42 are selected as input signals, and output as a double-speed scanning video signal in which the current line video and the interpolated line video are combined. Here, the input selection control of the selectors 46 and 48 is performed by the scanning method discriminating circuit 61 by judging the scanning method of the main screen image input and the sub-screen image signal, and based on the obtained result. When the NTSC interlaced scanning signal is input for both the main screen video input and the sub-screen video signal input, the selection input signals of the selectors 46 and 48 are the same signals from the control circuit 43 whose polarity is not inverted as in the case of one screen. , Always choose. At this time, the video signal of each part is the same as that shown in FIG. 10 of the conventional example. If the main screen video input is a non-standard signal, for example, a 262 sequential scanning signal output from a certain game, and the sub-screen video signal input is an NTSC interlaced scanning signal, the scanning method is determined. The circuit 61 determines this, and switches the input selection signals of the selectors 48 and 49 for each frame of the main screen video input. When the sub-screen video displays an odd field video, the polarity is used as the input signal of the selectors 46 and 48. A signal as it is from the control circuit 43 which is not inverted is selected, and when an even field image is displayed, control is performed such that a signal obtained by inverting the polarity of the control signal from the control circuit 43 is selected as an input signal of the selectors 46 and 48. .
Further, in the reading of the image memories 41 and 42, the interlaced scanning is performed as a combination of the control signal from the control circuit 43 which becomes the high level when reading the non-standard progressive scanning video area and the input of the main screen video and the sub-screen video signal of the two screen display. When a non-standard progressively scanned image area is read out, a logical sum operation of the control signal from the scanning method discriminating circuit 61 which becomes a high level at the time of the input where the sequential scanning is mixed is performed by using the logical sum gates 49 to 51. The output of the image memory 41 is always selected as the input selection signal of the selector 52, and the double-speed reading display of the current line video is performed. FIG. 6 shows the video signal of each part at this time.

(Embodiment 3) FIGS. 1, 3 and 7 are block diagrams showing an embodiment of the present invention. The description of FIGS. 1 and 3 is the same as that of (Embodiment 1), and thus the description is omitted. In FIG. 7, reference numeral 31 designates a video signal synthesized by the selector 8 as an input, performs bus width conversion by serial-parallel conversion, writes it into the video RAM, and delays the signal for an arbitrary period into a parallel signal.
A wide bus width image memory for performing bus width conversion again by serial conversion and a memory I / F circuit 32 for interfacing video signals, a large 32 having a high transfer rate by having a bus width wider than the video signals. The capacity image memory 33 receives the signal obtained by delaying the video signal synthesized by the selector 8 through the memory i / f circuit 31 for an arbitrary period as input and performs scan conversion by field interpolation and field interpolation to perform the current line. An interpolation operation circuit 34 for outputting the scanned image and the interpolated line scan image is a control circuit for generating control signals for the memory i / f circuit 31, the image memory 32 and the interpolation operation circuit 33. The operation of the television receiver configured as described above will be described below.

[Single-Screen Display] When a single-screen display and a type of display image are designated by a user, a corresponding video signal is input from the A / D converter 1 and written into the image memory 3. The selector 8 always selects and outputs the video signal from the image memory 3. The output video signal of the selector 8 is thereafter input to the scanning video arithmetic circuit 20. In the case of NTSC video, an interpolation line scanning video signal that has been subjected to scan conversion that is motion-adapted to the current line scanning video signal is calculated.
High vertical resolution signals such as TV and 525P video are output without processing. Referring to FIG.
When the input video is an NTSC video, the memory i / f circuit 3
1 and a signal having no delay with respect to the output video signal of the selector 8 by the image memory 32, a signal delayed by one scanning period, 26
A signal delayed by three scanning periods and a signal delayed by 526 scanning periods are generated. Motion adaptive scan conversion is performed using the above four signals, and a current line scan image and an interpolated line scan image are output. Since the detailed operation is the same as in the first embodiment,
Description is omitted. Also, a signal with a high vertical resolution such as an HDTV or 525P video is output from the current line scan video without performing the arithmetic processing as described above. The current line scan video signal and the interpolated line scan video signal output from the scan video arithmetic circuit 20 are input to the double speed scan conversion circuit 40. In the case of NTSC video, the scan is double-speed converted using an image memory. The detailed operation is the same as in the first embodiment. A signal with a high vertical resolution, such as an HDTV or 525P video, is input as a current line scan video, subjected to only delay processing in the image memory 41, and the selector 52 always selects and outputs the input of the image memory 41.

"Two-screen display" The type of reference video (display video on the main screen) serving as a reference for two-screen display and display synchronization by the user and the video (display video on the sub-screen) displayed simultaneously with the reference video signal When the type is specified, A / D
The corresponding main screen video signal is input from the converter 1, is subjected to band limitation according to the reduction ratio by the low-pass filter 2, and is then written to the image memory 3. A / D converter 4
And the corresponding sub-screen video signal is input and written to the image memory 5. The image memory 5 writes the video signal to the memory using the synchronization of the sub-screen video, and reads the video signal from the memory using the synchronization of the main screen video. Synchronous conversion processing for synchronizing with the main screen video is performed in the frequency cycle (frame synchronization processing). At this time, if the frame frequency is different between the main screen image and the sub-screen image, the phase of the vertical synchronization signal between the main screen image and the sub-screen image is detected, and the display sub-screen image is shifted by one or more fields. The control circuit 9 controls the write / read control signal of the image memory 5 so that the phase difference does not occur (overtaking / overtaking control). Image memory 5 synchronized with main screen image by image memory 5
Is output to the image memory 7 after the band is limited by the low-pass filter 6 in accordance with the reduction ratio. Thereafter, the control circuit 9 controls the display phase of the main screen video and the sub-screen video, and the display boundary line phase, by controlling the video signal read-out phase of the image memories 3 and 7 and the input selection control signal of the selector 8 to form a two-screen composite video. To achieve. Further, the output video signal of the selector 8 is thereafter input to the scanning video arithmetic circuit 20 and a sequential scan conversion process is performed. When the display video on the main screen side is NTSC, the subsequent processing is performed when one screen is displayed. Since the processing is the same as described above, the description is omitted.
The display video on the main screen is a signal with a high vertical resolution such as HDTV and 525P video, and the display video on the sub-screen is NTS.
In the case of C, the display image on the main screen side does not perform the interpolation operation processing, and the display image on the sub screen side performs the field interpolation operation according to the number of scanning lines of the main screen image, and performs the current line scan image. Output. The processing in the double-speed scanning conversion circuit 40 at the subsequent stage is the same as that for one screen.

(Embodiment 4) FIGS. 8, 3 and 7 are block diagrams showing an embodiment of the present invention. In FIG. 8, reference numeral 62 denotes a video start line detection circuit that detects video information of each line of the display video on the main screen side and determines a video start scan line. The other processing blocks perform the same operation as in the first embodiment, and thus the description is omitted. 3 and FIG. 7 perform the same operation as in the third embodiment, and a description thereof will be omitted. The operation of the television receiver configured as described above will be described below.

The operation is the same as that of the third embodiment when one screen is displayed. "Dual-screen display" The user specifies the type of reference video (displayed video on the main screen) and the type of video displayed simultaneously with the reference video signal (displayed video on the sub-screen) as a reference for two-screen display and display synchronization. Then, the corresponding main screen video signal is input from the A / D converter 1, subjected to band limitation according to the reduction ratio by the low-pass filter 2, and then written into the image memory 3. Further, the corresponding sub-screen video signal is input from the A / D converter 4 and written into the image memory 5. The image memory 5 writes the video signal to the memory using the synchronization of the sub-screen video, and reads the video signal from the memory using the synchronization of the main screen video. Synchronous conversion processing for synchronizing with the main screen video is performed in the frequency cycle (frame synchronization processing). At this time, if the frame frequency is different between the main screen image and the sub-screen image, the phase of the vertical synchronization signal between the main screen image and the sub-screen image is detected, and the display sub-screen image is shifted by one or more fields. The control circuit 9 controls the write / read control signal of the image memory 5 so that the phase difference does not occur (overtaking / overtaking control). The output sub-screen image of the image memory 5 synchronized with the main screen image by the image memory 5 is subjected to band limitation according to the reduction ratio by the low-pass filter 6, and then written to the image memory 7. Thereafter, the control circuit 9 controls the display phase of the main screen video and the sub-screen video, and the display boundary line phase, by controlling the video signal read-out phase of the image memories 3 and 7 and the input selection control signal of the selector 8 to form a two-screen composite video. To achieve. Further, the output video signal of the selector 8 is thereafter input to the scanning video arithmetic circuit 20 and a sequential scan conversion process is performed. When the display video on the main screen side is NTSC, the subsequent processing is performed when one screen is displayed. Since the processing is the same as described above, the description is omitted. When the display image on the main screen is a signal with a high vertical resolution such as an HDTV or 525P image and the display image on the sub-screen is NTSC,
The display image on the main screen side does not perform the interpolation operation processing, and the display image on the sub-screen side performs the field interpolation operation according to the number of scanning lines of the main screen image, and is output from the current line scan image. The processing in the double-speed scanning conversion circuit 40 at the subsequent stage is the same as that for one screen. Here, the display image on the sub-screen side matches the number of scanning lines of the main screen image, and when performing the field interpolation operation, the vertical composite phase of the video signal of both images is determined by the output determination result of the scanning method determination circuit 61 and the video. Start line detection circuit 62
Is detected using the output detection result of For example, in the case of a 1125-line interlaced scan image, when the signals are of the same scanning method and different video start lines, such as the analog HDTV signal format and the digital HDTV signal format, the output detection result of the video start line detection circuit 62 is determined. The vertical synthesizing phase of the video signal of both the main and sub-images is determined using this. Particularly, it is possible to realize high-accuracy synthesis of the main and sub-images even when the system determination is difficult due to the deterioration of the system determination signal due to the recording and reproduction of a VTR or the like.

(Embodiment 5) FIGS. 9, 3 and 7 are block diagrams showing an embodiment of the present invention. In FIG. 9, reference numeral 63 denotes an effective video line number detection circuit that detects video information of each line of the display video on the main screen side and determines the number of effective video lines. The other processing blocks perform the same operations as in (Embodiment 4), and a description thereof will be omitted. 3 and FIG. 7 perform the same operation as in the third embodiment, and a description thereof will be omitted.

The operation of the television receiver configured as described above will be described below.

Regarding the operation, when displaying one screen, the same operation as in the third embodiment is performed. "Dual-screen display" The user specifies the type of reference video (displayed video on the main screen) and the type of video displayed simultaneously with the reference video signal (displayed video on the sub-screen) as a reference for two-screen display and display synchronization. Then, the corresponding main screen video signal is input from the A / D converter 1, subjected to band limitation according to the reduction ratio by the low-pass filter 2, and then written into the image memory 3. Further, the corresponding sub-screen video signal is input from the A / D converter 4 and written into the image memory 5. The image memory 5 writes the video signal to the memory using the synchronization of the sub-screen video, and reads the video signal from the memory using the synchronization of the main screen video. Synchronous conversion processing for synchronizing with the main screen video is performed in the frequency cycle (frame synchronization processing). At this time, if the frame frequency is different between the main screen image and the sub-screen image, the phase of the vertical synchronization signal between the main screen image and the sub-screen image is detected, and the display sub-screen image is shifted by one or more fields. The control circuit 9 controls the write / read control signal of the image memory 5 so that the phase difference does not occur (overtaking / overtaking control). The output sub-screen image of the image memory 5 synchronized with the main screen image by the image memory 5 is subjected to band limitation according to the reduction ratio by the low-pass filter 6, and then written to the image memory 7. Thereafter, the control circuit 9 controls the display phase of the main screen video and the sub-screen video, and the display boundary line phase, by controlling the video signal read-out phase of the image memories 3 and 7 and the input selection control signal of the selector 8 to form a two-screen composite video. To achieve. Further, the output video signal of the selector 8 is thereafter input to the scanning video arithmetic circuit 20 and a sequential scan conversion process is performed. When the display video on the main screen side is NTSC, the subsequent processing is performed when one screen is displayed. Since the processing is the same as described above, the description is omitted. When the display image on the main screen is a signal with a high vertical resolution such as an HDTV or 525P image and the display image on the sub-screen is NTSC,
The display image on the main screen side does not perform the interpolation operation processing, and the display image on the sub-screen side performs the field interpolation operation according to the number of scanning lines of the main screen image, and is output from the current line scan image. The processing in the double-speed scanning conversion circuit 40 at the subsequent stage is the same as that for one screen. Here, the display image on the sub-screen side is adjusted to the number of scanning lines of the main screen image, and when performing the field interpolation operation, the method of the field interpolation operation of the sub-screen video signal is determined by the effective image line number detection circuit 63. Determined using the output detection result. For example, for an interlaced scan image of 1125 lines, an analog HDTV signal format and a digital H
In the case of a signal having the same scanning method but different video start lines as in the DTV signal format, the method of field interpolation calculation of the sub-screen video signal is determined using the output detection result of the effective video line number detection circuit 63. . Particularly, it is possible to realize high-accuracy synthesis of the main and sub-images even when the system determination is difficult due to the deterioration of the system determination signal due to the recording and reproduction of a VTR or the like.

[0035]

As described above, according to the television receiver of the present invention, (1) In the invention of the first, second and third aspects, the scanning method determining circuit for detecting and determining the scanning method of the input video signal. In accordance with the scanning method discrimination result of the reference video signal, controls whether or not to perform processing for switching whether or not to delay the synthesized video signal before the double-speed scan conversion by one scanning period at the field frequency of the reference video signal, For a video whose scanning method is a progressive scanning method, by performing a process of switching the subsequent double-speed scanning conversion from the motion-adaptive progressive scanning conversion to the simple twice writing double-speed scanning conversion, for example, terrestrial broadcasting and a partial VTR In the case of blue screen, terrestrial broadcasting and game video, etc., when the interlaced scanning method and the sequential scanning method are mixed as the scanning method of the main screen image and the sub screen image, the images overlap in the vertical direction. It is possible to perform multi-screen display without causing image quality deterioration such as occurrence of image distortion.

(2) According to the fourth aspect of the present invention, the amount of delay of the input video signal by the memory is adaptively controlled in accordance with the result of the scanning mode determination of the scanning mode determining circuit for detecting and determining the scanning mode of the input video signal. In addition, by performing a process of switching between a video synthesizing method and a scan conversion method of each input video signal to be displayed on a multi-screen, it has been conventionally required as a pre-process at the time of multi-screen display of an image having a high video scanning frequency such as HDTV. Multi-screen display can be performed without performing signal format conversion to the pseudo NTSC system. For images having a high video scanning frequency, deterioration in image quality and resolution due to down conversion of the scanning rate is prevented, and high video scanning is performed. In a conventional configuration such as the NTSC system, which simultaneously displays images having frequencies, the down Makes it possible to produce a potential for further image quality improvement by up-conversion of even scan rate for a video is Bad not displayable, the high-quality image can be multi-screen display.

(3) According to the fifth and sixth aspects of the present invention, the video information of the input video signal is analyzed and the interlaced scanning input video is in the field, and the progressive scanning input video is in the frame. The phase of the video start scanning line and the vertical synchronizing signal and the number of effective video scanning lines are detected for the input video signal. According to the result, the readout phase of the video signal from the video reduction processing memory and the composite phase of the video are controlled. By switching the reduction magnification of the reduction processing memory,
Analyze the input video signal even if the number of scanning lines is the same but the effective phase of the image or the number of effective scanning lines are different,
The optimum multi-screen display can be automatically performed by calculating the display phase and the scan conversion method at the time of multi-screen display from the analysis result, and performing scan conversion and video synthesis.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a television receiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a scanning video calculation circuit in the television receiver according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a schematic configuration of a double-speed scanning conversion circuit in the television receiver according to the first embodiment of the present invention.

FIG. 4 is a signal waveform diagram of each part in the television receiver according to the first embodiment of the present invention.

FIG. 5 is a block diagram illustrating a schematic configuration of a double-speed scanning conversion circuit in the television receiver according to the second embodiment of the present invention.

FIG. 6 is a signal waveform diagram of each part in the television receiver according to the first embodiment of the present invention.

FIG. 7 is a block diagram showing a schematic configuration of a scanning video arithmetic circuit in a television receiver according to a third embodiment of the present invention.

FIG. 8 is a block diagram illustrating a schematic configuration of a television receiver according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram illustrating a schematic configuration of a television receiver according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing a schematic configuration of a conventional television receiver.

FIG. 11 is a block diagram showing a schematic configuration of a scanning video calculation circuit in a conventional television receiver.

FIG. 12 is a block diagram showing a schematic configuration of a double-speed scanning conversion circuit in a conventional television receiver.

FIG. 13 is a signal waveform diagram of each part in a conventional television receiver.

FIG. 14 is a signal waveform diagram of each part in a conventional television receiver.

[Explanation of symbols]

1, 4 A / D converter 2, 6 Low-pass filter 3, 5, 7, 21, 23, 24, 32, 41, 42 Image memory 8, 46, 48, 52 Selector 9, 27, 34, 43 Control circuit 20 Scanned video operation circuit 22 Adder 25 Motion detection circuit 26 MIX circuit 31 Memory i / f circuit 33 Interpolation operation circuit 40 Double speed scan conversion circuit 44, 45, 47 Inversion circuit 49, 50, 51 OR gate 61 Scanning method discrimination circuit 62 Video start line detection circuit 63 Effective video line number detection circuit 71 D / A converter

Claims (6)

[Claims] 1. A television receiver capable of simultaneously displaying two or more types of video signals on one display device, wherein a plurality of video signals are converted into a reference video signal by scanning conversion. When displaying simultaneously on the display device,
Detect the scanning method of each video signal to be displayed simultaneously,
According to the detection result, the synthesizing method and the scan conversion method at the time of video synthesis are switched, and a high quality multi-screen display is realized by performing optimal video synthesis and scan conversion according to the scanning method of the input video. Television receiver. 2. A television receiver capable of simultaneously displaying two or more types of video signals on one display device, a first memory for reducing a reference video signal, and a first memory for reducing the reference video signal. 2nd processing for synchronizing the video signals to be displayed simultaneously with the frame frequency cycle of the video
, A third memory for reducing a video signal displayed simultaneously with the reference video signal, a reference video signal reduced by the first memory, and the reference reduced by the third memory A selector for synthesizing a video signal and a video signal to be simultaneously displayed;
A control circuit for generating a control signal for the memory and a selection signal for the selector, a scanning method determination circuit for detecting and determining the scanning method of the reference video signal and the video signal to be simultaneously displayed, and a video signal synthesized by the selector Detects the amount of motion between frames of the same signal as input and calculates the interpolated line scanning video signal by interpolating the field when the amount of motion is small when the amount of motion is small, and delays the input image when the amount of motion is large. A scanning video calculation circuit for outputting a current line scanning video signal having the same phase as the interpolation line scanning video signal; and scanning of the current line scanning video signal and the interpolation line scanning video signal output from the scanning video calculation circuit by two.
A double-speed scanning conversion circuit for performing synthesis by switching and selecting both signals for each double-speed scanning after double-speed conversion, and the scanning method determining result of the reference video signal and the simultaneously displayed video signal in the scanning method determining circuit. A television receiver for controlling whether or not to perform a process of switching the scanning order of the current line scanning video signal and the interpolated line scanning video signal at the time of double speed scan conversion at the field frequency of the reference video signal according to . 3. A television receiver capable of simultaneously displaying two or more types of video signals on one display device, a first memory for reducing a reference video signal, and a first memory for reducing the reference video signal. 2nd processing for synchronizing the video signals to be displayed simultaneously with the frame frequency cycle of the video
, A third memory for reducing a video signal displayed simultaneously with the reference video signal, a reference video signal reduced by the first memory, and the reference reduced by the third memory A selector for synthesizing a video signal and a video signal to be simultaneously displayed;
A control circuit for generating a control signal for the memory and a selection signal for the selector, a scanning method determination circuit for detecting and determining the scanning method of the reference video signal and the video signal to be simultaneously displayed, and a video signal synthesized by the selector Detects the amount of motion between frames of the same signal as input and calculates the interpolated line scanning video signal by interpolating the field when the amount of motion is small when the amount of motion is small, and delays the input image when the amount of motion is large. A scanning video calculation circuit for outputting a current line scanning video signal having the same phase as the interpolation line scanning video signal; and scanning of the current line scanning video signal and the interpolation line scanning video signal output from the scanning video calculation circuit by two.
A double-speed scanning conversion circuit that performs synthesis by switching and selecting both signals after double-speed conversion, and according to the scanning method determination result of the reference video signal and the simultaneously displayed video signal in the scanning method determination circuit, A television receiver characterized by switching between motion adaptive progressive scan conversion and simple double writing double speed scan conversion as double speed scan conversion processing. 4. A television receiver capable of simultaneously displaying two or more types of video signals on one display device, a first memory for reducing a reference video signal, and a first memory for reducing the reference video signal. 2nd processing for synchronizing the video signals to be displayed simultaneously with the frame frequency cycle of the video
, A third memory for reducing a video signal to be displayed simultaneously with the reference video signal, a control circuit for generating control signals for the first to third memories, and a display for simultaneously displaying the reference video signal A scanning mode discriminating circuit for detecting and discriminating a scanning mode of a video signal; a video signal simultaneously displayed with the reference video signal reduced by the first memory and the reference video signal reduced by the third memory And a fourth memory for delaying the reference video signal and the video signal to be displayed simultaneously by the fourth memory using the output signal of the scanning mode discrimination circuit as a control signal and a video signal to be displayed simultaneously. A video synthesizing / scan converting circuit for performing a synthesizing process and a scan converting process, wherein the scanning method discriminating circuit scans the reference video signal and the video signal to be simultaneously displayed. The delay amount of the reference video signal and the video signal to be simultaneously displayed by the fourth memory are switched and controlled according to the determination result, and the video synthesizing method and the scan conversion method of the video signal to be simultaneously displayed with the reference video signal. A television receiver. 5. A television receiver capable of simultaneously displaying two or more types of video signals on one display device, wherein a first memory for reducing a reference video signal is processed, and 2nd processing for synchronizing the video signals to be displayed simultaneously with the frame frequency cycle of the video
, A third memory for reducing a video signal displayed simultaneously with the reference video signal, a reference video signal reduced by the first memory, and the reference reduced by the third memory A selector for synthesizing a video signal and a video signal to be simultaneously displayed;
A control circuit for generating a control signal of the memory and a selection signal of the selector, and analyzing the video information of the reference video signal and the video signal to be simultaneously displayed, and sequentially scanning the input video of the interlaced scanning method in the field. Video input line detection for detecting the phase of a video start scanning line and a vertical synchronizing signal in a frame with respect to the reference video signal and the video signal to be simultaneously displayed, and outputting the detection result to the control circuit. A video from the first and third memories in accordance with a phase detection result between the reference video signal and a video start scanning line of a video signal to be simultaneously displayed and a vertical synchronization signal in the video start line detection circuit. A television receiver which controls a signal reading phase and a switching phase of the selector. 6. A television receiver capable of simultaneously displaying two or more types of video signals on one display device, a first memory for reducing a reference video signal, and a first memory for reducing the reference video signal. 2nd processing for synchronizing the video signals to be displayed simultaneously with the frame frequency cycle of the video
, A third memory for reducing a video signal displayed simultaneously with the reference video signal, a reference video signal reduced by the first memory, and the reference reduced by the third memory A selector for synthesizing a video signal and a video signal to be simultaneously displayed;
A control circuit for generating a control signal of the memory and a selection signal of the selector, and analyzing the video information of the reference video signal and the video signal to be simultaneously displayed, and sequentially scanning the input video of the interlaced scanning method in the field. For the input image of the system, an effective image scanning line number detecting circuit for detecting the number of effective image scanning lines in a frame with respect to the reference image signal and the simultaneously displayed image signal and outputting the detection result to the control circuit is provided. Reducing the reduction ratio of the reduction processing performed in the third memory according to the result of detecting the number of effective video scanning lines of the reference video signal and the video signal to be simultaneously displayed in the effective video scanning line number detection circuit. Television receiver.