JPH08317344A - Display device - Google Patents

Abstract

PURPOSE: To provide the inexpensive display device with an integrated scanning speed changing circuit for enabling image display with fidelity to an inputted video signal without picture quality degradation caused by the interpolation of scanning lines. CONSTITUTION: A scanning speed changing circuit 4 reads and outputs video signals for one scanning line during the 1/2 horizontal scanning period of inputting at the double speed of inputting concerning primary color video signals inputted and stored in line memories, stops reading them during the remaining 1/2 horizontal scanning period and further outputs the input horizontal synchronizing signals after converting their frequency to a double frequency. Based on the synchronizing signals outputted from the scanning speed changing circuit 4, a deflection circuit 6 performs the deflection control of a CRT display device 7.

Description

Detailed Description of the Invention

[0001]

The present invention relates to NTSC, PAL, SE
The present invention also relates to a display device having a scanning speed conversion function for a high-definition television signal or an interlaced signal such as an image information signal in a personal computer.

[0002]

2. Description of the Related Art In recent years, along with the development of multimedia, there is an increasing need for displaying a natural image of NTSC system taken by a home VTR or a video camera on a display device for displaying an image of a personal computer or a workstation. .

However, the horizontal scanning frequency of the video signal of a personal computer or the like is almost 24 kHz or more, whereas the horizontal scanning frequency of the NTSC system is 15.75.
As low as kHz. 15.75 kHz on the display device side
In order to cope with the horizontal scanning frequency, the load on the horizontal deflection circuit is increased, and the image quality is deteriorated such as an increase in screen distortion. Therefore, a double speed conversion process for converting the interlaced signal into a non-interlaced signal to double the horizontal scanning frequency has been studied.

The conversion into a non-interlaced signal is roughly divided into two methods. One is an intra-field scanning line interpolation method that creates an interpolated scanning line by using scanning lines in the same field, and the other is an interpolated scanning line that is created by using scanning lines between preceding and following fields. Inter-field scanning line interpolation method.

Of these two non-interlaced conversion methods, if the inter-field scanning line interpolation method is applied to the moving part of the image, two fields that differ in time are combined, resulting in a double image. appear. Therefore, for the moving part of the image, it is necessary to create an interpolated scan line by the intra-field scan line interpolation method.

Further, in the intra-field scanning line interpolation method,
A line memory that can store at least one scanning line video signal is provided, and an interlace system video signal is written to this line memory one scanning line at a time, and the same scanning line is read twice at twice the writing speed. There are a reading interpolation method and a calculation interpolation method that creates an interpolation scanning line by a calculation considering weighting of upper and lower scanning lines.

However, in the same scanning line double reading interpolation method, the resolution in the vertical direction is lowered, and the image quality may be deteriorated. Therefore, as disclosed in Japanese Patent Laid-Open No. 3-113977, the vertical deflection circuit on the receiver side is modified so that the same scanning line read twice is displayed at the same position on the cathode ray tube. It has been proposed to suppress degradation of directional resolution. The arithmetic interpolation method is disclosed in Japanese Patent Laid-Open No. 4-157886.

Further, as disclosed in Japanese Patent Laid-Open No. 63-63283, the horizontal scanning frequency is doubled by doubling the field frequency, and the vertical deflection circuit is devised to scan the odd field scanning positions. And an example of suppressing the confusion of the scanning positions of the even fields.

[0009]

In such a conventional apparatus, the method of scanning the same scanning line twice every time requires a means for switching the output signal of the vertical deflection circuit on the side of the receiver. The circuit has a very special configuration, which increases the cost.

Further, the arithmetic interpolation method cannot avoid a large increase in cost due to the addition of arithmetic circuits. Further, since the scanning line created by the calculation is a scanning line that does not exist in the original video signal, the sharpness of the image may be deteriorated and the image quality may be deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device which is inexpensive, has little deterioration in image quality due to scanning line interpolation, and has a scanning speed conversion function for performing a display faithful to an input video signal.

[0012]

In order to solve the problems of the prior art, the present invention stores at least one scanning line portion of an input interlaced video signal in a memory and stores it in this memory. A display device provided with a scanning speed conversion means for reading the generated video signal at a speed n times the input speed and outputting a video signal at a scanning speed n times, and a display means for displaying the video signal with the converted scanning speed. In the scanning speed conversion means, a video signal for one scanning line is read from the memory during the 1 / n horizontal scanning period of writing at a speed n times the speed of writing the video signal to the memory, and the remaining (n-1) ) / N horizontal scanning period, reading is stopped, and in the next field, during the horizontal scanning period in which reading was stopped in the previous field, 1 / n horizontal scanning is performed from the memory at a speed of n times. Other horizontal scanning period is read out video signals of one scanning line period is characterized in that a memory control signal generator means for stopping the reading.

Alternatively, input means for inputting the first video signal of the interlace system, input means for inputting the second video signal of the non-interlace system, and scanning speed for converting the scanning speed of the first video signal The conversion device includes a conversion device, a switching device that switches between the first video signal and the second video signal that have undergone the scanning speed conversion process, and selectively outputs the video signal, and a display device that displays the video signal output from the switching device. In the display device, the scanning speed conversion means stores a memory for storing an input video signal of at least one scanning line, and a 1 / n horizontal scanning period of writing at a speed n times the speed of writing the video signal to the memory. Then, the video signal for one scanning line is read out from the memory, the reading is stopped for the remaining (n-1) / n horizontal scanning period, and the reading is stopped in the next field. A memory control signal for reading a video signal for one scanning line from the memory at a speed n times higher than that of one scanning line during the horizontal scanning period during which the reading is stopped during the horizontal scanning period and for stopping the reading during another horizontal scanning period. It is characterized in that a generating means is provided. Alternatively, an A / D conversion circuit that converts an input interlaced video signal into a digital signal, a field memory that stores at least one field of video signal output from the A / D conversion circuit, and an input video A dot clock generation circuit that multiplies an input horizontal synchronizing signal of a signal to generate a dot clock, a write control circuit that controls writing of the field memory, a read control circuit that controls reading of the field memory, and the dot clock An output synchronizing signal generating circuit that divides the dot clock generated by the generating circuit to generate horizontal and vertical synchronizing signals of the output, and increases the horizontal scanning frequency by n times by multiplying the number of fields by n times. In a display device equipped with a scanning speed converter, first read from said memory Wherein the video signal of the even field provided read delay circuit for delaying the read start signal from the read control circuit so that the delay of one horizontal scanning period.

Alternatively, an A / D conversion circuit for converting the input interlaced video signal into a digital signal,
A field memory for storing a video signal for at least one field output from the A / D conversion circuit; a dot clock generation circuit for multiplying a horizontal synchronizing signal of the input video signal to generate a dot clock; A write control circuit that controls writing to the memory, a read control circuit that controls reading from the field memory, and the dot clock generated by the dot clock generation circuit are divided to generate horizontal and vertical synchronization signals of output. In the display device having a scanning speed conversion device for increasing the horizontal scanning frequency by n times by multiplying the number of fields by n times, the output video signal of the same continuous field is scanned in the same direction. Shift the output vertical sync signal so that it is displayed at the line position. The is characterized in that provided.

Alternatively, in a display device equipped with a scanning speed conversion circuit for increasing the horizontal scanning frequency by n times by increasing the field frequency of the input interlace type video signal by n times, the scanning speed conversion circuit is inputted with the input signal. A / D conversion circuit for converting the converted analog video signal into a digital signal, a memory for storing at least one field of the video signal output from the A / D conversion circuit, and an analog video signal read from this memory A D / A conversion circuit for converting to a video signal and outputting the same, a dot clock generating circuit for generating a dot clock by multiplying the horizontal synchronizing signal of the input video signal, and a dot clock generated by this dot clock generating circuit. Write control of the memory from the input horizontal sync signal and vertical sync signal of the input video signal A write control circuit for generating a signal, and an output synchronizing signal generating circuit for counting the dot clock generated by the dot clock generating circuit and generating and outputting an output horizontal synchronizing signal and a vertical synchronizing signal having a frequency n times as high as the input frequency. A field discriminating circuit which discriminates an odd field or an even field from the horizontal synchronizing signal and the vertical synchronizing signal of the input video signal and outputs a field discriminating signal; and the output synchronizing signal generating circuit based on the field discriminating signal. An output vertical synchronizing signal shift circuit that shifts and outputs the vertical synchronizing signal output from the dot clock generating circuit by the dot clock generating circuit, and a dot clock generated by the dot clock generating circuit and the output synchronizing signal generating circuit. Output from the output horizontal sync signal and the output vertical sync signal shift circuit Characterized in that a read control circuit for controlling reading from the memory based on an output vertical synchronizing signal and said field discrimination signal.

[0016]

Since the video signal is read from the memory at a speed n times faster than the writing speed, the scanning speed of the input video signal is doubled. Moreover, in the next field, by performing the reading during the period in which the reading of the memory is stopped in the previous field, it is possible to perform the video display so as to interpolate the period in which the reading is stopped for each field.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a display device according to the first embodiment of the present invention, and in particular, N
It is an example of an apparatus for receiving a TSC television signal and doubling the horizontal scanning frequency for display.

In FIG. 1, 1 is an NTSC signal source for outputting a composite video signal, 2 is a red, green and blue primary color image obtained by subjecting the input composite video signal to signal processing such as DC reproduction and Y / C separation. A video signal processing circuit for converting and outputting a signal, 3 is a sync separation circuit for extracting and outputting a horizontal synchronizing signal and a vertical synchronizing signal from an input composite video signal, 4 is a scanning speed converting circuit, 5 is a scanning speed converting A video output circuit that amplifies the processed video signal to drive the CRT display device 7, and a deflection circuit 6 that controls deflection of the CRT display device 7 in accordance with a synchronization signal output from the scanning speed conversion circuit 4.

Next, the structure of the scanning speed conversion circuit 4 will be described in detail with reference to FIG.

In FIG. 2, reference numeral 41 is a video signal input terminal for inputting red, green and blue primary color video signals, and 42 is an A / D for converting the primary color video signal input to the video signal input terminal 41 into a digital video signal. A conversion circuit, 43 is a line memory for storing a digital video signal of one scanning line output from the A / D conversion circuit 42, and 44 is a digital video signal read from the line memory 43 into an analog video signal. D / A conversion circuit, 45 is an input terminal for a video signal subjected to scanning speed conversion processing, 46 is a horizontal synchronization signal input terminal, and 47 is a dot obtained by multiplying the horizontal synchronization signal input from the horizontal synchronization signal input terminal 46. It is a dot clock generation circuit that generates a clock. In this embodiment, the PLL
An example will be described in which a (Phase Locked Loop) circuit is used to multiply a horizontal sync signal of 15.75 KHz by 1820 times to generate a dot clock of 28.6 MHz.

Reference numeral 413 is an input terminal for a vertical synchronizing signal, and 48 is an output horizontal for dividing the dot clock generated by the dot clock generating circuit 47 to generate a horizontal synchronizing signal having a frequency twice that of the input horizontal synchronizing signal. Sync signal generator, 4
Reference numeral 9 generates a sampling clock for the A / D conversion circuit 42 and a write control signal for the line memory 43 based on the horizontal synchronizing signal input from the horizontal synchronizing signal input terminal 46 and the dot clock generated by the dot clock generating circuit 47. The write control circuit 410 is D based on the horizontal synchronizing signal output from the output horizontal synchronizing signal generating circuit 48 and the dot clock generated by the dot clock generating circuit 47.
This is a read control circuit that generates a clock for the A / A conversion circuit 44 and a read control signal for the line memory 43.

It should be noted that the video signal input terminal 41, the A / D conversion circuit 42, the line memory 43, the D / A conversion circuit 44, and the video signal output terminal 45 are illustrated only for one system in order to simplify the description. Actually, there is one system for each color of red, green and blue.

FIG. 3 is a conceptual diagram showing the timing relationship between the input video signal and the output video signal of the line memory 43 in this embodiment. (1) is a vertical synchronizing signal of the input video signal, and (2) and (3) are input horizontal synchronizing signals of the odd field and the even field. (4) and (5) are the input data timings of the odd and even fields, and O1, O2, and O3 are the input timings of the scanning line data of the first, second, and third lines in the odd fields, respectively. E0, E1, E2, E3 are input timings of the data of the 0th, 1st, 2nd and 3rd scanning lines in the even field. (6) is the output horizontal sync signal,
(7) and (8) are read enable signals of the line memory 43 for the odd field and the even field, and (9),
(10) is a video signal read from the line memory 43 of the odd field and the even field.

FIG. 4 is a schematic diagram showing the scanning line position of the primary color video signal input to the video signal input terminal 41. Since this embodiment is an example of a device for converting the scanning line velocity of an NTSC video signal which is an interlaced signal, the scanning line positions of odd fields are shown in (a) and the scanning lines positions of even fields are shown in (b). As described above, the fields are arranged so as to be interpolated with each other.

Next, the operation of the scanning speed conversion circuit 4 will be described with reference to FIGS. In FIG. 2, the dot clock generation circuit 47 is a horizontal synchronization signal input terminal 46.
The horizontal synchronizing signal of 15.75 KHz input to 182
By multiplying by 0, a 28.6 MHz dot clock is generated and supplied to the write control circuit 49, the read control circuit 410, and the output horizontal synchronization signal generation circuit 48.

The write control circuit 49 divides the 28.6 MHz dot clock input from the dot clock generation circuit 47 by two to generate a 14.3 MHz clock, and the A / D conversion circuit 42 receives the sampling clock. And the input horizontal sync signal and 1
A control signal for the line memory 43 is generated from a clock of 4.3 MHz and supplied to the line memory 43.

The A / D conversion circuit 42 writes the primary color video signal input to the video signal input terminal 41 into a write control circuit 49.
Is converted into a digital signal at the timing of the rising edge of the sampling clock input from the line memory 4
Supply 3 At this time, since the input primary color video signal is an interlace signal, the timing of the input signal of the line memory 43 is, as shown in (4) and (5) of FIG. It will be just shifted.

The output horizontal synchronizing signal generating circuit 48 divides the 28.6 MHz dot clock input from the dot clock generating circuit 47 and generates an output horizontal synchronizing signal of 31.5 KHz, which is horizontally synchronized with the read control circuit 410. It is supplied to the signal output terminal 411. Read control circuit 41
0 is 2 input from the dot clock generation circuit 47.
The 8.6 MHz dot clock is subjected to phase adjustment processing and supplied to the D / A conversion circuit 44, and further, based on the 28.6 MHz dot clock and the 31.5 KHz output horizontal synchronizing signal, a read control signal of the line memory 43. Is generated and supplied to the line memory 43. Here, as the read enable signal of the line memory 43, in the case of an odd field, as shown in (7) of FIG. 3, a signal that switches between “H” and “L” is generated for each cycle of the output horizontal synchronizing signal. On the contrary, in the case of the even field, as opposed to the odd field, as shown in (8) of FIG. 3, the line memory 4 is switched to “L” and “H” at each cycle of the output horizontal synchronizing signal.
The read enable signal of 3 is generated to generate the line memory 4
Supply 3

By controlling the reading of the line memory 43 as described above, the line memory 43 becomes active when the enable signal is at "L" level, and the reading becomes possible. Then, as shown in (9) of FIG. 3, the line memory 43 stops reading the video signal during one horizontal scanning period of the output horizontal synchronizing signal at the start of the field, and then during the next one horizontal scanning period. To read. This operation is repeated on the subsequent lines.

In the case of the even field, conversely to the above, as shown in (10) of FIG. 3, the video signal is read during the period in which the reading is stopped in the odd field. That is, the video signal is read from the line memory 43 so as to interpolate the video signals in the period in which the reading is stopped for each field.

The D / A conversion circuit 44 is composed of (9),
The video signal read from the line memory 43 at the timing shown in (10) is converted to an analog video signal at the rising timing of the 28.6 MHz clock input from the read control circuit 410 and output to the video signal output terminal 45. .

The video output circuit 5 shown in FIG. 1 amplifies the video signal after scanning speed conversion outputted from the video signal output terminal 45 and supplies it to the CRT display device 7. The deflection circuit 6 also controls the deflection of the CRT display device 7 based on the synchronization signals output to the horizontal synchronization signal output terminal 411 and the vertical synchronization signal output terminal 415.

FIG. 5 is a schematic diagram showing the scanning line position on the CRT display device 7 when the scanning speed conversion process is performed on the video signal input from the NTSC signal source 1 as described above. A) is a case where an output video signal of an odd field is displayed, and FIG. Figure 5
In (a) and (b), a solid line is an effective scanning line on which a video signal is displayed, and a dotted line is an invalid scanning line that is not actually displayed because the video signal is not read from the line memory 43. The arrangement of the effective scanning lines shown in FIGS. 5A and 5B is ½ horizontal as a whole as compared with the arrangement of the scanning lines of the input video signal shown in FIGS. 4A and 4B. Although the scanning cycle is shifted, the arrangement of scanning lines and the interval between scanning lines are completely the same. Therefore, it is possible to display an image faithful to the input video signal without deterioration of resolution.

In this embodiment, an example in which the horizontal scanning frequency is converted to double has been described, but it is not limited to double, and reading is performed at a speed n times (n is a natural number) writing to the line memory 43. The display according to the present invention is obtained even when the horizontal scanning frequency is converted to n times by setting only one effective scanning line and the remaining (n-1) scanning lines as invalid scanning lines. The scanning speed conversion circuit of the device can deal with this.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 6 is a block diagram showing the configuration of the scanning speed conversion circuit 4 of the display device according to the second embodiment of the present invention. The same circuit means as those of the scanning speed conversion circuit 4 in the first embodiment shown in FIG. 2 are designated by the same reference numerals, and a duplicate description will be omitted.

The scanning speed conversion circuit 4 of the first embodiment described above is an example of a device which doubles the number of lines and doubles the horizontal scanning frequency by interpolating invalid scanning lines with a constant vertical scanning frequency. In contrast, the second embodiment is
This is an example of a device that doubles the number of lines by invalid scanning line interpolation and doubles the vertical scanning frequency to double the horizontal scanning frequency. Therefore, the point that the field memory 412 that stores the video signal for one field is used and the point that the output vertical synchronizing signal generation circuit 414 that generates the output vertical synchronizing signal having a frequency twice the input vertical synchronizing signal is provided are described above. Different from the first embodiment described above. The operation will be described below.

The dot clock generating circuit 47 receives the horizontal synchronizing signal 3640 from the horizontal synchronizing signal input terminal 46.
The dot clock of 57.2 MHz is generated by multiplying by two, and the write control circuit 49, the read control circuit 410,
The output horizontal synchronizing signal generating circuit 48 is supplied. The write control circuit 49 divides the inputted 57.2 MHz dot clock by 4 to generate a 14.3 MHz clock,
The sampling clock is supplied to the A / D conversion circuit 42.

The output horizontal synchronizing signal generating circuit 48 divides the input 57.2 MHz dot clock to generate an output horizontal synchronizing signal having a frequency four times as high as the input horizontal synchronizing signal. The output vertical sync signal generation circuit 414 divides the output horizontal sync signal generated by the output horizontal sync signal generation circuit 48 to generate an output vertical sync signal of 120 Hz. The read control circuit 410 performs phase adjustment processing on the 57.2 MHz dot clock and supplies it to the D / A conversion circuit 44, and further, based on the dot clock, the output horizontal synchronizing signal, and the output vertical synchronizing signal, a field memory. A read control signal 412 is generated and supplied to the field memory 412.

As in the first embodiment, the field memory 412 reads out a video signal for one field for each line at intervals of one output horizontal scanning cycle. However,
The scanning speed conversion circuit 4 of the first embodiment has a read speed twice the writing speed, whereas the scanning speed conversion circuit 4 of this embodiment has a read speed four times the writing speed. Even if the number of lines is doubled by the invalid scanning line interpolation, the reading from the field memory 412 is completed in the time of 1/2 output vertical scanning cycle. Therefore, the remaining 1 /
By rereading the video signal for one field again during the time period of two input horizontal scanning cycles, the field double speed can be achieved.

The D / A conversion circuit 44 converts the field-doubled video signal into an analog signal and supplies it to the video signal output terminal 45. 7A and 7B are schematic diagrams when a video signal subjected to the scanning speed conversion processing by the scanning speed conversion circuit 4 of this embodiment is displayed on the CRT display device 7, where (a) is an odd field and (b) is. The scanning line positions and the number of fields of even fields are shown. Similar to the first embodiment, the solid line is the effective scanning line on which the video signal is displayed, and the dotted line is the invalid scanning line on which the video signal is not displayed. The position of the scanning line is exactly the same as that of the first embodiment, but the number of fields is doubled. Therefore, a large area flicker can be suppressed.

In this embodiment, the vertical scanning frequency is 2
Although the example in the case of conversion to double is described, it is not limited to double, and the scanning speed conversion circuit according to the present invention can cope with this even in the case of conversion to n. Also in this case, similar to the first embodiment, the case is not limited to the case where the horizontal scanning frequency is doubled, and reading is performed at a speed n times (n is a natural number) the writing of the field memory 412. Only one line is an effective scanning line,
By making the remaining n-1 scanning lines invalid scanning lines, the horizontal scanning frequency can be converted to n times.

A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 8 is a block diagram showing the configuration of the scanning speed conversion circuit 4 of the display device according to the third embodiment of the present invention. The same circuit means as the circuit means in the second embodiment shown in FIG. 6 are designated by the same reference numerals, and overlapping description will be omitted.

In the second embodiment described above, the write control circuit 49 and the read control circuit 410 generate the control signal for the field memory 412 based on the dot clock supplied from the dot clock generation circuit 47, whereas
In this embodiment, the write system dot clock generation circuit 4 is used.
16 and a read system dot clock generation circuit 417 are provided independently of each other, and this is an example of a device that performs the reading asynchronously with the writing of the field memory 412, which is a difference from the second embodiment.

In such asynchronous writing and reading, a so-called address overtaking phenomenon occurs in which the read address of the field memory 412 overtakes the write address. Therefore, in this embodiment, the second field memory 418 is provided and the field is overwritten. The video signal is alternately written every time, and at the time of reading, the video signal of the field memory 412 (418) of which writing has been completed is read to suppress the image quality deterioration due to the address overtaking phenomenon. Further, since the read dot clock generation circuit 417 does not need to be synchronized with the write dot clock generation circuit 416, for example, an independent crystal oscillation circuit can be used.

As described above, in this embodiment, since the reading can be performed asynchronously with the writing in the field memories 412 and 418, for example, the scanning speed of the video signal of the NTSC system can be changed to that of the video signal in an arbitrary computer or the like. It can be converted into scanning speed.

In this embodiment, the input video signal is NTS.
Although the example of the C type video signal has been described, the present invention is not limited to the NTSC type video signal.
It goes without saying that any signal of the L system, SECAM system, or interlace system such as a high-definition television signal can be applied.

Next, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 9 is a block diagram showing the configuration of a display device according to a fourth embodiment of the present invention, which is a device for synthesizing two video signals having different scanning speeds and displaying them on the same display screen. Here is an example. The same circuit means as those of the display device shown in FIG. 1 are designated by the same reference numerals, and a duplicate description will be omitted.

In FIG. 9, an engineering workstation (hereinafter abbreviated as EWS signal source) 8 as a second video signal source outputs a video signal having a display resolution of, for example, 1280 dots in the horizontal direction and 1024 dots in the vertical direction. appear. In this embodiment, N which is the first video signal source is displayed on the screen displaying the video signal from the EWS signal source 8.
CR by inserting the image of the video signal from the TSC signal source 1
It is an example of a device to be displayed on the T display device 7.

FIG. 10 is a block diagram showing the structure of the scanning speed conversion circuit 4 in this embodiment. 419 is EW
A video signal input terminal from the S signal source 8 is a video signal switching circuit 420. This video signal switching circuit 42
0 inputs the video signal from the EWS signal source 8 to the input terminal 420a, and inputs the output video signal from the D / A conversion circuit 44 subjected to the scanning speed conversion processing to the input terminal 420b,
Based on the switching control signal input from the read control circuit 410, the video signal from the EWS signal source 8 and the D / A
The output video signal from the conversion circuit 44 is switched and selectively output to the video signal output terminal 45. Reference numeral 421 is an input terminal for a horizontal synchronizing signal from the EWS signal source 8 and 422 is an input terminal for a vertical synchronizing signal from the EWS signal source 8.

The write control circuit 49 has a video input terminal 4
The NTSC video signal input to 1 is converted into a digital video signal by the A / D conversion circuit 42, and then written in the field memories 412 and 418 alternately for each field. The read control circuit 410 generates a control signal of the video signal switching circuit 420, that is, a control signal indicating the display position of the NTSC video signal, and supplies the control signal to the video signal switching circuit 420, and further, the video signal switching circuit 420. The field memories 412 and 418 are controlled so as to read from the field memories 412 and 418 while the NTSC video signal is selected. Then, in the video signal switching circuit 420, a part of the period for displaying the video signal from the EWS signal source 8 is switched to the NTSC system video signal subjected to the scanning speed conversion process, and the NTSC system video signal is switched to the video signal. Output terminal 45
Supply to.

FIG. 11 is a schematic display diagram of the CRT display device 7 in this embodiment. (A) is an odd frame,
(B) shows the scanning line positions of even frames. According to this embodiment, as shown in FIG. 11, the EWS signal source 8
The image of the NTSC system video signal can be displayed in the window form on the screen displaying the video signal. It is also clear that the resolution of the display image by the NTSC video signal inside the window is not deteriorated as in the first to third embodiments.

In this embodiment, an example of an apparatus for displaying an image by the video signal from the NTSC signal source 1 by inserting it in the screen by the video signal from the EWS signal source 8 is described, but the invention is not limited to this. However, it goes without saying that any signal may be used as long as the second video signal has a higher resolution than the first video signal and the first video signal is an interlaced signal.

Next, a fifth embodiment of the present invention will be described with reference to the drawings. The display device of the fifth embodiment is an example of a device using a matrix type display device such as liquid crystal or plasma, and an example of a device using a liquid crystal type display device will be described with reference to FIG.

In FIG. 12, a liquid crystal display device 9 has a resolution of 640 dots in the horizontal direction and 480 lines in the vertical direction, and has a horizontal scanning circuit 91 and a vertical scanning circuit 92 built therein. Further, as shown in FIG. 2, a scanning speed conversion circuit 4 of a system that doubles the number of lines using a line memory is provided. Since the number of effective scanning lines of the NTSC system video signal is 242.5 per field, the scanning speed conversion circuit 4 doubles the number of lines to convert it to 485 and outputs it. The liquid crystal display device 9 is
Since it has a resolution of 480 lines in the vertical direction, the video signal input from the scanning speed conversion circuit 4 can be displayed on almost the entire screen.

In the display device of this embodiment, the case of using the scanning speed conversion circuit 4 shown in FIG. 2 has been described, but the present invention is not limited to this, and the scanning speed shown in FIGS. 6, 8 and 10 is used. It can be modified to use the conversion circuit 4.

As described above, the display device of the present invention is
The display device is not limited to the CRT, and a matrix type display device such as liquid crystal or plasma may be used. When the display device is compatible with the input of the digital video signal, the D / A conversion circuit 44 is omitted in the first to fifth embodiments described above, and the digital video signal is input to the display device. It goes without saying that you should do this.

Next, a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram of the scanning speed conversion circuit unit 4 of the display device according to the sixth embodiment of the present invention. The same circuit means as those in the above-described embodiment are designated by the same reference numerals, and the duplicated description will be omitted.

This embodiment is a display device in which the horizontal scanning frequency is doubled by doubling the number of fields. In particular, the even field video signal read first from the field memory 412 has one horizontal scanning period. A read delay circuit 423 that delays the read start signal from the read control circuit 410 so as to be delayed is provided. FIG. 14 shows the scanning line positions that can be placed on this display device.

Next, a seventh embodiment of the present invention will be described with reference to the drawings. FIG. 15 is a block diagram of the scanning speed conversion circuit unit 4 of the display device according to the seventh embodiment of the present invention. The same circuit means as those in the above-described embodiment are designated by the same reference numerals, and the duplicated description will be omitted.

This embodiment is a display device in which the horizontal scanning frequency is doubled by doubling the number of fields. In particular, output video signals of the same continuous field are displayed at the same scanning line position. Thus, the output vertical synchronizing signal shifting circuit 424 for shifting the output vertical synchronizing signal is provided. FIG. 16 shows scanning line positions in this display device.

Next, an eighth embodiment of the present invention will be described with reference to the drawings. FIG. 17 is a block diagram of the scanning speed conversion circuit 4 of the display device according to the eighth embodiment of the present invention.

In this embodiment, a field discriminating circuit 425 for discriminating whether the input video signal is of an odd field or an even field and outputting the discrimination result is provided, and the output vertical synchronizing signal shifting circuit 424 outputs the output synchronizing signal. This is an example of an apparatus in which the phase of the output vertical synchronizing signal output from the generation circuit 426 is selectively shifted in dot clock units based on the field determination signal output from the field determination circuit 425. The same circuit means as those in the seventh embodiment shown in FIG. 15 are designated by the same reference numerals, and a duplicate description will be omitted.

FIG. 18 is a block diagram of the output vertical synchronizing signal shift circuit 424 of the scanning speed conversion circuit 4 of this embodiment. In FIG. 18, reference numeral 4241 denotes the synchronization signal generation circuit 4
An input terminal for the output vertical synchronizing signal output from
42 is an input terminal of the dot clock output from the dot clock generation circuit 47, 4243 is an input terminal of the field determination signal output from the field determination circuit 425,
Reference numeral 4244 is a first delay circuit, 4245 is a second delay circuit, 4246 is an output vertical synchronizing signal selection circuit, 4247 is a changeover switch, and 4248 is a vertical synchronizing signal output terminal of the output vertical synchronizing signal shifting circuit.

Next, the operation of this embodiment will be described with reference to FIG. FIG. 19 shows the output signal waveform of the main circuit means of this embodiment. (1) is the input vertical sync signal of the input video signal, and (2) is the field discrimination signal output from the field discrimination circuit 425. Signal, (3) is the output vertical synchronizing signal output from the output synchronizing signal generating circuit 426, (4) is the output horizontal synchronizing signal output from the output synchronizing signal generating circuit 426, and (5) is the first delay circuit 42.
44 is an output signal of 44, (6) is an output signal of the second delay circuit 4245, and (7) is an output vertical synchronizing signal output to the output terminal 4248.

The field discriminating circuit 425 counts the number of horizontal synchronizing signals in one vertical scanning period of the input video signal to determine whether the input video signal is of an odd field or an even field. To determine
As shown in (2), an "H" level field discrimination signal is output in the case of an odd field and an "L" level field discrimination signal is output in the case of an even field.

In the output vertical synchronizing signal shift circuit 424, the first delay circuit 4244 and the second delay circuit 4245 are provided.
Outputs the output vertical synchronization signal input to the input terminal 4241 after delaying the output vertical synchronization signal in dot clock units. In this embodiment, the delay amount of the first delay circuit 4244 is
As shown in (5), 0.5 output horizontal scanning cycle is set, and the delay amount of the second delay circuit 4245 is set to 1 output horizontal scanning cycle as shown in (6). The reason why such a set value is selected will be described later.

The output vertical synchronizing signal selection circuit 4246 counts the output vertical synchronizing signal input to the input terminal 4241. At this time, by clearing the count value at the rising edge of the field discrimination signal input from the input terminal 4243, the field immediately after the rising edge of the field discrimination signal is output as the first field, and the subsequent fields are the second field. Recognize as the third and fourth fields. And
As shown in (7), in the first field of the output, (3)
The output vertical synchronizing signal which has not been subjected to the delay processing shown in (5) is selected, and the output subjected to the delay processing of 0.5 output horizontal scanning cycle by the first delay circuit 4244 shown in (5) in the second field of the output. Select the vertical sync signal and output the third
In the field, the second delay circuit 4245 shown in (6)
The output vertical synchronizing signal subjected to the delay processing of one output horizontal scanning cycle is selected by, and in the fourth field of the output, the first delay circuit 4244 shown in (5) again selects 0.5 output horizontal scanning cycle. The changeover switch 4247 is controlled so as to select the output vertical synchronizing signal subjected to the delay processing.

In this way, the output vertical synchronizing signal selection circuit 4
The output vertical synchronizing signal output from the output terminal 4248 by controlling the changeover switch 4247 by the switch 246 has the first field of output of 263 output horizontal scanning period,
The second field is 263 output horizontal scanning period, the third field is 262 output horizontal scanning period, and the fourth field is 26
This is a 2-output horizontal scanning period, and this cycle is repeated in the subsequent fields.

The first delay circuit 4244, the second delay circuit 4245, and the output vertical synchronizing signal selection circuit 4246.
Can be easily configured by, for example, a counter, a shift register, a latch, or the like, and therefore detailed description thereof is omitted here.

Next, the scanning line structure in the CRT display device 7 using the scanning speed conversion circuit 4 will be described with reference to FIG. For the sake of simplicity, the deflection circuit 6 is assumed to have its center of vertical deflection at the center of the screen.

In FIG. 20, (a) to (d) are principle diagrams showing the scanning line position and the vertical size of the screen on the CRT display device 7 in the first to fourth fields of the output described above, respectively. Yes, (e) is a principle diagram showing the positional relationship of the scanning lines of the screen in which the four fields are combined.

The vertical size of the first and second fields of the output is 26 as shown in (a) and (b).
The vertical size of the third and fourth fields of the output is (c) and (d), while it is three horizontal scanning periods.
As shown in (2), the vertical size of the screen of the third field and the fourth field is smaller than that of the screen of the first field and the second field of the output by one horizontal scanning period because of the 262 horizontal scanning period. Since the center of vertical deflection of the CRT display device 7 is the central portion of the screen, when displaying the screens of the fields having different vertical sizes as described above, the central portions of the screens of the respective fields coincide with each other. Therefore, the screens of the third and fourth fields are
As compared with the field and second field screens, a space for 0.5 horizontal scanning period is generated above and below. That is, the scan lines of the third and fourth fields are
The scanning lines of the first field and the second field are displaced by 0.5 horizontal scanning period.

On the other hand, since the video signal of the odd field and the video signal of the even field are read twice from the field memory 412, the video signal of the odd field read first is displayed at the position (a) and read again. The video signal of the odd field is displayed at the same position as the video signal of the odd field read first as shown in (b). Similarly, the video signal of the even field first read from the field memory 412 is displayed at the position (c), and the video signal of the even field read again is the video signal of the odd field read first as shown in (d). It is displayed at the same position as the signal. Then, since these four fields are combined on the CRT display device 7, as shown in (e), the positional relationship of the scanning lines of the input video signal can be reproduced, and the vertical resolution cannot be deteriorated. Absent.

According to the scanning speed conversion circuit 4 as described above, in the display device equipped with the scanning speed conversion circuit of the type in which the horizontal scanning frequency is doubled by doubling the field frequency, the vertical deflection circuit is not required. Since there is no need to make changes, it is very advantageous in terms of cost and versatility.

Although the center of the vertical deflection of the deflection circuit 6 is the central portion of the screen in the present embodiment, the present invention is not limited to this, and the scanning speed of the display device according to the present invention is not limited to this. Since the output vertical synchronizing signal shift circuit 424 of the conversion circuit 4 can change the phase of the output vertical synchronizing signal in dot clock units, the deflection circuit 6
Even if the center of the vertical deflection is other than the center of the screen, it can be dealt with.

Next, a ninth embodiment of the present invention will be described with reference to the drawings. This embodiment is an example of a device that uses a deflection circuit 6 that deflects the CRT display device 7 so that the upper ends of the screens match when displaying fields with different numbers of lines. The same circuit means as the circuit means in the eighth embodiment are designated by the same reference numerals, and overlapping description will be omitted.

FIG. 21 is a block diagram of the output vertical synchronization signal shift circuit 424 of the scanning speed conversion circuit 4 of this embodiment. The output vertical synchronization signal shift circuit 42 of the eighth embodiment is shown in FIG.
4 is different in that the delay circuit 4244 is one system (the delay circuit 4245 is omitted).

Next, the operation of this embodiment will be described with reference to FIG. FIG. 22 shows the output signal waveform of the main circuit means of this embodiment.

In the output vertical synchronizing signal shift circuit 424, the first delay circuit 4244 subjects the output vertical synchronizing signal input to the input terminal 4241 to delay processing in dot clock units and outputs it. In this embodiment, the delay amount of the first delay circuit 4244 is as shown in (5) of FIG.
The output horizontal scanning period is set to 0.5.

The output vertical synchronizing signal selection circuit 4246 selects the output vertical synchronizing signal not subjected to the delay processing shown in (3) in the first field of the output and outputs it, as shown in (7) in FIG. In the second field and the third field of the first delay circuit 4244 as shown in (5).
The output vertical synchronizing signal subjected to the delay processing of 0.5 output horizontal scanning cycle is selected by, and in the fourth field, again,
The changeover switch 4247 is controlled so as to select the output vertical synchronizing signal which is not subjected to the delay processing shown in (3).

In this way, the output vertical synchronization signal selection circuit 4
The output vertical synchronizing signal output from the output terminal 4248 by controlling the changeover switch 4247 by the switch 246 has the first field of output of 263 output horizontal scanning period,
The second field is a 262.5 output horizontal scanning period, the third field is a 2rEv'p scan figure scanning period, the fourth field is a 262.5 output horizontal scanning period, and this cycle is repeated in the subsequent fields.

Next, the scanning line structure in the CRT display device 7 using the scanning speed conversion circuit 4 will be described with reference to FIG.

In FIG. 23, (a) to (d) are principle diagrams showing the scanning line position and the vertical size of the screen on the CRT display device 7 in the first to fourth fields of the output, respectively. Yes, (e) is a principle diagram showing the positional relationship of the scanning lines of the screen in which the four fields are combined.

As described above, when displaying fields having different numbers of lines, the CRT is arranged so that the upper ends of the screens coincide with each other.
Since the deflection circuit 6 that deflects the display device 7 is used, the upper ends of the screens of the respective fields are aligned. Since the screens of these fields are combined on the CRT display device 7, the positional relationship of the scanning lines of the input video signal can be reproduced as shown in (e), and the vertical resolution is not deteriorated. .

According to this embodiment, the scanning speed of an interlaced signal having a low horizontal scanning frequency such as an NTSC signal can be doubled without deteriorating the vertical resolution, and high quality with a large area flicker suppressed. Such an image can be displayed on a display device having a conventional display drive circuit.

[0090]

As described above, the display apparatus according to the present invention does not require the conventional signal-to-strength interpolation processing for converting the scanning speed of the interlaced signal, so that it does not increase the memory capacity and is simple. With such a configuration, the scanning speed of the video signal can be converted. Moreover, by shifting the phase of the output vertical synchronizing signal to correct the scanning position,
It is possible to always display the correct positions on the CRT screen without confusing the positions where the odd-numbered field scanning lines and the even-field scanning lines of the video signal are displayed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a display device according to the present invention.

FIG. 2 is a block diagram of a rowing speed conversion circuit in the display device according to the present invention shown in FIG.

FIG. 3 is a waveform diagram showing operation timings of respective parts of the scanning speed conversion circuit in the display device according to the present invention shown in FIG.

FIG. 4 is a schematic diagram showing scanning line positions of an NTSC video signal.

FIG. 5 is a schematic diagram showing scanning line positions of a display image in the first embodiment of the display device according to the present invention.

FIG. 6 is a block diagram of a scanning speed conversion circuit in a second embodiment of the display device according to the present invention.

FIG. 7 is a schematic diagram showing scanning line positions of a display image in a second embodiment of the display device according to the present invention.

FIG. 8 is a block diagram of a scanning speed conversion circuit in a third embodiment of the display device according to the present invention.

FIG. 9 is a block diagram showing a fourth embodiment of the display device according to the present invention.

FIG. 10 is a block diagram of a scanning speed conversion circuit of a fourth embodiment of the display device according to the present invention shown in FIG.

FIG. 11 is a schematic diagram showing scanning line positions of a display image in a fourth embodiment of the display device according to the present invention.

FIG. 12 is a block diagram showing a fifth embodiment of the display device according to the present invention.

FIG. 13 is a block diagram of a scanning speed conversion circuit in a sixth embodiment of the display device according to the present invention.

FIG. 14 is a schematic diagram showing scanning line positions of a display image in a sixth embodiment of the display device according to the present invention.

FIG. 15 is a block diagram of a scanning speed conversion circuit in a seventh embodiment of the display device according to the present invention.

FIG. 16 is a schematic diagram showing scanning line positions of a display image in a seventh embodiment of the display device according to the present invention.

FIG. 17 is a block diagram of a scanning speed conversion circuit in an eighth embodiment of the display device according to the present invention.

18 is a block diagram of an output synchronization signal shift circuit of a scanning speed conversion circuit in an eighth embodiment of the display device according to the present invention shown in FIG.

FIG. 19 is a signal waveform diagram showing operation timings of main circuit means in the scanning speed conversion circuit of the eighth embodiment of the display device according to the present invention.

FIG. 20 is a principle view showing a scanning line structure in a CRT display device in an eighth embodiment of the display device according to the present invention.

FIG. 21 is a block diagram of an output synchronization signal shift circuit in a scanning speed conversion circuit of a ninth embodiment of the display device according to the present invention.

FIG. 22 is a signal waveform diagram showing operation timings of main circuit means in the scanning speed conversion circuit in the ninth embodiment of the display device according to the present invention.

FIG. 23 is a principle diagram showing a scanning line structure in a CRT display device in an eighth embodiment of the display device according to the present invention.

[Explanation of symbols]

1 ... NTSC signal source, 2 ... video signal processing circuit, 3 ... synchronization separation circuit, 4 ... scanning speed conversion circuit, 5 ... video output circuit, 6 ... deflecting circuit, 7 ... CRT display device, 8 ... EWS signal source, 9 ... Liquid crystal display device, 41 ... Video signal input terminal, 4
2 ... A / D conversion circuit, 43 ... Line memory, 44 ... D /
A conversion circuit, 45 ... Video signal output terminal, 46 ... Horizontal synchronization signal input terminal, 47 ... Dot clock generation circuit, 48 ...
Output horizontal sync signal generation circuit, 49 ... Write control circuit,
Reference numeral 410 ... Read control circuit, 411 ... Horizontal sync signal output terminal, 412 ... Field memory, 413 ... Vertical sync signal input terminal, 414 ... Output vertical sync signal generation circuit, 41
5 ... Vertical sync signal output terminal, 416 ... Write dot clock generation circuit, 417 ... Read dot clock generation circuit, 418 ... Second field memory, 419 ... Second
Video signal input terminal, 420 ... video signal switching circuit,
420a ... second video signal input terminal of video signal switching circuit, 420b ... video signal input terminal subjected to scanning speed conversion of video signal switching circuit, 421 ... second video signal horizontal sync signal input terminal, 422 ... vertical sync signal input terminal of the second video signal, 423 ... read delay circuit,
424 ... Output horizontal sync signal shift circuit, 4241 ... Vertical sync signal input terminal, 4242 ... Dot clock input terminal, 4243 ... Field discrimination signal input terminal, 42
44 ... First delay circuit, 4245 ... Second delay circuit, 4
246 ... Output vertical synchronizing signal selection circuit, 4247 ... Changeover switch, 4248 ... Vertical synchronizing signal output terminal, 42
5 ... Field discrimination circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sadao Tsuruga 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Multimedia system development headquarters (72) Inventor Jiro Kawasaki Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address 292, Hitachi Ltd., Information & Video Division (72) Inventor Go Sano Yoshida Town, Totsuka-ku, Yokohama, Kanagawa 292 Address Hitachi, Ltd., Information & Video Division

Claims (14)

[Claims] 1. An at least one scanning line segment of an input interlaced video signal is stored in a memory, and the video signal stored in this memory is read at a speed n times the input speed to obtain a scan speed n times the speed. In a display device having a scanning speed conversion means for outputting a video signal and a display means for displaying a video signal whose scanning speed has been converted, the scanning speed conversion means is n times as fast as a video signal writing speed to the memory. During the 1 / n horizontal scanning period of writing, a video signal for one scanning line is read from the memory, the reading is stopped for the remaining (n-1) / n horizontal scanning period, and the reading is performed in the previous field in the next field. During the horizontal scanning period that has been stopped, the video signal for one scanning line is read from the memory at a speed of n times during the 1 / n horizontal scanning period and is read during the other horizontal scanning periods. A display device comprising a memory control signal generating means for stopping. 2. The scanning speed conversion means according to claim 1, wherein the scanning speed conversion means converts an input interlaced video signal into a digital signal, and at least one line output from the A / D conversion circuit. Minute line video signal, a dot clock generation circuit that generates a dot clock by multiplying the horizontal synchronization signal of the input video signal, the input horizontal synchronization signal and the output from the dot clock generation circuit. A write control circuit for generating a write control signal for the line memory based on a clock, and an output horizontal sync signal for generating an output horizontal sync signal based on the input horizontal sync signal and the clock output from the dot clock generation circuit. The signal generating circuit, the input horizontal synchronizing signal, and the clock output from the dot clock generating circuit. Display apparatus characterized by comprising a reading control circuit for generating a read control signal of the line memory based on. 3. The A / D conversion circuit for converting an input interlaced video signal into a digital signal, and at least one field output from the A / D conversion circuit. Field memory storing the video signal, a dot clock generation circuit for generating a dot clock by multiplying the horizontal synchronization signal of the input video signal, the input horizontal synchronization signal and the clock output from the dot clock generation circuit A write control circuit for generating a write control signal for the field memory based on an input vertical sync signal; and an output horizontal sync signal based on the input horizontal sync signal and a clock output from the dot clock generation circuit. Output horizontal sync signal generating circuit, and the input horizontal sync signal and vertical sync signal An output vertical synchronizing signal generating circuit for generating an output vertical synchronizing signal based on the output vertical synchronizing signal generating circuit, a clock output from the dot clock generating circuit, a synchronizing signal output from the output horizontal synchronizing signal generating circuit, and an output vertical synchronizing signal generating circuit. A display device comprising a read control circuit for generating a read control signal for the field memory based on an output synchronization signal. 4. The scanning speed conversion means according to claim 1, wherein the scanning speed conversion means converts an input interlaced video signal into a digital signal, and at least one field output from the A / D conversion circuit. Two field memories for alternately storing minute video signals, a write dot clock generation circuit for multiplying a horizontal synchronizing signal of the input video signal to generate a dot clock for a write system of the field memory, A write control circuit for generating a write control signal for the field memory based on a horizontal sync signal, a clock output from the write dot clock generation circuit, and an input vertical sync signal, and a dot clock for a read system of the field memory. A read dot clock generation circuit to generate,
An output horizontal synchronization signal generation circuit that generates an output horizontal synchronization signal based on the clock output from the read dot clock generation circuit, and an output vertical synchronization signal based on the synchronization signal output from the output horizontal synchronization signal generation circuit. An output vertical synchronizing signal generating circuit, a clock output from the read dot clock generating circuit, a synchronizing signal output from the output horizontal synchronizing signal generating circuit, and a synchronizing signal output from the output vertical synchronizing signal generating circuit. A display device comprising a read control circuit for generating a read control signal for the field memory based on the above. 5. An input unit for inputting a first video signal of interlace system, an input unit for inputting a second video signal of non-interlace system, and a scanning speed for converting the scanning speed of the first video signal. The conversion device includes a conversion device, a switching device that switches between the first video signal and the second video signal that have undergone the scanning speed conversion process, and selectively outputs the video signal, and a display device that displays the video signal output from the switching device. In the display device, the scanning speed conversion means stores a memory for storing an input video signal of at least one scanning line and a writing speed 1 / n of a writing speed of the video signal to the memory.
A video signal for one scanning line is read from the memory in two horizontal scanning periods, and reading is stopped for the remaining (n-1) / n horizontal scanning periods, and reading is stopped in the previous field in the next field. Memory control signal generating means for reading out a video signal of one scanning line from the memory at a speed n times higher than that of the memory in the horizontal scanning period in the 1 / n horizontal scanning period and stopping the reading in the other horizontal scanning period is provided. Display device. 6. The A / D conversion circuit according to claim 5, wherein the scanning speed conversion means converts an input interlaced first video signal into a digital signal, and the A / D conversion circuit.
Two field memories that store at least one field of video signals output from the conversion circuit and a horizontal sync signal of the input first video signal are multiplied to generate a write-system dot clock for the field memory. A write dot crack generation circuit, the field memory based on a horizontal synchronization signal of the input first video signal, a clock output from the write dot clock generation circuit, and a vertical synchronization signal of the input first video signal. Write control circuit for generating the write control signal, a read dot clock generation circuit for generating a dot clock for the read system of the field memory by multiplying the horizontal synchronizing signal of the input second video signal, and the read dot The clock output from the clock generation circuit and the input second video signal Display apparatus characterized by comprising a reading control circuit for generating a read control signal of the field memory based on a horizontal synchronizing signal and a vertical synchronizing signal. 7. The display device with a scanning speed conversion function according to claim 2, wherein the read control circuit reads a video signal from the line memory or the field memory at a speed that is an even multiple of a writing speed. . 8. A display device according to claim 2, 3, 4, or 6, wherein the dot clock generation circuit uses a PLL circuit. 9. The display device according to claim 4, wherein the write dot clock generation circuit uses a PLL circuit, and the read dot clock generation circuit uses a crystal oscillation circuit. 10. The display device according to claim 1, wherein the display means is a CRT type display, a liquid crystal type display or a plasma type display. 11. An A / D conversion circuit for converting an input interlaced video signal into a digital signal, and the A / D conversion circuit.
A field memory for storing a video signal for at least one field output from the D / D conversion circuit, a dot clock generation circuit for multiplying an input horizontal synchronizing signal of the input video signal to generate a dot clock, and the field memory A write control circuit for controlling the writing of the data, a read control circuit for controlling the reading of the field memory, and an output for dividing the dot clock generated by the dot clock generation circuit to generate horizontal and vertical synchronization signals of the output. It has a synchronizing signal generating circuit and the number of fields is n.
In a display device equipped with a scanning speed conversion device for doubling the horizontal scanning frequency by n times, reading from a reading control circuit is performed so that an even field video signal read first from the memory is delayed by one horizontal scanning cycle. A display device comprising a read delay circuit for delaying a start signal. 12. An A / D conversion circuit for converting an input interlaced video signal into a digital signal, and the A / D conversion circuit.
A field memory for storing a video signal for at least one field output from the D / D conversion circuit, a dot clock generation circuit for multiplying a horizontal synchronizing signal of the input video signal to generate a dot clock, and the field memory A write control circuit that controls writing, a read control circuit that controls reading of the field memory, and a dot clock generated by the dot clock generation circuit, and output synchronization that generates horizontal and vertical synchronization signals of the output. In a display device having a signal generation circuit and a scanning speed conversion device for increasing the horizontal scanning frequency by n times by multiplying the number of fields by n times, consecutive output video signals of the same field are at the same scanning line position. Set up an output vertical sync signal shift circuit that shifts the output vertical sync signal so that it is displayed. A display device characterized by a mark. 13. A display device comprising a scanning speed conversion circuit for increasing the horizontal scanning frequency by n times by increasing the field frequency of an input interlaced video signal by n times, wherein the scanning speed conversion circuit is an input device. An A / D conversion circuit for converting the converted analog video signal into a digital signal, and
A memory for storing at least one field of the video signal output from the D / D conversion circuit, and D for converting the video signal read from this memory into an analog video signal and outputting the analog video signal.
/ A conversion circuit, a dot clock generation circuit that generates a dot clock by multiplying the horizontal synchronization signal of the input video signal, and an input horizontal synchronization of the dot clock generated by this dot clock generation circuit and the input video signal A write control circuit that generates a write control signal for the memory from a signal and a vertical sync signal, and counts the dot clock generated by the dot clock generation circuit to generate an output horizontal sync signal and a vertical sync signal having a frequency n times as high as the input frequency. An output synchronizing signal generating circuit for generating and outputting, a field discriminating circuit for discriminating between an odd field and an even field from a horizontal synchronizing signal and a vertical synchronizing signal of an inputted video signal and outputting a field discriminating signal, and the field discriminating circuit. The vertical sync signal output from the output sync signal generation circuit based on the signal An output vertical synchronization signal shift circuit that shifts and outputs the dot clock generated by the lock generation circuit, a dot clock generated by the dot clock generation circuit, an output horizontal synchronization signal output from the output synchronization signal generation circuit, and the output A display device comprising: a read control circuit that controls reading from the memory based on an output vertical sync signal output from a vertical sync signal shift circuit and the field discrimination signal. 14. The output vertical synchronization signal shift circuit according to claim 13, wherein the output vertical synchronization signal output from the output synchronization signal generation circuit is shifted by the dot clock unit generated by the dot clock generation circuit and output. At least one delay circuit, a switching circuit for switching and outputting the output signal of the delay circuit, and controlling the switching circuit based on the field discrimination signal and the output vertical synchronizing signal output from the output synchronizing signal generating circuit. A display device comprising an output vertical synchronizing signal selection circuit.