JP3804893B2 - Video signal processing circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a video signal processing circuit for converting an interlaced NTSC video signal into a digital signal, temporarily writing it into one memory, and displaying it in a non-interlaced format.
[0002]
[Prior art]
When outputting an analog video signal to a display device such as a CRT or LCD, the analog video signal is once converted into a digital video signal and written into a memory, and in that state, processing such as brightness correction, frequency conversion, noise removal, etc. is performed. Output in interlace format and output to display device. At this time, there are two types of video signals written in the memory, an interlace method (interlaced scanning method) or a non-interlace method (sequential operation method) depending on the scanning method.
[0003]
The non-interlace method is a scanning method in which horizontal scanning lines are sequentially scanned from the upper left of the screen without jumping during scanning, and one frame image is formed by one scanning. In this non-interlace method, since the scanning lines are sequentially scanned, the sequential writing method is adopted for the memory, the control is easy, and the control circuit can be simply realized. On the other hand, the interlace method currently used for the NTSC signal, which is a standard video signal of a television in Japan, is an image of one frame by alternately scanning an odd field and an even field of the video signal. Is a scanning method. In this interlace method, one frame is formed by two scans. Conventionally, there are the following writing methods when writing an NTSC signal to a memory.
[0004]
FIG. 11 is a block diagram showing a configuration example of an apparatus according to a memory control method disclosed in Japanese Patent Laid-Open No. 62-163092. When an interlace video signal is written into the memory using this apparatus, an odd field memory 13 for writing an odd field of the video signal and an even field memory 14 for writing an even field are used.
[0005]
The write destination control circuit 12 determines whether the video signal is an odd field signal or an even field signal based on the synchronization signal separated from the analog video signal by the synchronization signal separation circuit 11, and is used for the odd field. In this case, the video signal digitized by the A / D converter 16 is stored in the odd field memory 13, and in the case of the even field, the video signal digitized by the A / D converter 16 is stored in the even field memory 14. Sort and write each.
[0006]
FIG. 12 is a memory map showing a state in which the video signals for each line are written in both the field memories 13 and 14 described above. Lines 1, 3,... 2, 4 ... are written respectively.
[0007]
Thus, the video signals separated and written in the field memories 13 and 14 by the write destination control circuit 12 are restored by the multiplexer 15 in synchronization with a display synchronization signal (not shown) and supplied as RGB signals to a cathode ray tube or the like. Is done.
[0008]
FIG. 13 is a block diagram showing a configuration example of an apparatus according to the memory address control method disclosed in Japanese Patent Laid-Open No. 8-32938. Here, instead of the odd field memory and the even field memory, there is an odd / even field memory 24 capable of writing video signals of both odd and even fields by one, and when writing odd field video signals and even field video signals. A connection switching unit 23 is provided for switching the connection destination of the address bus of the odd / even field memory 24 at the time of writing.
[0009]
The connection switching unit 23 is connected to the address counter circuit 22 on one end side and is connected to the odd / even field memory 24 on the other end side. When an interlaced video signal is input to this circuit, the address counter circuit 22 generates an appropriate address under the control of the synchronizing signal separation circuit 21, and the video data of the odd-numbered lines 1, 1, 3,. Writing is performed at a write destination determined by an address assigned to each of the odd / even field memory 24, and then video data of the line 2, line 4... Line 2n of the even field is similarly determined by an address assigned to each of the odd / even field memory 24. Written first.
[0010]
FIG. 14 is a memory map showing a state in which the video signal for each line is written in the odd / even field memory 24. Lines 1, 2, 3, 4... Are written in the odd / even field memory 24 as they are. The video data of the frame.
[0011]
The video signal written in the odd / even field memory 24 in this way is supplied as it is to the cathode ray tube or the like as an RGB signal in synchronism with a display synchronization signal (not shown).
[0012]
[Problems to be solved by the invention]
In the memory address control method disclosed in the above-mentioned JP-A-62-163092, when writing a video signal, a separate memory is required for each of the odd and even fields, and the cost is high. The area occupied by the substrate also increases. On the other hand, in the memory address control method disclosed in Japanese Patent Application Laid-Open No. 8-32938, since the odd and even fields of the video signal are written using one memory, the area occupied by the substrate of the memory is reduced. Since the video signal is written by providing a connection destination switching unit that switches the connection destination of the memory address bus between when writing odd fields and when writing even fields, the device becomes very large and has an address bus function. Therefore, the type of memory that can be used is limited, leading to an increase in the cost of the apparatus.
[0013]
The present invention has been made in view of such circumstances, and a memory required for writing video data of even fields when writing video data of odd fields using address control signals and write signals generated from video signals. When writing even field video data, avoid the memory area where the odd field video data has already been written. It is an object of the present invention to provide a video signal processing circuit that can be performed on one inexpensive memory without providing a means for switching.
[0014]
[Means for Solving the Problems]
The video signal processing circuit according to the present invention is a video signal processing circuit for writing video data of each line into one memory in order to display an interlace video signal composed of odd fields and even fields in a non-interlace method. When writing the video data of each line in the odd field to the memory The address control basic clock is output as the address control clock only during the period in which the number of dots for one line is counted by the address control basic clock every period other than the horizontal display period from the predetermined timing. When writing the video data of each line in the even field to the memory The address control clock is output by switching the predetermined timing for a period of one line. Write in address control signal output section and horizontal display period clock Address control in other periods clock A clock selection unit that selects and applies to the memory, and writes to the memory from the clock selection unit clock Write in a given period clock 1 line of video data is stored in synchronization with the address control clock Address control during a given period clock Accordingly, the address for one line is incremented.
[0015]
In such a video signal processing circuit of the present invention, when the video data of each line in the odd field is written to the memory, The address control basic clock is output as the address control clock only during the period in which the number of dots for one line is counted by the address control basic clock every period other than the horizontal display period from the predetermined timing. When writing the video data of each line in the even field to the memory The address control clock is output by switching the predetermined timing for a period of one line. And note Re Write from the clock selector when writing video data for each line to clock Write in a given period clock The video data for one line is stored in synchronization with the address control. clock Address control during a given period clock Accordingly, the address for one line is incremented according to the above. Therefore, when writing the video data of the odd field, the writing is performed while avoiding the memory area necessary for writing the video data of the even field, and the video data of the even field is written. At this time, the writing is performed while avoiding the memory area where the video data of the odd field has already been written. Therefore, it is possible to carry out a single inexpensive memory without separately providing means for switching the connection destination of the memory address bus.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings illustrating embodiments thereof.
[0017]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of a video signal processing circuit according to Embodiment 1 of the present invention.
[0018]
The synchronization signal separation unit 10 includes a horizontal synchronization signal separation function for separating the horizontal synchronization signal HS from the interlaced analog video signal employed in the NTSC signal, which is one of the standard television video signals, and a vertical synchronization signal VS. It has a vertical synchronizing signal separating function for separating and a field identifying signal separating function for separating the field identifying signal O / E. The synchronization signal separation unit 10 outputs the horizontal synchronization signal HS to the write signal generation unit 20 and the horizontal display period signal generation unit 40, the horizontal synchronization signal HS and the vertical synchronization signal VS to the vertical display period signal generation unit 50, and the address increment control signal. A vertical synchronization signal VS and a field identification signal O / E are supplied to the generation unit 60, respectively.
[0019]
The write signal generation unit 20 writes the video data constituting each line of the video signal from the horizontal synchronization signal HS separated and output by the synchronization signal separation unit 10 to the memory 100 having a capacity capable of writing one frame of the video signal. A write clock DCLK, which is a dot clock used at this time, is generated, and this signal is output to the horizontal display period signal generator 40 and the clock selector 90.
[0020]
The write clock DCLK is a clock corresponding to one dot of the digital image, and therefore its frequency is determined depending on the resolution of the display device and the video display period. For example, when the resolution is XGA (1024 × 768 pixels) and the video display period is 40.554 μs, the frequency of the write clock DCLK is 25 MHz. The write clock DCLK can be generated in phase synchronization with the horizontal synchronization signal HS using, for example, a phase synchronization circuit (PLL).
[0021]
The horizontal display period signal generation unit 40 receives the horizontal synchronization signal HS output from the synchronization signal separation unit 10 and the write clock DCLK generated by the write signal generation unit 20. Here, the horizontal back porch A horizontal display period signal HD that controls the horizontal display period of the video obtained from the video signal by setting the period and the horizontal display period is generated. The vertical display period signal generation unit 50 receives the horizontal synchronization signal HS and the vertical synchronization signal VS output from the synchronization signal separation unit 10 described above. Here, the vertical back porch period and the vertical display period are set. Thus, the vertical display period signal VD for controlling the vertical display period of the video obtained from the video signal is generated.
[0022]
The horizontal display period signal HD thus selected is supplied to the AND gate 70, the clock selection unit 90, and the address increment control signal generation unit 60. The vertical display period signal VD is supplied to the AND gate 70 and the address increment control signal generation unit 60.
[0023]
In the AND gate 70, each line of the video signal is obtained from the logical product of the horizontal display period signal HD output from the horizontal display period signal generation unit 40 and the vertical display period signal VD output from the vertical display period signal generation unit 50. A write enable signal WE, which is a write enable signal for enabling or disabling the writing of the video data constituting the memory 100 to the memory 100, is generated and applied to the memory 100.
[0024]
The address control basic signal generation unit 30 generates an address control basic clock DCLK2 that is a basic signal of an address control signal that controls a write destination address of video data constituting each line of the video signal. Since this address control basic clock DCLK2 must be a clock with a fixed period, a crystal oscillator or the like is used for its generation. The generated address control basic clock DCLK2 is output to the address increment control signal generation unit 60 and the AND gate 80.
[0025]
FIG. 2 is a block diagram illustrating a configuration example of the address increment control signal generation unit 60, which includes a first block 61 and a second block 62.
[0026]
The first block 61 generates a control signal SA for switching the start timing of the address increment control signal (clock gate forward signal CGW) by one line according to the odd / even of the field, and the second block 62 sets the number of addresses to be incremented. At the same time, the control signal SB corresponding to the time corresponding to the number of addresses is generated. Specifically, the following processing is performed.
[0027]
The first block 61 is supplied with a horizontal display period signal HD, a vertical display period signal VD, a vertical synchronization signal VS, and a field identification signal O / E. The first line (first line) is processed in the odd field processing. So that the start address of the first line (second line) becomes the last value of the number of dots for one line (1024 in XGA) in the processing of even fields, respectively. A control signal SA is generated (this control signal SA is output to point A in FIG. 2).
[0028]
In the second block 62, a signal obtained by the logical sum of the control signals A and DCLK2 generated in the first block 61 is input to the counter, and the number of dots for one line (1024 in XGA) is counted. A control signal SB that enables address increment is generated during the counting period (this control signal SB is output to point B). Then, from the logical sum of the signal generated in the first block 61 as the logical sum signal of the horizontal display period signal HD and the vertical display period signal VD and the above-described control signal SB, the clock gate for write which is an address increment control signal. A signal CGW is generated.
[0029]
The AND gate 80 includes video data constituting each line of the video signal from the clock gate forward signal CGW output from the address increment control signal generator 60 and the address control basic clock DCLK2 output from the address control basic signal generator 30. The address control clock ADRCLK for controlling the write destination address is generated and output to the clock selector 90.
[0030]
The clock selection unit 90 includes a general-purpose selector or relay, and the horizontal display period signal generation unit 40 generates either the write clock DCLK generated by the write signal generation unit 20 or the address control clock ADRCLK generated by the AND gate 80. Selection is performed according to the horizontal display period signal HD. One of the selected clocks is given to the memory 100 as a write clock WCK, and the video data constituting each line of the video signal is written or the write destination address of the video data constituting each line of the video signal is incremented.
[0031]
Reference numeral 16 denotes an A / D converter, which digitizes the video signal and applies it to the memory 100.
[0032]
The vertical synchronization signal VS is used for a write reset WRST that is a signal for resetting a write destination address of the video signal in the memory 100. This write reset WRST initializes a write destination address when video data of each line of an interlace video signal is next input to the memory 100.
[0033]
FIG. 3 is a memory map showing allocation of write destination addresses in the memory 100 of video data constituting each line of an interlace video signal. H′00000,..., H′3FFFF, etc., shown on the left side are hexadecimal display addresses assigned to video data writing destinations constituting each line of the video signal. For example, the write destination of line 1 which is the first line of the odd field of the video signal is a write destination determined by addresses H′00000 and H′001FF, and this write destination is (H′00000−H′001FF) below. ).
[0034]
FIG. 4 is a timing chart when video data constituting each line of an interlace video signal is written in a memory. In the following description, when video data constituting each line of both fields of an interlaced video signal is written, each line in the odd field is written in the first writing process, and each line in the even field is written in the memory 100 in the second writing process. The case of writing to each will be described.
[0035]
First, video data of odd fields of 8 image signals is written into the memory 100. In this case, the clock selection unit 90 sets the write clock DCLK as the write clock WCK during the period in which the horizontal display period signal HD is “H”. Selected. On the other hand, in the period corresponding to one line, the number of dots for one line (1024 in XGA) is counted in the second block of the address increment control signal generator 60 shown in FIG. A control signal SB that enables the address increment is generated during the period in which the address increment is performed (this control signal SB is output to point B), thereby generating a clock gate forward signal CGW that is an address increment control signal. The
[0036]
Accordingly, in a period in which the write enable signal WE is “H” (high level) and the clock gate for write CGW is “H”, the memory 100 is supplied with a write clock WCK (write clock) from a predetermined address, for example, address 0. The video data for one line is written and stored in accordance with (equivalent to DCLK).
[0037]
In the period corresponding to one line (line 2) of the next even field, since the horizontal table period signal HD is “L”, the write enable signal WE is also “L”, and video data is written to the memory 100. Not done. However, since the address control clock ADRCLK is selected as the write clock WCK by the clock selection unit 90 during this period, the write address to the memory 100 is incremented by the number of addresses corresponding to one line.
[0038]
In the period corresponding to one line of the next odd field, the horizontal table period signal HD becomes “H”, the write enable signal WE also becomes “H”, and the write clock DCLK is selected as the write clock WCK. Since it is selected by the unit 90, the video data is written to the memory 100.
[0039]
By repeating the above processing, the video data in the odd field is sequentially written and stored in the memory 100 at a position that is skipped by the data amount for one line.
[0040]
FIG. 5 is a memory map when an odd field of an interlace video signal is written. Line 1 which is the first line of the video data constituting each line of the odd field of the video signal is (H'00000-H'001FF), and line 3 which is the second line is (H'00400-H '). 005FF),... And the 256th line 511 is written and stored in (H'3FC00-H'3FDFF).
[0041]
Next, the video data of the even field of the video signal is written. In this case, the horizontal table period signal HD is initially “L” in the period corresponding to the first line (line 1) of the odd field. The write enable signal WE also becomes “L”, and the video data is not written to the memory 100. However, since the address control clock ADRCLK is selected as the write clock WCK by the clock selection unit 90 during this period, the write address to the memory 100 is incremented by one line.
[0042]
Then, the write clock DCLK is selected as the write clock WCK by the clock selector 90 during the period in which the horizontal display period signal HD, which is the period of the first line (line 2) in the fool number field, is “H”. Therefore, in a period in which the write enable signal WE is “H” (high level) and the clock gate for write CGW is “H”, the memory 100 has one line from the predetermined address (line 1 which is an odd field). The video data for one line is written and stored in accordance with the write clock WCK (equivalent to the write clock DCLK) from the address next to the address corresponding to.
[0043]
In the period corresponding to one line (line 3) of the next odd field, since the horizontal table period signal HD is “L”, the write enable signal WE is also “L”, and video data is written to the memory 100. Not done. However, since the address control clock ADRCLK is selected as the write clock WCK by the clock selection unit 90 during this period, the write address to the memory 100 is incremented by the number of addresses corresponding to one line.
[0044]
In the period corresponding to one line (line 4) of the next even field, the horizontal table period signal HD becomes “H”, the write enable signal WE also becomes “H”, and the write clock DCLK becomes the write clock. Since WCK is selected by the clock selection unit 90, video data is written to the memory 100.
[0045]
By repeating the above processing, the video data of the even field jumps to the memory 100 by the data amount for one line, and the position where the video data of each line of the odd field is written first is avoided. Sequentially written and stored.
[0046]
FIG. 6 is a memory map when an even field of an interlace video signal is written. Line 2 as the first line of the video data constituting each line of the even field of the video signal is (H′00200-H′003FF), and line 4 as the second line is (H′00600-H ′). .., And the line 512, which is the 256th line, is written to (H′3FE00−H′3FFFF).
[0047]
FIG. 7 is a memory map when both fields of an interlace video signal are written. In the above-described two writing operations in the odd field and the even field, the video data of each line in the even field is written in the memory 100 so as to skip the position already written at the time of writing the odd field.
[0048]
(Embodiment 2)
FIG. 8 is a block diagram showing a configuration example of Embodiment 2 of the video signal processing circuit of the present invention. Hereinafter, the same reference numerals are used for the same or corresponding parts as those in the first embodiment, and the description thereof is omitted.
[0049]
In the first embodiment described above, the write clock DCLK for writing video data to the memory is generated by the write signal generator 20, and the address control clock ADRCLK for incrementing the write destination address is generated by the address control basic signal generator 30. The AND gate 80 generates a logical product of the address control basic clock DCLK2 and the clock gate forward CGW generated by the address increment control signal generation unit 60.
[0050]
In the second embodiment, the write clock DCLK is used as an address control signal for incrementing the write destination address, and this signal is generated by the address control basic signal generation unit 31 having the same configuration as the write signal generation unit 20 of the first embodiment. . Further, instead of the clock selection unit 90 of the first embodiment, a clock selection unit 91 having a frequency dividing circuit for dividing the input signal is provided. The frequency divider circuit of the clock selector 91 generates a write signal 1 / 2DCLK obtained by dividing the write clock DCLK supplied from the address control basic signal generator 31 by 1/2. The write signal 1 / 2DCLK is given to the horizontal display period signal generation unit 40 as a write signal when video data is written to the memory. In addition, the clock selection unit 91 selects either the write signal 1 / 2DCLK or the address control clock DCLK according to the horizontal display period signal HD, and provides it to the memory 100 as the write clock WCk.
[0051]
(Embodiment 3)
FIG. 9 is a block diagram showing a configuration example of the video signal processing circuit according to the third embodiment of the present invention. Hereinafter, the same reference numerals are used for the same or corresponding parts as those in the first embodiment or the second embodiment, and the description thereof is omitted.
[0052]
The NTSC signal, which is the current standard for television video signals in Japan, employs an interlace method. Such an interlaced video signal can be separated by the synchronization signal separation circuit 10 into a field identification signal O / E and a composite synchronization signal CS obtained by synthesizing the horizontal synchronization signal HS and the vertical synchronization signal VS. For this reason, in the third embodiment, instead of the horizontal display period signal generation unit 40 and the vertical display period signal generation unit 50 provided in the first embodiment, a horizontal and vertical display period signal HVD is generated. A vertical display period signal generation unit 41 is provided.
[0053]
The horizontal / vertical synchronization signal CS output from the synchronization signal separation unit 10 and the write clock DCLK output from the write signal generation unit 20 are input to the horizontal display period signal generation unit 40, where both horizontal and vertical back porch periods are input. Both horizontal and vertical display periods are set, and a horizontal / vertical display period signal HVD for controlling the horizontal display period and the vertical display period of the video obtained from the video signal is generated. The horizontal / vertical display period signal HVD serves as a write enable signal WE for enabling or disabling writing of video data constituting each line of the video signal.
[0054]
(Embodiment 4)
FIG. 10 is a block diagram showing a configuration example of the fourth embodiment of the video signal processing circuit of the present invention. Hereinafter, the same reference numerals are used for the same or corresponding parts as those in the first embodiment, the second embodiment, or the third embodiment, and the description thereof is omitted.
[0055]
In the fourth embodiment, instead of the write signal generation unit 20 of the first embodiment, the display frequency (for example, 25 MHz in the case of XGA) of the display device that displays the video extracted from the interlace video signal is set. A write signal generator 27 having a clock oscillator 271 that oscillates and a synchronous IC 272 that synchronizes with the frequency of the clock oscillated by the clock oscillator 271 is provided.
[0056]
The horizontal synchronizing signal HS, which is the output of the synchronizing signal separation unit 10, is synchronized with the clock oscillated by the clock oscillator 271 by using the synchronization IC 272, thereby writing the video data constituting each line of the video signal from the video signal to the memory. A write clock DCLK used at this time is generated.
[0057]
【The invention's effect】
As described above in detail, according to the video signal processing circuit of the present invention, means for switching the connection destination of the address bus of the memory is separately provided for the video data of each line of the odd field and the even field of the interlace video signal. Without a single memory. Therefore, since it is not necessary to provide the video signal processing circuit with a means for switching the connection of the memory address bus, which was conventionally required when writing the video signal in one memory, the video signal processing circuit does not become large-scale, Cost can be reduced. In addition, the video signal processing circuit is provided inside a video device such as a consumer television used when a high resolution video is realized by outputting an interlace video signal from a single memory. It is possible to further reduce the space of the apparatus, and at the same time, it is possible to provide high-resolution video at a lower cost than before.
[0058]
Further, according to the video signal processing circuit of the present invention, the internal configuration can be freely changed to some extent, so that the device design should be performed with sufficient consideration for the cost of realizing a high-resolution video. Can respond to various needs of users and contribute to further development of the media environment.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a video signal processing circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration example of an address increment control signal generation unit according to the first embodiment of the video signal processing circuit of the present invention.
FIG. 3 is a memory map showing assignment of write destination addresses of interlace video signals.
FIG. 4 is a timing chart when video data of each line of an interlace video signal of the video signal processing circuit of the present invention is written in a memory.
FIG. 5 is a memory map in a state where an odd field of an interlace video signal is written in the video signal processing circuit of the present invention.
FIG. 6 is a memory map in a state where even fields of an interlaced video signal of the video signal processing circuit of the present invention are written.
FIG. 7 is a memory map in which both fields of an interlaced video signal of the video signal processing circuit of the present invention are written.
FIG. 8 is a block diagram showing a configuration example of Embodiment 2 of a video signal processing circuit of the present invention.
FIG. 9 is a block diagram illustrating a configuration example of a video signal processing circuit according to a third embodiment of the present invention.
FIG. 10 is a block diagram illustrating a configuration example of a video signal processing circuit according to a fourth embodiment of the present invention.
FIG. 11 is a block diagram illustrating a configuration example of an apparatus according to a conventional memory control method.
FIG. 12 is a memory map of an apparatus according to a conventional memory control method.
FIG. 13 is a block diagram illustrating a configuration example of an apparatus according to another conventional memory control method.
FIG. 14 is a memory map of an apparatus according to another conventional memory control method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Sync signal separation part, 20, 27 Write signal generation part, 30, 31 Address control basic signal generation part, 40 Horizontal display period signal generation part, 41 Horizontal / vertical display period signal generation part, 50 Vertical display period signal generation part, 60 Address increment control signal generation unit, 70, 80 AND gate, 90, 91 clock selection unit, 100 memory.

Claims (2)

In a video signal processing circuit for writing video data of each line to one memory in order to display an interlace video signal composed of an odd field and an even field in a non-interlace method,
A write signal generator for generating a write clock for writing video data of each line to the memory in dot units;
A horizontal display period signal generator for generating a horizontal display period signal corresponding to the horizontal display period of the video signal;
A vertical display period signal generator for generating a vertical display period signal corresponding to the vertical display period of the video signal;
A write enable signal generating unit that generates a write enable signal for permitting writing of video data of each line of the video signal to the memory in the horizontal display period of the vertical display period from the horizontal display period signal and the vertical display period signal; ,
And address control basic signal generator for generating an address control basic clock which is a clock of a countable period the number of dots for one line within a period not horizontal display period,
When writing the video data of each line in the odd field to the memory , the address control basic clock only during a period in which the number of dots for one line is counted by the address control basic clock every period other than the horizontal display period from a predetermined timing. Is output as an address control clock, and when the video data of each line in an even field is written to the memory, the predetermined timing is switched for a period of one line and the address control clock is output. And
A clock selection unit for selecting a write clock in a horizontal display period and selecting an address control clock in another period and supplying the clock to the memory, and
Said memory, said image data for one line in synchronization with the write clock during the period from the clock selector is write clock is given is stored, 1-line according to an address control clock in a period in which the address control clock is given A video signal processing circuit characterized in that an address for a minute is to be incremented. 2. The video signal processing circuit according to claim 1, wherein the write clock is generated by dividing the address control basic clock .

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