KR100594237B1 - Apparatus and method for converting scanning method - Google Patents

Abstract

Provided are a scan conversion apparatus and a scan conversion method for generating interlaced scan data and sequential scan data in order to simultaneously drive each of the display apparatuses using different scan methods. The scan conversion device includes a first conversion circuit for converting first interlaced scan data into sequential scan data; And a second conversion circuit for converting the sequential scan data into second interlaced scan data, wherein the sequential scan data and the second interlaced scan data are synchronized with each other.

Interlaced, progressive,

Description

Scanning converting apparatus and scanning converting method {Apparatus and method for converting scanning method}

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1A is a diagram for explaining a general interlaced scanning method.

Figure 1b illustrates the general sequential scanning method.

2 shows a block diagram of a scan conversion device according to an embodiment of the present invention.

3 shows an output signal of a scan conversion device according to an embodiment of the present invention.

4A shows a timing diagram of interlaced scanning.

4B shows a timing chart of sequential scanning.

FIG. 5A is a timing diagram of an output signal of the first conversion circuit shown in FIG. 2.

FIG. 5B is a timing diagram for the case where the second conversion circuit shown in FIG. 2 outputs a top field.

5C is a timing diagram for the case where the second conversion circuit shown in FIG. 2 outputs a bottom field.

FIG. 6 shows a first embodiment of the second conversion circuit shown in FIG.

FIG. 7 illustrates an operation timing diagram of the second conversion circuit illustrated in FIG. 6.

FIG. 8 shows a second embodiment of the second conversion circuit shown in FIG.

FIG. 9 illustrates an operation timing diagram of the second conversion circuit illustrated in FIG. 8.

FIG. 10 shows a third embodiment of the second conversion circuit shown in FIG.

The present invention relates to a scan converting apparatus and a scan converting method, and more particularly, a scan converting apparatus which generates interlaced scan data and sequential scan data synchronized with each other to simultaneously drive display devices using different scan methods. And a scanning conversion method.

Common methods used to display images on screen are interlaced scans and progressive scans.

Hereinafter, for convenience of description, a description will be made based on a standard definition (SD) class display device using a national television system committee (NTSC) method. However, this description is not limited to display devices using the NTSC method, and it is natural to apply to all display devices using standard television formats such as PAL (phase alternation by lines) and SECAM (sequential color memories).

1A is a diagram for explaining a general interlaced scanning method. Referring to FIG. 1A, a display apparatus using an interlaced scanning method such as an analog television displays one field every 1/60 second. That is, the analog television scans the TOP FIELD consisting of the odd-numbered scan lines 1, 3, 5, ..., 477, 479 every 1/60 second, and the even-numbered scan lines 2, 4, Inject the BOTTOM FIELD consisting of ..., 478, 480).

One frame consists of a combination of one top field and one batam field. Thus, analog television displays one frame every 1/30 seconds.

1B is a diagram illustrating a general sequential scanning method. Referring to FIG. 1B, a display device using a sequential scanning method such as a computer monitor and a digital television displays one frame every 1/60 second. That is, computer monitors and digital televisions sequentially scan all scan lines 1 to 480 every 1/60 second.

Interlaced and sequential scanning methods are different. Therefore, the display device using the interlaced scanning method cannot display the desired image using the progressive scanning method as it is. In addition, a display device using the progressive scanning method cannot display a desired image using the interlaced scanning method as it is.

Therefore, in order to simultaneously drive each display device using a different scanning method, a video signal for interlaced scanning (hereinafter referred to as interlaced scan data) is a video signal for progressive scanning (hereinafter referred to as sequential scan data). And a device for converting the sequential scan data into the interlaced scan data.

Accordingly, a technical problem of the present invention is to provide a scan conversion device and a scan conversion method for generating interlaced scan data and sequential scan data synchronized with each other to simultaneously drive display devices using different scanning methods. will be.

The scanning conversion apparatus for achieving the technical problem comprises a first conversion circuit for converting the first interlaced scan data into sequential scan data; And a second conversion circuit connected to the first conversion circuit for converting the sequential scan data into second interlaced scan data, wherein the sequential scan data and the second interlaced scan data are synchronized with each other. Preferably, the horizontal synchronization signal for the sequential scan data and the horizontal synchronization signal for the second interlaced scan data are synchronized with each other.

The second conversion circuit includes an address generation circuit for generating a write address and a read address; And a data conversion circuit for storing data corresponding to the write address among the received sequential scan data, or outputting data corresponding to the read address among the stored data as the second interlaced scan data.

The data conversion circuit includes a selection circuit for outputting any one of the write address and the read address in response to an address selection signal; And storing data corresponding to the write address among the sequential scan data received in response to the first edge among the two edges of the address selection signal, and in response to the second edge among the two edges of the address selection signal. And a memory for outputting data corresponding to the read address among the stored data as the second interlaced scanning data.

The scanning method converting method for achieving the technical problem comprises the steps of: receiving first interlaced scan data, converting the received first interlaced scan data into sequential scan data, and outputting the sequential scan data; And receiving the progressive scan data, converting the received progressive scan data into second interlaced scan data, and outputting the second interlaced scan data, wherein the sequential scan data and the second interlaced scan data Synchronized with each other.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 shows a block diagram of a scan conversion circuit according to an embodiment of the present invention. Referring to FIG. 2, the scan conversion apparatus 200 according to the present invention may simultaneously drive a display device (not shown) using an interlaced scanning method and a display device (not shown) using a sequential scanning method.

The scan conversion device 200 includes a first conversion circuit 210 and a second conversion circuit 220. The first conversion circuit 210 receives the interlaced scan data IDATA input to the input terminal 201, converts the received interlaced scan data IDATA into sequential scan data PDATA, and converts the sequential scan data PDATA. ) Is output to the first output terminal 203.

Thus, the first conversion circuit 210 is an interlaced to progressive conversion circuit (IPC). In addition, a display device (not shown) using a sequential scan method may be connected to the first output terminal 203.

The first conversion circuit 210 may be referred to as interlaced data (or 'field data') through conventional methods such as WEAVE, BOB, MA-IPC (Motion adaptive IPC), MC-IPC (Motion compensated IPC), and the like. Converts the sequential scan data (or also referred to as 'frame data') and converts the sequential scan data PDATA to a timing required by a display device using a sequential scan method such as a computer monitor and a digital television; 203).

The second conversion circuit 220 receives the sequential scan data PDATA output from the first conversion circuit 210, converts the received sequential scan data PDATA into interlaced scan data IDATA ', and interlaces the interlaced data. The scan data IDATA 'is outputted to the second output terminal 205 in accordance with the timing required by the display apparatus using a sequential scanning method such as an analog television.

Therefore, the second conversion circuit 220 is a progressive to interlaced conversion circuit (PIC). The display apparatus using the interlaced scanning method may be connected to the second output terminal 205.

That is, the second conversion circuit 220 receives the sequential scan data PDATA, and among the received sequential scan data PDATA, data for constituting any one of the top field and the batam field according to the write address. The data is stored in the memory and data corresponding to the read address is output from the data stored in the memory.

Therefore, the scan conversion apparatus 200 according to the present invention simultaneously outputs the sequential scan data PDATA and the interlaced scan data IDATA 'through the first output terminal 203 and the second output terminal 205.

3 shows an output signal of a scan conversion device according to an embodiment of the present invention. In general, in the SD class using NTSC, one field is composed of 720 × 240 pixels, and one frame is composed of 720 × 480 pixels.

In the memory (not shown) built in the first conversion circuit 210, data for the top field 310, data for the batam field 320, and data for the top field 330 are sequentially stored.

The sequential scan data PDATA 321 at the moment t (i) is composed of a combination of the data of the top field 310 or 330 and the data of the batam field 320. In this case, the top field 310 or 330 is displayed through the odd-numbered scan lines 1, 3, 5, ..., 477, 479 of the sequential scan data PDATA 321, and the batam field 320 is The even-numbered scan lines 2, 4, 6, ..., 478 and 480 of the sequential scan data PDATA 321 are displayed as they are.

The sequential scan data PDATA 311 of the instant t (i-1) and the sequential scan data PDATA 331 of the t (i + 1) instant are also configured in the same manner as the sequential scan data of the t (i) instant. .

The second conversion circuit 220 converts the sequential scan data PDATA into interlaced scan data IDATA 'and outputs the interlaced scan data IDATA'. The second conversion circuit 220 has odd-numbered lines 1, 3, 5,... Among the frame data PDATA at each instant t (i-1), t (i), t (i + 1). Only .., 477, 479 or even-numbered lines 2, 4, 6,..., 478, 480 are selected to form top field 313, 333 or batam field 323.

Here, at the time of t (i-1) and t (i + 1), the top field is composed of the odd-numbered lines of the frame data PDATA, and at the time of t (i), only even-numbered lines of the frame data PDATA are formed. It is preferable to form a batam field by selecting.

For example, the odd horizontal sync signals 1, 3, 5, 477, and 479 for displaying the frame data PDATA on the display device and the odd horizontal sync signals 1 for displaying the top field IDATA 'on the display device. , 3, 5, 477, 479) are synchronized with each other. Therefore, the sequential scan data PDATA output from the first conversion circuit 210 and the interlaced scan data IDATA 'output from the second conversion circuit 220 are synchronized with each other.

4A shows a timing diagram of interlaced scanning. The sampling frequency of FIG. 4A is 13.5 MHz. Referring to FIG. 4A, the vertical synchronizing signal V_SYNC (i) is generated every 1/60 second and 262.5 horizontal synchronizing lines corresponding to 262.5 scan lines during one period Ti of the vertical synchronizing signal V_SYNC (i). There are signals H_SYNC (i). In this case, the active area includes 240 odd scan lines or even scan lines.

One scan line has a horizontal blanking interval (HBI) and video data. That is, the HBI is composed of 138 pixels, and the video data area is composed of 720 pixels.

4B shows a timing chart of sequential scanning. The sampling frequency of FIG. 4B is 27 MHz. Referring to FIG. 4B, the vertical sync signal V_SYNC (p) is generated every 1/60 second, and 525 horizontal lines corresponding to 525 scan lines during one period Tp of the vertical sync signal V_SYNC (p). Synchronization signals H_SYNC (p) exist. In this case, the active area is composed of 480 scan lines.

The active region of FIG. 4A and the active region of FIG. 4B start at the same point that has passed the vertical blanking interval (VBI), and the sequential scanning method scans two scan lines while the interlaced scan method scans one scan line. That is, while the interlaced scanning method sequentially scans 240 odd-numbered scan lines for (1/60) seconds, the sequential scanning method sequentially scans 480 scan lines.

Therefore, the scan conversion circuit 200 according to the present invention can simultaneously output the sequential scan data PDATA and the interlaced scan data IDATA 'synchronized with each other using this ratio relationship.

FIG. 5A is a timing diagram of an output signal of the first conversion circuit shown in FIG. 2. Referring to FIG. 5A, one scan line data outputs 720 data for 720 clocks after passing HBI corresponding to 138 clocks.

FIG. 5B is a timing diagram for the case where the second conversion circuit shown in FIG. 2 outputs a top field. Referring to FIG. 5B, one scan line data outputs 720 data for 1440 clocks after passing the HBI corresponding to 276 clocks.

5C is a timing diagram for the case where the second conversion circuit shown in FIG. 2 outputs a bottom field. Referring to FIG. 5C, one scan line data outputs 720 data for 1440 clocks after passing HBI corresponding to 276 clocks.

For example, when the sampling frequency of FIG. 5A is 27 MHz and the sampling frequency of FIGS. 5B and 5C is 13.5 MHz, the numbers (eg, 138, 276, 720, and 1440) shown in FIGS. 5A to 5C are interlaced scan specifications (eg, NTSC). The timing required by the sequential scanning specification 480P is calculated at the same clock frequency (for example, 27 MHz) to represent the number of clocks in a section corresponding to a line based on interlaced scanning.

Thus, during the same time, interlaced scans output one scan line data and sequential scans output two line scan data.

2, 4B, and 5A, when the first conversion circuit 210 outputs data for 480 scan lines constituting one frame, the second conversion circuit 220 may form a top field. Data for 240 scan lines or data for 240 scan lines are output.

The starting point of the video data of FIGS. 5B and 5C is always later than the starting point of the video data of FIG. 5A. Therefore, the output time of interlaced scan data is always delayed by a predetermined time δ than the output time of sequential scan data. The predetermined time δ is equal to the time of 138 clock signals when using 27 MHz as the sampling frequency.

FIG. 6 shows a first embodiment of the second conversion circuit shown in FIG. Referring to FIG. 6, the second conversion circuit 220 includes an address generation circuit and a data conversion circuit 670.

The address generation circuit generates a write address WA and / or a read address RA, and includes a synchronization signal generation circuit 622, a write address generation circuit 630, and a read address generation circuit 650.

The TV synchronization signal generation circuit 690 generates the field select signal FD_ID, the odd horizontal sync signal ODD_HSYNC, and the even horizontal sync signal EVEN_HSYNC. The synchronization signal generation circuit 622 receives an odd horizontal sync signal ODD_HSYNC and an even horizontal sync signal EVEN_HSYNC.

The odd-numbered horizontal sync signal (ODD_HSYNC) and the even-numbered horizontal sync signal (EVEN_HSYNC) are odd-numbered horizontal sync signals (ODD_HSYNC) and even-numbered horizontal sync signals (EVEN_HSYNC) from a predetermined reference among the horizontal sync signals commonly used in TVs. Means.

When the second conversion circuit 220 generates interlaced scanning data IDATA 'using the TOP field among the sequential scanning data PDATA input, the synchronization signal generating circuit 622 is each odd-numbered horizontal synchronization. It is reset every signal (ODD_HSYNC).

When the second conversion circuit 220 generates interlaced scanning data IDATA 'using the BOTTOM field among the sequential scanning data PDATA input, the synchronization signal generating circuit 622 is horizontal in each even number. It is reset every synchronization signal EVEN_HSYNC.

In the present invention, for convenience of description, only the case where the second conversion circuit 220 is used to make interlaced scanning data IDATA 'using only the top field of the sequential scanning data PDATA is described.

The synchronization signal generation circuit 622 is reset in response to the odd-numbered horizontal synchronization signal ODD_HSYNC, and then is clocked to the first clock signal CLK1 to output the synchronization signal CNT. The synchronization signal generation circuit 622 may be implemented as a counter. Accordingly, the counter 622 outputs a count signal CNT that is clocked by the first clock signal CLK1 and increments by one. The count signal CNT may synchronize the operations of the write address generation circuit 630 and the read address generation circuit 650 with each other.

The write address generation circuit 630 generates the write address WA in response to the field select signal FD_ID and the count signal CNT. The write address generation circuit 630 includes a first comparator 6301, a first subtractor 6303, a second subtractor 6305, a second selection circuit 6307, and a write address generator 6309.

The first comparator 6301 receives the field select signal FD_ID and the count signal CNT, and based on the field select signal FD_ID, the first comparator 6301 receives the count signal CNT and a predetermined signal (for example, 138, 858, and 996). The result of the comparison is output to the second selection circuit 6307.

When the field select signal FD_ID is the top field select signal TOP_ID and the output value CNT of the counter 622 is greater than or equal to 138 and smaller than 858, the first comparator 6301 is configured to determine the value of the second subtractor 6305. A signal for outputting the output signal to the write address generator 6309 is output.

When the field select signal FD_ID is the batam field select signal BT_ID and the output value CNT of the counter 622 is equal to or greater than 996, the first comparator 6301 may output the output signal of the first subtractor 6303. A signal for output to the write address generator 6309 is output. The numbers, 138, 858, and 996 are numbers that are applied when the frequency of the sequential scanning horizontal synchronous signal is 27 MHz in the SD class using NTSC, and may change when the frequency of the horizontal synchronous signal changes. It is a number.

In other cases (ELSE), the first comparator 6301 outputs a signal for outputting 0 to the write address generator 6309.

The first subtractor 6303 receives the counter signal CNT, subtracts a predetermined value (for example, 996) from the received count signal CNT and outputs the result. The second subtractor 6305 receives the counter signal CNT, subtracts a predetermined integer (for example, 138) from the received count signal CNT, and outputs the result.

The write address generator 6309 receives the output signal of the second selection circuit 6307, generates a write address WA in response to the first clock signal CLK1, and converts the generated write address WA into a data conversion circuit. An output is made to the fourth selection circuit 6701 of 670.

The read address generation circuit 650 generates the read address RA in response to the counter signal CNT. The read address generator circuit 650 includes a second comparator 6501, a third subtractor 6503, a third select circuit 6505, and a read address generator 6503.

The second comparator 6501 receives the counter signal CNT, compares the count signal CNT with a predetermined value (for example, 276), and outputs the comparison result to the third selection circuit 6505.

For example, when the output signal CNT of the counter 620 is equal to or larger than 276, the second comparator 6501 outputs a signal for outputting the output signal of the third subtractor 6503 to the read address generator 6503. . In other cases (ELSE), the second comparator 6501 outputs 0 (or a logic low) to the third selection circuit 6505.

The third subtractor 6503 subtracts 276 from the output signal CNT of the counter 620, divides the result by two, and outputs the divided result.

The read address generator 6503 receives the output signal of the third selection circuit 6505, generates a read address RA in response to the second clock signal CLK2, and converts the generated read address RA into data. An output is made to the fourth selection circuit 6701 of the circuit 670.

The data conversion circuit 670 receives the progressive scan data PDATA and stores data corresponding to the write address WA in the received progressive scan data PDATA, or stores the data corresponding to the write address WA to the read address RA among the stored progressive scan data. The corresponding data is output as interlaced data IDATA '.

The data conversion circuit 670 includes a fourth selection circuit 6701 and a memory (or also referred to as a buffer) 6703. The fourth select circuit 6701 outputs the write address WA to the memory 6703 in response to any edge (e.g., rising edge) of the address select signal WR, and the other of the address select signal WR. The read address RA is output to the memory 6703 in response to the edge of (e.g., the falling edge).

The memory 6703 stores data corresponding to the write address WA among the sequential scan data PDATA received in response to the rising edge of the address selection signal WR, and responds to the falling edge of the address selection signal WR. The data corresponding to the read address RA among the data stored in the memory 6703 is output as interlaced scanning data IDATA '.

FIG. 7 illustrates operation timings of the second conversion circuit shown in FIG. 6. An operation of the second conversion circuit 220 will be described with reference to FIGS. 6 and 7 as follows. P in parentheses of each signal shown in FIG. 7 denotes signals used for sequential scanning, and i denotes a signal used for interlaced scanning.

First, when the field select signal FD_ID is the top field select signal TOP_ID, the counter 622 is reset (i.e., zero) in response to the odd-numbered horizontal sync signal ODD_HSYNC, and then the first clock signal ( The count starts in response to CLK1).

The comparator 6301 receives the top field select signal TOP_ID and the count signal CNT 0 to 1715, compares the received count signal CNT 0 to 1715 with a predetermined value (for example, 138 or 858). The signal generated as a result of the comparison is output to the second selection circuit 6307.

If the count signal (CNT) 0 to 1715 is greater than or equal to 138 and smaller than 858, the comparator 6301 is configured to output the output signals 0 to 719 of the subtractor 6305 to the write address generator 6309. The signal is output to the selection circuit 6307.

Therefore, since the selection circuit 6307 outputs the output signals 0 to 719 of the subtractor 6305 to the write address generator 6309, the write address generator 6309 responds to the first clock signal CLK1 in response to the first address signal CLK1. WA; 0 to 719).

The selection circuit 6701 transmits a write address WA (0 to 719) input to the first input terminal 1 to the memory 6703 in response to the rising edge of the address selection signal WR.

Therefore, the memory 6703 receives the sequential scan data PDATA in response to the rising edge of the address selection signal WR, and stores data corresponding to the write addresses WA 0 to 719 among the received sequential scan data PDATA. Can be stored.

The comparator 6501 also receives a count signal CNT (0 to 1715), compares the received count signal (CNT) 0 to 1715 with a predetermined value (for example, 276), and outputs the comparison result.

If the count signal CNT is equal to or greater than 276, the comparator 6501 may output a signal for outputting the output signals 0 to 719.5 of the subtractor 6503 to the read address generator 6503. Will output

In other cases (e.g., when the count signal CNT is less than 276), the selection circuit 6505 outputs a signal (e.g., 0) input to the input terminal 0 to the read address generator 6503.

The selection circuit 6505 outputs the output signals 0 to 719.5 of the subtractor 6503 input to the input terminal 1 to the write address generator 6309, so that the read address generator 6503 is the second clock signal CLK2. A read address (0 to 719) is generated in response to the rising edge of.

Here, the frequency of the second clock signal CLK2 is preferably equal to or greater than the sum of the sampling frequency (for example, 27 MHz) for sequential scanning and the sampling frequency (for example, 13.5 MHz) for interlaced scanning (for example, 40.5 MHz).

When the count signal CNT is equal to or greater than 276, the selection circuit 6701 reads out the read address RA inputted to the second input terminal 0 in response to the falling edge of the address selection signal WR. Is output to the memory 6703.

Therefore, the memory 6703 stores the data corresponding to the read addresses 0 to 719 among the sequential scan data PDATA stored in the memory 6703 in response to the falling edge of the address selection signal WR. Can be output as

When the field selection signal FD_ID is the batam field selection signal BT_ID, the comparator 6301 receives the batam field selection signal BT_ID and the counter signals CNTs 0 to 1715 and receives the count signal CNTs 0 to 1715 are compared with a predetermined value (for example, 996), and a signal generated as a result of the comparison is output.

If the count signal CNT is equal to or greater than 996, the comparator 6301 outputs a signal for outputting the output signals 0 to 719 of the subtractor 6303 to the write address generator 6309. Will output

Since the selection circuit 6307 outputs the output signals 0 to 719 of the subtractor 6303 inputted to the input terminal 2 to the write address generator 6309, the write address generator 6309 receives the first clock signal CLK1. In response to this, a write address WA 0 to 719 is generated.

At this time, the selection circuit 6701 outputs a write address WA (0 to 719) input to the first input terminal 1 to the memory 6703 in response to the rising edge of the address selection signal WR.

Therefore, the memory 6703 receives the sequential scan data PDATA in response to the rising edge of the address selection signal WR and stores data corresponding to the write addresses 0 to 719 among the received sequential scan data PDATA. Can be.

When the count signal CNT is equal to or greater than 276, the comparator 6501 may output a signal for outputting the output signals 0 to 719.5 of the subtractor 6503 to the read address generator 6503. Will output

In other cases (e.g., when the count signal CNT is less than 276), the selection circuit 6505 outputs a signal (e.g., 0) input to the input terminal 0 to the read address generator 6503.

When the count signal CNT is equal to or greater than 276, the selection circuit 6505 outputs the output signals 0 to 719.5 of the subtractor 6503 to the write address generator 6309, so that the read address generator 6503 is set to the first. The read addresses 0 to 719 are generated in response to the two clock signals CLK2.

In this case, the selection circuit 6701 outputs a read address RA (0 to 719) input to the second input terminal 0 to the memory 6703 in response to the falling edge of the address selection signal WR.

Therefore, the memory 6703 may output data corresponding to the read addresses 0 to 719 among the sequential scan data PDATA stored in the memory 6703 in response to the falling edge of the address selection signal WR.

The memory 6703 can write the sequential scan data PDATA in response to the falling edge of the address selection signal WR, and read the sequential scan data PDATA in response to the rising edge of the address selection signal WR. Can be.

FIG. 8 shows a second embodiment of the second conversion circuit shown in FIG. Referring to FIG. 8, the second conversion circuit 220 may include a timing signal generation circuit, a write address generation circuit 630, a read address generation circuit 650, a data conversion circuit 670, and a TV synchronous signal generation circuit 690. ). The timing signal generation circuit 701 includes a selection circuit 610 and a synchronization signal generation circuit 621. The selection circuit 610 may be implemented as a MUX, and the synchronization signal generation circuit 621 may be implemented as a counter.

FIG. 9 illustrates an operation timing diagram of the second conversion circuit illustrated in FIG. 8. An operation of the second conversion circuit 220 will be described with reference to FIGS. 8 and 9 as follows.

First, when the field select signal FD_ID is the top field select signal TOP_ID, the MUX 610 outputs only the odd-numbered synchronization signal ODD_HSYNC to the counter 621. Accordingly, the counter 621 is reset in response to the falling edge of the odd-numbered horizontal synchronization signal ODD_HSYNC (ie, zero), and starts counting in response to the first clock signal CLK1.

The comparator 6301a receives a counter signal CNT (0 to 1715), compares the received count signal (CNT) 0 to 1715 with a predetermined value (for example, 138 or 858), and generates the signal as a result of the comparison. Outputs

If the count signal CNT is greater than or equal to 138 and smaller than 858, the comparator 6301a outputs a signal for outputting the output signals 0 to 719 of the subtractor 6305 to the write address generator 6309. Output to (6307a). In other cases, the selection circuit 6307a outputs a signal (for example, 0) input to the input terminal 0 to the write address generator 6309.

When the count signal CNT is greater than or equal to 138 and smaller than 858, the selection circuit 6307a outputs the output signals 0 to 719 of the subtractor 6305 to the write address generator 6309, and thus the write address generator 6309. ) Generates a write address WA 0 to 719 in response to the first clock signal CLK1.

At this time, the selection circuit 6701 receives a write address WA (0 to 719) input to the first input terminal 1 in response to one of the two edges (for example, the rising edge) of the address selection signal WR. Transfer to memory 6703.

Therefore, the memory 6703 receives the sequential scan data PDATA in response to the rising edge of the address selection signal WR, and stores data corresponding to the write addresses 0 to 719 among the received sequential scan data PDATA. Can be.

In addition, the comparator 6501a receives the counter signals CNT 0 to 1715, compares the received count signals CNT 0 to 1715 with a predetermined value (for example, 276), and outputs the comparison result.

If the count signal CNT is equal to or larger than 276, the comparator 6501a outputs a signal for outputting the output signals 0 to 719.5 of the subtractor 6503 to the read address generator 6503. Will output In other cases (e.g., when the count signal CNT is less than 276), the selection circuit 6505 outputs a signal (e.g., 0) input to the input terminal 0 to the read address generator 6503.

Therefore, since the selection circuit 6505 outputs the output signals 0 to 719.5 of the subtractor 6503 to the write address generator 6309, the read address generator 6501 reads the read address (in response to the second clock signal CLK2). 0 to 719).

In this case, the selection circuit 6701 transmits a read address RA (0 to 719) input to the second input terminal 0 to the memory 6703 in response to the falling edge of the address selection signal WR.

 Therefore, the memory 6703 stores the data corresponding to the read addresses 0 to 719 among the sequential scan data PDATA stored in the memory 6703 in response to the falling edge of the address selection signal WR. Can be output as

The memory 6703 can write the sequential scan data PDATA in response to the rising edge of the address selection signal WR, and read the sequential scan data PDATA in response to the falling edge of the address selection signal WR. You may.

FIG. 10 shows a third embodiment of the second conversion circuit shown in FIG. The structure of the second conversion circuit 220 shown in FIG. 10 and the structure of the second conversion circuit shown in FIG. 6 are identical except for the selection circuit 610 and the counter 6620. Therefore, a detailed description of the operation of the second conversion circuit 220 shown in FIG. 10 will be omitted.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the scan conversion circuit and the scan conversion method according to the present invention have the effect of simultaneously driving displays using different scan methods.

Claims (27)

In the scanning converter, A first conversion circuit for converting the first interlaced scan data into sequential scan data; And A second conversion circuit connected to said first conversion circuit for converting said sequential scan data into second interlaced scan data, And the sequential scan data output from the first conversion circuit and the second interlaced scan data output from the second conversion circuit are output in synchronization with each other. The scan conversion apparatus according to claim 1, wherein the first conversion circuit converts the first interlaced scan data into the sequential scan data by using any one of BOB and WEAVE. The scan conversion apparatus according to claim 1, wherein the horizontal synchronization signal for the sequential scan data and the horizontal synchronization signal for the second interlaced scan data are synchronized with each other. The method of claim 1, wherein the second conversion circuit, An address generating circuit for generating a write address and a read address; And And a memory for storing data corresponding to the write address among received sequential scan data, or outputting data corresponding to the read address among the stored sequential scan data as the second interlaced scanning data. Device. The scan conversion apparatus according to claim 4, wherein the second conversion circuit further comprises a selection circuit for outputting any one of the write address and the read address in response to an address selection signal. The second interlaced scan according to claim 5, wherein the selection circuit scans the second data corresponding to the read address from among the stored data while the first data corresponding to the write address is stored among the received sequential scan data. A scanning converter, which outputs as data. The method of claim 5, wherein the memory, Storing data corresponding to the write address among sequential scan data received in response to a first edge among two edges of the address selection signal, and responsive to a second edge among two edges of the address selection signal And the data corresponding to the read address among the stored data is output as the second interlaced scanning data. The method of claim 1, wherein the second conversion circuit, A counter for generating a count signal; A write address generation circuit for generating a write address in response to a field selection signal and the count signal; A read address generating circuit for generating a read address in response to the count signal; And And a memory for storing data corresponding to the write address among the received sequential scan data, and outputting data corresponding to the read address among the stored sequential scan data as the second interlaced data. . The method of claim 8, wherein the second conversion circuit, And a selection circuit for outputting any one of the write address and the read address in response to an address selection signal. The method of claim 1, wherein the second conversion circuit, A selection circuit for outputting an odd synchronization signal or an even synchronization signal in response to the field selection signal; A counter which resets in response to an output signal of the selection circuit and generates a count signal based on a first clock signal; A write address generation circuit for generating a write address in response to a field select signal and the count signal; A read address generating circuit for generating a read address in response to the count signal; And And a memory configured to store data corresponding to the write address among received sequential scan data, and to output data corresponding to the read address among the stored data as the second interlaced data. The method of claim 10, wherein the second conversion circuit, And a selection circuit for outputting any one of the write address and the read address in response to an address selection signal. The circuit of claim 8, wherein the write address generation circuit comprises: A first comparator for comparing the count signal with a predetermined value based on the field selection signal and generating a first selection signal as a result of the comparison; A first subtractor which subtracts a predetermined value from the count signal and outputs a result; A second subtractor which subtracts a predetermined value from the count signal and outputs a result; A first selection circuit outputting an output signal of the first subtractor or an output signal of the second subtractor in response to the first selection signal; And And a write address generator for receiving the output signal of said first selection circuit and clocked to said first clock signal to generate a write address. The circuit of claim 12, wherein the read address generating circuit comprises: A second comparator for comparing the count signal with a predetermined value and generating a second selection signal according to the comparison result; A third subtractor for subtracting a predetermined value from the count signal and generating a result; A second selection circuit outputting an output signal of the third subtractor or a ground voltage in response to the second selection signal; And And a read address generator for receiving the output signal of the second selection circuit and clocked to the second clock signal to generate a read address. The circuit of claim 8, wherein the write address generation circuit comprises: A first comparator for comparing the count signal with a predetermined value and generating a first selection signal as a result of the comparison; A first subtractor which subtracts a predetermined value from the count signal and outputs a result; A first selection circuit outputting an output signal of the first subtractor or an output signal of the first subtractor in response to the first selection signal; And And a write address generator for receiving the output signal of said first selection circuit and clocked to said first clock signal to generate a write address. 15. The system of claim 14, wherein the read address generating circuit comprises: A second comparator for comparing the count signal with a predetermined value and generating a second selection signal according to the comparison result; A second subtractor which subtracts a predetermined value from the count signal and generates a result; A second selection circuit outputting an output signal of the second subtractor or a ground voltage in response to the second selection signal; And And a read address generator for receiving the output signal of the second selection circuit and clocked to the second clock signal to generate a read address. An apparatus for converting progressive scan data into interlaced data, A write address generation circuit for generating a write address for storing the received sequential scan data in a memory; And A read address generation circuit for generating a read address for outputting the sequential scan data stored in the memory as the interlaced scan data, The memory, Storing data corresponding to the write address among the received progressive scan data, and outputting data corresponding to the read address among the stored progressive scanning data as the interlaced scanning data, And the sequential scan data and the interlaced scan data are synchronized with each other. The apparatus of claim 16, wherein the apparatus for converting the progressive scan data into the interlaced scan data comprises: And a selection circuit for outputting one of the write address and the read address in response to an address selection signal. The method of claim 17, wherein the memory, Storing data corresponding to the write address among the sequential scan data received in response to the first edge among the two edges of the address selection signal, and responding to the second edge among the two edges of the address selection signal. And convert the sequential scan data into interlaced data by outputting data corresponding to the read address from the stored data as the interlaced scan data. In the scanning converter, A first conversion circuit for converting input field data into frame data; And A second conversion circuit for receiving the frame data and outputting any one of field data for constructing a top field and field data for constructing a batam field among the received frame data, And the frame data output by the first conversion circuit and the field data output by the second conversion circuit are output in synchronization with each other. The method of claim 19, wherein the second conversion circuit, An address generating circuit for generating a write address and a read address; And And a data conversion circuit for storing data corresponding to the write address among received frame data or outputting frame data corresponding to the read address among the stored frame data as the field data. The method of claim 20, wherein the data conversion circuit, A selection circuit outputting the write address or the read address in response to an address selection signal; And Frame data corresponding to the write address is stored among frame data received in response to a first edge among the two edges of the address selection signal, or the stored frame in response to a second edge among the two edges of the address selection signal. And a memory for outputting, as the field data, frame data corresponding to the read address from among the data. In the scanning method conversion method, Receiving first interlaced data, converting the received interlaced data into progressive scan data, and outputting the progressive scan data; And Receiving the progressive scan data, converting the received progressive scan data into second interlaced scan data, and outputting the second interlaced scan data, And the sequential scan data and the second interlaced scan data are output in synchronization with each other. The method of claim 22, wherein the sequential scan data and the second interlaced scan data are synchronized with each other. The method of claim 22, wherein the outputting of the second interlaced scanning data comprises: Generating a write address and a read address; And And storing the data corresponding to the write address among the received sequential scan data and outputting the sequential data corresponding to the read address among the stored sequential data as the second interlaced scanning data. Way. The method of claim 22, wherein the outputting of the second interlaced scan data comprises: Generating a count signal; Generating a write address in response to a field select signal and the count signal; Generating a read address in response to the count signal; And Storing the sequential scan data corresponding to the write address among the received sequential scan data, and outputting the data corresponding to the read address among the stored sequential scan data as the second interlaced data. How to convert. In the scanning method conversion method, Converting input field data into frame data and outputting the frame data; And Receiving the frame data and outputting field data for constructing a top field or field data for constructing a batam field among the received frame data, And the field data output by the outputting of the frame data and the field data are output in synchronization with each other. The method of claim 26, wherein outputting the field data comprises: Generating a write address and a read address; And And storing the data corresponding to the write address among the received frame data, or outputting the data corresponding to the read address among the stored data as the field data.

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