JP3573784B2 - Video signal processing device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a video signal processing device for converting an analog video signal into a digital signal and performing predetermined video signal processing.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the increase in the number of functions of television, not only video signals of the National Television Committee (NTSC) system and the like, but also computer video signals of the VGA standard (640 × 480 pixels) and the like. Also, it has been proposed to display a video signal such as a high definition video on the same display.
[0003]
Since these video signals have different standards, they have different frequencies and the like. Therefore, in order to display these video signals on the same display, a video signal processing device is provided in the display device or the computer main body, and analog video signals are digitized to perform predetermined video signal processing such as frequency conversion. Needed.
[0004]
Further, when performing predetermined signal processing such as frequency conversion using a peripheral device such as a memory, serial data is converted into parallel data and parallel operation is performed. This is because the frequency of the pixel clock such as a computer video signal (for example, 30 MHZ) is higher than the processing speed of the memory, and the processing of the memory cannot keep up with the state of serial data.
[0005]
Hereinafter, an example of the video signal processing device will be described with reference to FIG.
[0006]
The clock generation unit constituted by the PLL 42 and the signal processing unit 16 are formed in an internal circuit of the same IC 10, and are controlled by a CPU (not shown) or the like.
[0007]
Then, based on the horizontal synchronizing signal (104), the PLL 42 generates a sampling clock (406) as shown in FIG. 8A corresponding to the number of pixels on one horizontal scanning line.
[0008]
The input analog video signal (102) is, for example, a video signal of the NTSC system, a video signal of a computer such as the VGA standard, or a video signal of a high-definition television. It is. In the case of color display, the analog video signal (102) has signals for each color of RGB, but is omitted here for simplification of description.
[0009]
The analog-to-digital (A / D) converter 14 samples the input serial analog video signal (102) based on a sampling clock (406) and outputs a serial digital video signal (110) corresponding to each pixel. Convert to Then, the serial digital video signal (110) is sequentially output to the signal processing unit 16.
[0010]
The programmable clock buffer 44 is a circuit formed of, for example, a predetermined number n (n = 4 in this embodiment) bit counter and formed outside the IC 10. The clock buffer 44 divides the frequency of the sampling clock by n, and a plurality of parallel conversion clocks (408) having different phases as shown in clocks 408-1 to 408-4 in FIGS. 8B to 8E. To occur. Then, this parallel conversion clock (408) is supplied to each memory 46.
The serial digital video signal (110) output to the signal processing unit 16 is sampled based on each parallel conversion clock (408) and stored in each memory 46 as a parallel digital video signal (412).
[0011]
The signal processing section 16 reads out the parallel digital video signals (412) stored in the memory 46 and performs predetermined signal processing as described later.
[0012]
The digital video signal that has been subjected to the signal processing is output to a digital / analog (D / A) conversion unit 18, which converts the digital video signal into an analog video signal (414) again and receives a CRT image. Output to a pipe or the like.
[0013]
Note that the memory 46, the A / D converter 14, and the D / A converter 18 are configured by peripheral devices provided outside the IC 10 similarly to the clock buffer 44.
[0014]
The signal processing performed by the signal processing unit 16 varies depending on the input video signal (102), the video displayed on the display, and the like.
[0015]
For example, when the input video signal (102) is a computer video signal, its horizontal frequency is about 30 kHz when the number of pixels is 640 × 480 (VGA), and the number of frames per second is 60. When the display is a television receiver that displays an NTSC video signal in a raster scan, the horizontal frequency of the video signal is about 15 kHz and the number of frames per second is 30.
[0016]
Therefore, in this case, the signal processing unit 16 needs to perform time axis conversion to convert the horizontal frequency of the computer video signal to the same as the horizontal frequency of the NTSC video signal.
[0017]
In the time axis conversion process, the signal processing unit 16 reads out the video signal stored in each memory 46 and sequentially outputs the video signal to the digital / analog (D / A) conversion unit 18 at the frequency of the pixel clock of the NTSC system. Further, the D / A converter 18 converts the digital video signal into an analog video signal (414) again and outputs this to a picture tube (in the case of a CRT display) or the like.
[0018]
Further, if the time axis conversion is simply performed, the displayed video may not be smooth, and flickers may occur on the display. Then, in order to prevent the flicker, the signal processor 16 performs the following correlation processing (filtering processing) and the like.
[0019]
For example, three data of adjacent pixels on the same vertical scanning line of the display are read from each memory 46. Then, correlation processing such as predetermined weighting and averaging is performed on the three data to generate data for one pixel. When the correlation processing is completed, the signal processing section 16 reads out the processed data, sequentially outputs the processed data to the D / A conversion section 18 at the frequency of the pixel clock of the NTSC system, and converts this into an analog video signal (414).
[0020]
By performing such a correlation process, it is possible to improve the display quality of the video on which the time axis conversion has been performed.
[0021]
[Problems to be solved by the invention]
However, in the conventional video signal processing device, although the PLL 42 and the signal processing unit 16 are formed in the same IC circuit, the clock buffer 44 for dividing the frequency of the sampling clock (406) is provided outside the IC 10. Was provided as a separate circuit.
[0022]
In general, when the sampling clock (406) is divided to generate each parallel conversion clock (408), a predetermined time delay t occurs with respect to the sampling clock (406).
[0023]
However, if the clock buffer 44 is an external circuit of the IC 10, it is not easy to grasp the amount of the time delay t, and the system design is complicated.
[0024]
If the time delay t is not eliminated, there is a possibility that a sampling error occurs when the serial digital video signal (110) is sampled based on the parallel conversion clock (408).
[0025]
Further, by using the clock buffer 44 as an external circuit of the IC 10, miniaturization of the system is prevented.
[0026]
The order of generation of the parallel conversion clocks (408-1) to (408-4) shown in FIGS. 8B to 8E is irrelevant to the number of pixels on one horizontal scanning line. The digital video signal sampled based on (408-1) to (408-4) and stored in each memory 46 is simply converted in parallel.
[0027]
Therefore, for example, the relationship between the data of each pixel in raster scan display and the data stored in each memory 46 is as shown in FIG. In the figure, the data stored in the first memory by the clock 408-1 is ○, the data stored in the second memory by the clock 408-2 is □, and the data is stored in the third memory by the clock 408-3. Data is indicated by ●, and data stored in the fourth memory by the clock 408-4 is indicated by a black square.
[0028]
As is clear from FIG. 8, the data stored in each memory 46 is not always the data of the pixels (pixels arranged in the vertical direction) located on the same vertical line on the screen of the display.
[0029]
Therefore, for example, even when video signals between adjacent horizontal scanning lines have a strong correlation in the serial data, it is difficult to maintain this correlation in the parallel data stored in each memory 46.
[0030]
Further, in the correlation processing performed between the data corresponding to the same vertical line in the signal processing unit 16, it is necessary to access all the memories 46, so that there is a problem that the speeding up of the image processing is hindered.
[0031]
The present invention has been made to solve these problems, and an object of the present invention is to provide a video signal processing device capable of performing highly accurate video signal processing with a simple device configuration.
[0032]
[Means to solve the problem]
In order to achieve the above object, a video signal processing device according to the present invention has the following features.
[0033]
In the present invention, for displaying an image on a display, First frequency Analog video signals into digital signals and perform predetermined signal processing. Output as an analog signal of the second frequency In the video signal processing device, a sampling clock is generated based on a horizontal synchronization signal, and the frequency of the sampling clock is further divided. The frequency is low according to the dividing ratio, Clock generating means for generating a plurality of parallel conversion clocks having different phases from each other, and analog / digital for sampling a serial analog video signal based on the sampling clock output from the clock generating means and converting the serial analog video signal into a digital video signal Conversion means, and the digital video signal Several different phases Clock for parallel conversion Are used repeatedly in a predetermined order. Sampling and converting to parallel digital video signal Stored in the memory means and stored parallel of Digital video signal Performs a correlation process on signals of adjacent pixels on the same vertical scanning line in the above, performs a signal process of adjusting a readout timing and performing a time axis conversion, and responds to a pixel clock corresponding to an analog signal of a second frequency. Output as a digital signal for each pixel Signal processing means; Per pixel Digital video signal Of the second frequency Digital-to-analog conversion means for converting into an analog video signal.
[0034]
In the signal processing means, when the signal is converted into a parallel digital video signal, the signals have different phases from each other. Plurality of clocks for parallel conversion Order of using Is reset in synchronization with the horizontal synchronization signal. Then, in each horizontal scan line, the conversion is started using the parallel conversion clock of the same phase among the plurality of parallel conversion clocks, and the parallel digital video signals of the adjacent pixels on the same vertical scan line are converted to the same. Characterized in that the phase is obtained using a clock for parallel conversion. I do.
[0035]
Further, the apparatus has a plurality of memory means for storing the parallel digital video signals in correspondence with the plurality of parallel conversion clocks, respectively, and the digital video signals stored in the plurality of memory means respectively are displayed on a screen of a display. In the above, Predetermined It is a signal related to each pixel on a vertical line.
[0036]
[Action]
According to the present invention, the time delay between the sampling clock and the parallel conversion clock can be easily reduced by generating the sampling clock and the parallel conversion clock by the same clock generation unit.
[0037]
If the frequency division of the sampling clock is performed in a circuit of a peripheral device different from the sampling clock generator, it is difficult to grasp the amount of time delay of the generated parallel conversion clock with respect to the sampling clock. However, in the present invention, since two clocks are generated by an internal circuit such as an IC, it is easy to grasp the time delay amount, and it is also easy to delay and output the sampling clock by the time delay amount. .
[0038]
Therefore, conversion of serial data into parallel data based on the parallel conversion clock can be performed very accurately. It should be noted that n memories can be operated at a low speed of 1 / n of the sampling frequency by n parallel conversion clocks obtained by dividing the sampling clock by n, and a video signal having a high pixel clock frequency can be used. Even if there is, predetermined video signal processing can be reliably performed.
[0039]
Further, the generation order of the plurality of parallel conversion clocks is reset in synchronization with the horizontal synchronization pulse. Thereby, the video signal of the pixel related to the same vertical line of the display can be sampled by one parallel conversion clock.
[0040]
Further, each memory stores video signals on the same vertical line.
[0041]
Therefore, for example, when performing a correlation process on video signals of vertically adjacent pixels on the same vertical line, data may be read from the same memory, and the process can be performed without accessing a plurality of memories. Thereby, the access time of the memory is shortened, and the speed of the image processing can be increased. Therefore, it is possible to reliably perform video signal processing on a computer video signal having a high pixel clock frequency, a high-definition video signal such as a high-definition video signal, etc., and further contribute to simplification of the device configuration.
[0042]
【Example】
An embodiment of the present invention will be described below with reference to the drawings.
[0043]
FIG. 1 is a schematic diagram illustrating a video signal processing device according to an embodiment of the present invention. In addition, the same reference numerals are given to the same portions as those already described, and the description is omitted.
[0044]
The input video signal (102) is a video signal of the NTSC system, a video signal of a computer of the VGA standard or the like, or a video signal of a high-definition television or the like. Signal.
[0045]
The clock generation unit 12 is a circuit formed together with the signal processing unit 16 in an internal circuit of the IC 10 provided in, for example, a display device or a computer main body. The clock generator 12 includes a PLL described later and a 1 / n frequency divider.
[0046]
The PLL section is an oscillation circuit that generates a sampling clock (106) based on the horizontal synchronization signal (104). On the other hand, the 1 / n frequency divider is a circuit that divides the sampling clock (106) by n (n = 4 in this embodiment) to generate n parallel conversion clocks having different phases from each other (FIG. 5 (c) to (f)).
[0047]
The A / D converter 14 samples the input serial analog video signal (102) based on the sampling clock (106) supplied from the clock generator 12, and converts it into a serial digital video signal (110). I do. Then, the digital video signal (110) is sequentially output to the signal processing unit 16.
[0048]
The n (n = 4) memories 20 are storage elements such as DRAMs, FIFO memories, and VRAMs provided outside the IC 10, and supplied with four parallel conversion clocks (108) from the clock generator 12. Have been. The memory 20 samples the serial digital video signal (110) based on the parallel conversion clock (108) and stores the obtained parallel digital video signal (112).
[0049]
The signal processing unit 16 is a circuit that reads out the digital video signal (112) stored in the memory 20 and performs predetermined video signal processing based on the input video signal (102). The data is stored in a line memory provided in the memory 16 and output to the D / A converter 18.
[0050]
The D / A conversion unit 18 is a conversion unit provided outside the IC 10 and converts a digital video signal output from the signal processing unit 16 into an analog video signal (114) and sends it out.
[0051]
Next, the configuration of the clock generator 12 will be described with reference to FIG.
[0052]
The clock generation unit 12 includes a PLL unit that generates a sampling clock (106 ') formed in the internal circuit of the same IC, and 1 / n (n = 4 in this embodiment) that generates a parallel conversion clock (108). And (2) a frequency divider 32.
[0053]
The PLL unit includes a phase comparison unit 22, a voltage controlled oscillator (VCO) 26, and a loop filter 28 inserted in a path from the phase comparison unit 22 to the VCO 26. Further, a frequency divider (the number of 1 / 1H pixels) 24 is provided in a path from the VCO 26 to the phase comparator 22.
[0054]
The frequency divider 24 divides a signal of a predetermined frequency output from the VCO 26 in accordance with the number of pixels in one horizontal scanning line, and supplies a signal of a frequency substantially equal to the horizontal synchronization signal to the phase comparator 22.
[0055]
The phase comparator 22 compares the phase of the signal output from the frequency divider 24 with the phase of the horizontal synchronization signal, and generates an error signal. The error signal is output to the VCO 26 via the loop filter 28.
[0056]
The VCO 26 is an oscillating unit that changes the transmission frequency in accordance with the error signal. The signal finally output from the VCO 26 as the sampling clock (106 ') shown in FIG. The frequency is exactly the same as the number of 1H pixels.
[0057]
The 1 / n frequency dividing section 32 and the delay section 30 are connected to the output side of the VCO 26, respectively. The delay unit 30 is a circuit for delaying the sampling clock (106 ') by a predetermined amount. The amount of delay corresponds to the time delay of the parallel conversion clock (108) generated when the 1 / n frequency divider 32 divides the frequency of the sampling clock (106 ').
[0058]
Since the PLL section and the 1 / n frequency dividing section 32 are formed in the same IC as described above, it is extremely easy to grasp the amount of time delay.
[0059]
Therefore, the configuration of the delay unit 30 for correcting the delay amount of the sampling clock (106 ') is simple, and the delay between the sampling clock (106) supplied to the A / D conversion unit 14 and each of the parallel conversion clocks (108). It is possible to prevent a time delay from occurring. Thus, the sampling of the video signal at the time of the analog-to-digital conversion and the serial-to-parallel conversion can be accurately performed.
[0060]
Next, a configuration example of the 1 / n frequency dividing unit 32 will be described with reference to FIG.
[0061]
The 1 / n frequency dividing unit 32 includes two-stage flip-flops 34 (FF1) and 36 (FF2) and a number (n = 4) of gates 38-1 to 38-4 corresponding to the frequency dividing number n. Have been.
[0062]
Here, the configuration of the 1 / n frequency dividing section 32 is not limited to that shown in FIG. 3, and the frequency dividing number n is set to an optimum value according to the operation speed of a memory or the like. The frequency division number n is equal to the number of generated parallel conversion clocks (108) and the number of memories 20.
[0063]
The sampling clock (106 ') output from the VCO 26 as shown in FIG. 4A is supplied to the CLK input terminal of the FF1.
[0064]
The inverted Q output terminal of the FF1 is connected to the D input terminal of the FF1. Therefore, the Q output of the FF1 is inverted every time the pulse of the sampling clock (106 ') rises, and the Q output terminal of the FF1 doubles the sampling clock (106') as shown in FIG. Is output.
[0065]
The inverted Q output terminal of FF1 is connected to the CLK input terminal of FF2. Then, a pulse obtained by inverting the output signal from the Q output terminal of the FF1 as shown in FIG. 4C is output from the inverted Q output terminal of the FF1.
[0066]
The inverted Q output terminal of FF2 is connected to the D input terminal of FF2. As a result, the Q output of FF2 is inverted each time the pulse of the inverted Q output of FF1 rises. Therefore, as shown in FIG. 4D, the Q output terminal of FF2 is delayed by one clock from the inverted Q output of FF1. A rising pulse is output.
[0067]
The Q output terminals of FF1 and FF2 are connected to the input terminals of the gates 38-1 to 38-4, respectively. In the present embodiment, two inputs of the gate 38-1 are both inverted inputs, and only one of the inputs of the gates 38-2 and 38-3 is an inverted input.
[0068]
Then, from each of the gates 38-1 to 38-4, as shown in (c) to (f) of FIG. Clocks for parallel conversion (108-1 to 4) are output. In the figure, the positive pulse width of each of the parallel conversion clocks (108-1 to 108-4) is illustrated in the same manner as the pulse width of the sampling clock (106 '). However, the pulse width is not limited to this and may be a pulse having a duty of 50%. .
[0069]
Further, a horizontal synchronizing signal (104) shown in FIG. 4B is supplied as a reset signal to the R input terminals of the FF1 and FF2, and when this reset signal is input, the Q output terminals of the FF1 and FF2 output the respective signals. Is initialized. Then, the order in which the parallel conversion clocks (108-1 to 108-4) are generated is reset.
[0070]
That is, as shown in FIGS. 5C to 5F, the respective parallel conversion clocks 108-1 to 108-4 are clock 108-1 → clock 108-2 → clock 108-3 → clock 108-4 → A pulse is generated in the order of clock 108-1.
[0071]
In this state, when a horizontal synchronizing signal (104) generated every one horizontal scanning period is supplied as a reset signal to the R input terminals of FF1 and FF2, the order of generation of each of the parallel conversion clocks (108-1 to 4). Is reset. At the same time as the reset, the pulse of the parallel conversion clock (108-1) rises.
[0072]
As described above, by resetting the generation order of the parallel conversion clocks (108-1 to 108-4) by the horizontal synchronization signal (104), the generation order becomes the same during each horizontal scanning period.
[0073]
Then, the serial digital video signal (110) of FIG. 1 is sampled based on the parallel conversion clocks (108-1 to -4), converted into parallel data, and stored in the memories 20.
[0074]
FIG. 6 shows the relationship between the data of each pixel in raster scan display and the data stored in each memory 20.
[0075]
In the figure, data stored in the first memory by the clock 108-1 is ○, data stored in the second memory by the clock 108-2 is stored in the third memory by the clock 108-3. Data is indicated by ●, and data stored in the fourth memory by the clock 108-4 is indicated by a black square.
[0076]
As is clear from the figure, the generation order of the parallel conversion clocks (108-1 to 4) is reset by the horizontal synchronizing signal (104), so that the data of the pixels located on the same vertical scanning line on the display screen are displayed. Are stored in the same memory 20.
[0077]
Therefore, in the arithmetic processing of data relating to the upper and lower pixels adjacent to the same vertical scanning line, such as correlation processing for eliminating flicker between lines, data may be read from the same memory, and multiple memories are not accessed. Can be processed. Thereby, the access time of the memory is shortened, and the speed of the image processing can be increased. Therefore, it is possible to reliably perform video signal processing on a computer video signal having a high pixel clock frequency, a high-definition video signal such as a high-definition video signal, etc., and further contribute to simplification of the device configuration.
[0078]
The video signal processing device according to the present embodiment may be provided inside the display device or inside the computer body or the like. When provided in a display device, signal processing is performed in accordance with its own display function (number of pixels, frame frequency, etc.), so that the range of application to input video signals is wide, and displays can be used in television receivers. In some cases, this can contribute to the enhancement of TV vision functions. On the other hand, when it is provided inside the computer main body, it has an effect that it can be connected to a commercially available television receiver.
[0079]
In the present embodiment, the display is not limited to a CRT or the like that performs raster scan display, but may be a projector of a projection type or the like, a liquid crystal display, a plasma display, or the like.
[0080]
【The invention's effect】
As described above, according to the present invention, the sampling clock and the parallel conversion clock are generated by the same clock generator, so that the time delay between the sampling clock and the parallel conversion clock can be easily reduced.
[0081]
That is, by generating two clocks in the same circuit, it is easy to grasp the time delay amount of the clock, and it is also easy to adopt a configuration in which the sampling clock is delayed by the time delay amount and output.
[0082]
Therefore, conversion of serial data into parallel data using the clock for parallel conversion can be performed extremely accurately. It should be noted that n memories can be operated at a low speed of 1 / n of the sampling frequency by n parallel conversion clocks obtained by dividing the sampling clock by n, and a video signal having a high pixel clock frequency can be used. Even if there is, predetermined video signal processing can be reliably performed.
[0083]
Also, by resetting the order of generation of the plurality of parallel conversion clocks in synchronization with the horizontal synchronization pulse, it is possible to sample the video signal of the pixel related to the same vertical scanning line of the display with one parallel conversion clock.
[0084]
Further, each memory stores video information on the same vertical scanning line.
[0085]
Therefore, for example, when performing correlation processing or the like on video signals related to adjacent pixels on the same vertical scanning line, data may be read from the same memory, and processing can be performed without accessing a plurality of memories. Thereby, the access time of the memory is shortened, and the speed of the image processing can be increased.
[0086]
Therefore, it is possible to reliably perform video signal processing on a computer video signal having a high pixel clock frequency, a high-definition video signal such as a high-definition video signal, etc., and further contribute to simplification of the device configuration.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing a video signal processing device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a clock generation unit 12 of FIG. 1;
FIG. 3 is a diagram showing a circuit configuration of a 1 / n frequency dividing unit 32 in FIG. 2;
FIG. 4 is a diagram showing signal waveforms at each terminal of a 1 / n frequency divider in FIG. 3;
FIG. 5 is a diagram showing a clock waveform output from a clock generation unit 12 of FIG.
6 is a diagram showing a relationship between data stored in a memory 20 of FIG. 1 and each pixel on a display screen.
FIG. 7 is a schematic configuration diagram showing a conventional video signal processing device.
FIG. 8 is a diagram showing clock waveforms output from a PLL 42 and a clock buffer 44 in FIG. 7;
9 is a diagram showing a relationship between data stored in a memory 20 of FIG. 7 and each pixel on a display screen. FIG. 4 is a diagram illustrating a circuit configuration of an output control unit 34 in FIG. 3.
[Explanation of symbols]
10 IC
12 Clock generator
14 A / D converter
16 signal processing unit
18 D / A converter
20 memories

Claims (2)

In the first have rows predetermined signal processing an analog video signal into digital signals of a frequency, a video signal processing apparatus for outputting an analog signal of a second frequency for displaying an image on a display,
Clock generating means for generating a sampling clock based on a horizontal synchronization signal, further dividing the sampling clock, and generating a plurality of parallel conversion clocks having a low frequency according to a dividing ratio and different phases from each other;
Analog-to-digital conversion means for sampling a serial analog video signal based on the sampling clock output from the clock generation means and converting it to a digital video signal,
Wherein the digital video signal to said sampling used repeatedly in a predetermined order phase multiple parallel conversion clock different from each other and stored in the memory means is converted into a parallel digital video signal, the stored parallel digital A pixel clock corresponding to an analog signal of a second frequency is subjected to a correlation process with respect to a signal of an adjacent pixel on the same vertical scanning line in a video signal, and a signal process of performing a time axis conversion by adjusting a readout timing. Signal processing means for outputting as a digital signal for each pixel according to
Digital / analog conversion means for converting the digital video signal for each pixel into an analog video signal of a second frequency ;
Has,
In the signal processing means, when converting to a parallel digital video signal, reset the order using the plurality of parallel conversion clocks having different phases in synchronization with the horizontal synchronization signal , in each horizontal scanning line, The conversion is started using the parallel conversion clock of the same phase among the plurality of parallel conversion clocks, and the parallel digital video signals of adjacent pixels on the same vertical scanning line are converted to the parallel conversion clock of the same phase. A video signal processing device characterized by being obtained by using the following . The video signal processing device according to claim 1,
A plurality of memory means for storing the parallel digital video signal in correspondence with the plurality of parallel conversion clocks,
A video signal processing device, wherein the digital video signals respectively stored in the plurality of memory means are signals relating to each pixel on a predetermined vertical line on a screen of a display.

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