JPH07298204A - Video signal processing unit - Google Patents

Abstract

PURPOSE:To provide a video signal processing unit in which a video signal is processed with high precision and simple unit configuration. CONSTITUTION:A clock generating section 12 and a signal processing section 16 are formed in a circuit of an IC 10. The clock generating section 12 generates a sampling clock 106 based on a horizontal synchronizing signal 104 and n-sets of parallel conversion clocks 108 whose phases differ from each other through the 1/n frequency division of the sampling clock 106. An A/D converter section 14 converts an analog video signal 102 into a digital video signal 110 based on the sampling clock 106. The digital video signal 110 is converted into parallel data 112 based on the parallel conversion clock 108. The generating sequence of the parallel conversion clocks 108 is controlled while being reset synchronously with the horizontal synchronizing signal 104. Then data stored in a memory 20 are signals relating to each picture element on a same vertical scanning line on the screen of the display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for converting an analog video signal into a digital signal and performing predetermined video signal processing.

[0002]

2. Description of the Related Art In recent years, along with the multifunctionalization of television, not only video signals of NTSC (National Television Committee) system but also VGA standard (pixel number 640 × 480), etc. It has been proposed to display the video signal of the computer and the video signal of high definition on the same display.

Since these video signals have different standards, their frequencies are different. Therefore, in order to display these video signals on the same display, a video signal processing device is provided in the display device or the computer main body, and the predetermined video signal processing such as frequency conversion is performed by digitizing the analog video signal. There was a need.

Further, when performing predetermined signal processing such as frequency conversion using a peripheral device such as a memory, serial data is converted into parallel data for parallel operation. This is because the frequency of a pixel clock such as a computer video signal (for example, 30 MHh) with respect to the processing speed of the memory.
This is because Z) is high and the memory processing cannot keep up with serial data.

An example of this video signal processing device will be described below with reference to FIG.

The clock generating section constituted by the PLL 42 and the signal processing section 16 are formed in an internal circuit of the same IC 10 and controlled by a CPU (not shown) or the like.

Then, the PLL 42 outputs a horizontal synchronizing signal (10
Based on 4), a sampling clock 406 as shown in FIG. 8A is generated according to the number of pixels on one horizontal scanning line.

The input analog video signal (102) is, for example, a video signal of NTSC system, a video signal of a computer such as VGA standard, or a video signal of high definition, and C
This is a video signal displayed on a display such as an RT (Cathod Ray Toub). In the case of color display, the analog video signal (102) has signals for each of RGB colors, but it is omitted here for simplification of description.

Analog / digital (A / D) converter 14
Is the input serial analog video signal (102)
Sampling is performed based on the sampling clock (406) and the serial digital video signal (11
Convert to 0). Then, the serial digital video signal (110) is sequentially output to the signal processing unit 16.

Programmable clock buffer 44
Is a circuit formed of a predetermined number n (n = 4 in this embodiment) bit counter and formed outside the IC 10. The clock buffer 44 divides the sampling clock by n to generate the clocks shown in FIGS.
A plurality of parallel conversion clocks (408) having different phases as shown in 408-1 to 408-4 are generated. And
This parallel conversion clock (408) is supplied to each memory 46, and the serial digital video signal (110) output to the signal processing unit 16 is supplied to each parallel conversion clock (40
8) and is stored in each memory 46 as a parallel digital video signal (412).

The signal processing section 16 reads the parallel digital video signals (412) stored in the memory 46 and performs predetermined signal processing as described later.

The digital video signal subjected to the signal processing is
Output to the digital / analog (D / A) converter 18,
The D / A converter 18 converts the digital video signal into an analog video signal (414) again and outputs it to a picture tube or the like of the CRT.

The memory 46, the A / D converter 14 and the D / A converter 18 are the same as the clock buffer 44.
It is composed of peripheral devices provided outside the C10.

The signal processing performed by the signal processing unit 16 varies depending on the input video signal (102), the video displayed on the display, and the like.

For example, when the input video signal (102) is a computer video signal, its horizontal frequency is about 30 kHz when the number of pixels is 640 × 480 (VGA),
The number of frames per second is 60. The display is N
In the case of a television receiver that displays a TSC video signal in raster scan display, the horizontal frequency of the video signal is about 15 kHz.
Z, the number of frames per second is 30.

Therefore, in this case, the signal processing unit 16 performs time base conversion to determine the horizontal frequency of the computer video signal as
It is necessary to convert the horizontal frequency of the NTSC video signal to the same level.

In the time axis conversion processing, the signal processing unit 1
6 reads the video signal stored in each memory 46 and sequentially outputs it to the digital-analog (D / A) converter 18 at the frequency of the pixel clock of the NTSC system. Furthermore, D / A
The converter 18 converts the digital video signal into an analog video signal (414) again and outputs it to a picture tube (in the case of a CRT display) or the like.

Further, if the time axis conversion is simply performed, the displayed image may not be smooth and flickering may occur in the display. Then, in order to prevent this flicker, the signal processing unit 16 performs the following correlation processing (filtering processing) and the like.

From each memory 46, for example, data of three adjacent pixels on the same vertical scanning line of the display are read. Then, correlation processing such as predetermined weighting and averaging is performed on these three data to create data for one pixel. When the correlation processing ends, the signal processing unit 1
6 reads out the processed data and sequentially outputs it to the D / A converter 18 at the frequency of the pixel clock of the NTSC system, and converts it into the analog video signal (414).

By performing such correlation processing, it is possible to improve the display quality of the video subjected to the time axis conversion.

[0021]

However, in the conventional video signal processing device, although the PLL 42 and the signal processing unit 16 are formed in the same IC circuit, the sampling clock (406) is divided. Clock buffer 4
4 is provided as a separate circuit outside the IC 10.

Generally, when the sampling clock 406 is divided to generate each parallel conversion clock 408, a predetermined time delay t occurs with respect to the sampling clock 406.

However, the clock buffer 44 is
In the case of the external circuit, it is not easy to grasp the amount of the time delay t and the system design is complicated.

If this time delay t is not resolved,
There was a possibility that a sampling error would occur when sampling the serial digital video signal (110) based on the parallel conversion clock (408).

Further, by making the clock buffer 44 an external circuit of the IC 10, miniaturization of the system is hindered.

The order of generation of the parallel conversion clocks (408-1) to (408-4) shown in FIGS. 8B to 8E is as follows.
The digital video signal stored in each memory 46, which is sampled based on this clock (408-1) to (408-4), is simply parallel-converted, regardless of the number of pixels on one horizontal scanning line. I was just there.

Therefore, for example, the relationship between the data of each pixel in the raster scan display and the data stored in each memory 46 is as shown in FIG. In the figure, clock 40
The data stored in the first memory by 8-1 is ◯, the data stored in the second memory by clock 408-2 is □, the data stored in the third memory by clock 408-3 is ●, The data stored in the fourth memory by the clock 408-4 is shown as a black square.

As is apparent from FIG. 8, the data stored in each memory 46 is not always the data of the pixels (pixels arranged in the vertical direction) located on the same vertical line on the screen of the display.

Therefore, for example, even if the video signals between adjacent horizontal scanning lines have a strong correlation in serial data, it is difficult to maintain this correlation in the parallel data stored in each memory 46. there were.

In addition, in the correlation processing performed between the data corresponding to the same vertical line in the signal processing unit 16, it is necessary to access all the memories 46, which hinders the speeding up of the image processing.

The present invention has been made in order to solve these problems, and an object of the present invention is to provide a video signal processing device capable of highly accurate video signal processing with a simple device configuration.

[0032]

In order to achieve the above object, the video signal processing apparatus according to the present invention has the following features.

In a video signal processing device for converting an analog video signal for displaying a video on a display into a digital signal and performing a predetermined signal processing, a sampling clock is generated based on a horizontal synchronizing signal, and the sampling clock is further used. Clock generation means for dividing and generating a plurality of parallel conversion clocks having mutually different phases,
An analog-to-digital converter that samples a serial analog video signal based on the sampling clock output from the clock generator and converts it into a digital video signal, and the digital video signal is sampled based on the parallel conversion clock. Signal processing means for converting the parallel digital video signal into a parallel digital video signal and performing a predetermined signal processing on the parallel digital video signal, and a digital for converting the signal-processed digital video signal into an analog video signal. -Analog conversion means.

The generation order of the plurality of parallel conversion clocks is reset in synchronization with the horizontal synchronizing signal.

Further, there is provided a plurality of memory means for storing the parallel digital video signal corresponding to the plurality of parallel conversion clocks, respectively, and the digital video signals stored in the plurality of memory means are respectively: It is characterized in that it is a signal relating to each pixel on the same vertical line on the screen of the display.

[0036]

According to the present invention, the sampling clock and the parallel conversion clock are generated by the same clock generating section, whereby the time delay between the sampling clock and the parallel conversion clock can be easily reduced.

If the frequency division of the sampling clock is performed in the circuit of the peripheral device different from the sampling clock generator, it is difficult to grasp the time delay amount of the generated parallel conversion clock with respect to the sampling clock. However, in the present invention, since two clocks are generated in the internal circuit such as an IC, it is easy to grasp the time delay amount, and it is also easy to delay the sampling clock by the time delay amount and output it. .

Therefore, the conversion of serial data into parallel data based on the parallel conversion clock can be performed extremely accurately. It should be noted that the n parallel conversion clocks obtained by dividing the sampling clock by n can operate the n memories at a low speed of 1 / n of the sampling frequency. Even if there is, the predetermined video signal processing can be surely performed.

Further, the generation order of the plurality of parallel conversion clocks is reset in synchronization with the horizontal synchronizing pulse. Thereby, the video signals of the pixels on the same vertical line of the display can be sampled by one parallel conversion clock.

Further, the video signals on the same vertical line are stored in each memory.

Therefore, for example, when performing correlation processing on video signals of vertically adjacent pixels on the same vertical line, it is sufficient to read data from the same memory, and the processing can be performed without accessing a plurality of memories. it can. This allows
The memory access time is shortened and the image processing can be speeded up. Therefore, it becomes possible to reliably perform video signal processing even for high-definition video signals such as high definition video signals and computer video signals with a high pixel clock frequency.
It can also contribute to simplification of the device configuration.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing a video signal processing device according to an embodiment of the present invention. It should be noted that the same parts as those in the above-described figures are designated by the same reference numerals and the description thereof will be omitted.

The input video signal (102) is an NTSC system video signal, a computer video signal such as VGA standard, or a high definition video signal as in the prior art, and is raster-scan-displayed on a CRT or the like, for example. This is the video signal of the display.

The clock generator 12 is a circuit formed together with the signal processor 16 in the internal circuit of the IC 10 provided in the display device or the computer main body, for example. The clock generator 12 is composed of a PLL and a 1 / n frequency divider which will be described later.

The PLL section is an oscillating circuit for generating a sampling clock (106) based on the horizontal synchronizing signal (104). On the other hand, the 1 / n frequency division section uses the sampling clock (10
6) is divided by n (n = 4 in this embodiment) to generate n parallel conversion clocks having mutually different phases (see FIGS. 5C to 5F).

The A / D converter 14 samples the input serial analog video signal (102) based on the sampling clock (106) supplied from the clock generator 12, and outputs the serial digital video signal (110). ). Then, the digital video signal (110) is sequentially output to the signal processing unit 16.

The n (n = 4) memories 20 are connected to the IC 10
DRAM, FIFO memory, VRA provided outside
It is a memory element composed of M and the like, and four parallel conversion clocks (108) are supplied from the clock generation unit 12. Further, this memory 20 is a clock for parallel conversion.
A parallel digital video signal obtained by sampling the serial digital video signal (110) based on (108).
Store (112) respectively.

The signal processing unit 16 is a circuit for reading the digital video signal (112) stored in the memory 20 and performing a predetermined video signal processing by the input video signal (102). The signal is stored in the line memory provided in the signal processing unit 16 and output to the D / A conversion unit 18.

The D / A converter 18 is a converter provided outside the IC 10, and converts the digital video signal output from the signal processor 16 into an analog video signal (114) and sends it out. .

Next, the configuration of the clock generator 12 will be described with reference to FIG.

The clock generator 12 generates a sampling clock (106 ') formed in the internal circuit of the same IC and a 1 / n (in this embodiment, a parallel conversion clock (108)) clock for parallel conversion. (n = 4) frequency divider 32.

The PLL section includes a phase comparison section 22 and a VCO.
(Voltage controlled Oscillator: Voltage controlled oscillator)
26 and a loop filter 28 inserted in the path from the phase comparison unit 22 to the VCO 26. Furthermore, VC
In the path from O26 to the phase comparison unit 22, the frequency division unit (1 /
1H pixel number) 24 is provided.

The frequency divider 24 divides the signal of the predetermined frequency output from the VCO 26 according to the number of pixels of one horizontal scanning line, and supplies the signal of the frequency substantially equal to the horizontal synchronizing signal to the phase comparator 22. .

The phase comparing section 22 compares the phase of the signal output from the frequency dividing section 24 with the phase of the horizontal synchronizing signal and generates an error signal thereof. Then, this error signal is output to the VCO 26 via the loop filter 28.

The VCO 26 is an oscillating unit that changes the oscillation frequency according to the error signal, and the signal finally output from the VCO 26 as the sampling clock (106 ') shown in FIG. 5A is a horizontal synchronizing signal. The frequency is exactly equal to the frequency x 1H pixels.

The output side of the VCO 26 has a 1 / n frequency divider 32.
And the delay unit 30 are respectively connected. Delay unit 30
Is a circuit for delaying the sampling clock (106 ') by a predetermined amount. The delay amount corresponds to the time delay of the parallel conversion clock (108) generated when the 1 / n frequency divider 32 divides the sampling clock (106 ').

Since the PLL section and the 1 / n frequency division section 32 are formed in the same IC as described above, it is extremely easy to grasp the time delay amount.

Therefore, the structure of the delay unit 30 for correcting the delay amount of the sampling clock (106 ') is simple, and the sampling clock (106) supplied to the A / D conversion unit 14 and each parallel conversion clock (108). It is possible to prevent a time delay from occurring. As a result, the sampling of the video signal at the time of analog / digital conversion and serial / parallel conversion can be accurately executed.

Next, a configuration example of the 1 / n frequency dividing section 32 will be described with reference to FIG.

The 1 / n frequency divider 32 has two stages of flip-flops 34 (FF1) and 36 (FF2), and a number (n = 4) of gates 38-1 to 38-4 corresponding to the frequency division number n. It consists of and.

The configuration of the 1 / n frequency divider 32 is not limited to that shown in FIG. 3, and the frequency division number n is set to an optimum value according to the operating speed of the memory or the like. Further, the frequency division number n is equal to the number of parallel conversion clocks (108) generated and the number of memories 20.

A sampling clock (106 ') output from the VCO 26 as shown in FIG. 4A is supplied to the CLK input terminal of the FF1.

The inverted Q output terminal of FF1 is FF
1 is connected to the D input terminal. Therefore, the Q output of FF1 is inverted each time the pulse of the sampling clock (106 ') rises, and the Q output of FF1 is output from the Q output terminal of FIG.
As shown in (b), a pulse having a cycle twice that of the sampling clock (106 ') is output.

The inverted Q output terminal of FF1 is the same as that of FF2.
It is connected to the CLK input terminal. Then, from the inverted Q output terminal of this FF1, the FF1 as shown in FIG.
A pulse obtained by inverting the output signal from the Q output terminal of is output.

The inverted Q output terminal of FF2 is connected to the D input terminal of FF2. As a result, the Q output of FF2 is inverted every time the pulse of the inverted Q output of FF1 rises, so that the Q output terminal of FF2 is delayed by one clock from the inverted Q output of FF1 as shown in FIG. 4 (d). A rising pulse is output.

The Q output terminals of FF1 and FF2 are
The gates are connected to the input terminals of 38-1 to 38-4, respectively. In this embodiment, the two inputs of the gate 38-1 are both inverting inputs, and the inputs of the gates 38-2 and 38-3 are only inverting inputs, respectively.

From each of the gates 38-1 to 38-4, as shown in FIG.
Sampling clock as shown in (c) to (f) of
4 that are 1/4 of the (106 ') frequency and have different phases
Two parallel conversion clocks (108-1 to 4) are output.
In the figure, each parallel conversion clock (108-1 to 4)
The positive pulse width of is shown as the same as the pulse width of the sampling clock 106 ′, but the pulse width is not limited to this and may be a pulse with a duty of 50%.

Further, the horizontal synchronizing signal (104) shown in FIG. 4 (b) is supplied as a reset signal to the R input terminals of FF1 and FF2, and when this reset signal is input, F
The outputs from the Q output terminals of F1 and FF2 are initialized. And the clock for parallel conversion (108-1 to 4)
The order of occurrence of is reset.

That is, each parallel conversion clock 108-1 ...
108-4 is a clock as shown in FIGS.
108-1 → Clock 108-2 → Clock 108-3 → Clock 10
Pulses are generated in order of 8-4 → clock 108-1 → ...

In this state, the horizontal synchronizing signal (104) generated every horizontal scanning period is used as a reset signal by the FF.
When supplied to the R input terminals of 1 and FF2, the generation order of the parallel conversion clocks (108-1 to 108-4) is reset. At the same time as the reset, the parallel conversion clock (108-
The pulse of 1) rises.

In this way, by the horizontal synchronizing signal (104),
By resetting the generation order of the parallel conversion clocks (108-1 to 108-4), the generation order becomes the same during each horizontal scanning period.

The serial digital video signal (110) shown in FIG. 1 is supplied to the parallel conversion clocks (108-1 to -4).
Are sampled, converted into parallel and stored in each memory 20.

The relationship between the data of each pixel in the raster scan display and the data stored in each memory 20 is shown in FIG.

In the figure, the data stored in the first memory by the clock 108-1 is ◯, the data stored in the second memory by the clock 108-2 is □, and the clock 108-3.
Data stored in the third memory by
108-4 shows the data stored in the fourth memory as black squares.

As is clear from the figure, the horizontal sync signal (10
By the generation order of the parallel conversion clocks (108-1 to 4) is reset by 4), the data of pixels located on the same vertical scanning line on the display screen is stored in the same memory 20. .

Therefore, in the arithmetic processing of the data relating to the adjacent upper and lower pixels of the same vertical scanning line, such as the correlation processing for removing the flicker between the lines, it is sufficient to read the data from the same memory. Processing is possible without access. As a result, the memory access time can be shortened and the image processing can be speeded up. Therefore,
It is possible to reliably perform video signal processing even on a computer video signal having a high pixel clock frequency, a high definition video signal such as a high-definition video, etc., and it is possible to further contribute to simplification of the device configuration.

The video signal processing device of this embodiment may be provided either inside the display device or inside the computer body or the like. When it is installed in a display device, it has its own display function (number of pixels,
Since the signal processing is performed according to the frame frequency, etc., it has a wide range of application to the input video signal, and when the display is a television receiver, it can contribute to high functionality of television vision. On the other hand, when it is provided inside the computer main body, it has an effect that it can be connected to a commercially available television receiver.

Further, in the present embodiment, the display is not limited to the CRT or the like which performs raster scan display, but may be a projection type projector, a liquid crystal display, a plasma display or the like.

[0080]

As described above, according to the present invention, the time delay between the sampling clock and the parallel conversion clock can be reduced by generating the sampling clock and the parallel conversion clock in the same clock generator. It's easy.

That is, by generating two clocks in the same circuit, the time delay amount of the clock can be easily grasped, and the sampling clock can be easily delayed by the time delay amount and output. Becomes

Therefore, the conversion of serial data into parallel data using the parallel conversion clock can be performed extremely accurately. Note that the sampling clock is
With n parallel conversion clocks obtained by frequency division, n memories can be operated at a low speed of 1 / n of the sampling frequency, and even if the video signal has a high pixel clock frequency, it can be surely specified. The video signal processing can be performed.

Further, by resetting the generation order of a plurality of parallel conversion clocks in synchronization with the horizontal synchronizing pulse, it is possible to sample the video signals of the pixels associated with the same vertical scanning line of the display by one parallel conversion clock. .

Further, the video information on the same vertical scanning line is stored in each memory.

Therefore, for example, when performing correlation processing or the like on video signals relating to pixels adjacent to each other in the same vertical scanning line, it is sufficient to read data from the same memory and the processing can be performed without accessing a plurality of memories. it can. This allows
The memory access time is shortened and the image processing can be speeded up.

Therefore, it becomes possible to surely perform the video signal processing even for the computer video signal having a high pixel clock frequency and the high definition video signal such as the high definition.
It can also contribute to simplification of the device configuration.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a video signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a clock generation unit 12 in FIG.

FIG. 3 is a diagram showing a circuit configuration of a 1 / n frequency divider 32 in FIG.

FIG. 4 is a diagram showing a signal waveform at each terminal of the 1 / n frequency divider in FIG.

5 is a diagram showing clock waveforms output from the clock generator 12 of FIG.

FIG. 6 is a diagram showing a relationship between data stored in a memory 20 of FIG. 1 and each pixel on a display screen.

FIG. 7 is a schematic configuration diagram showing a conventional video signal processing device.

8 is a diagram showing clock waveforms output from the PLL 42 and the clock buffer 44 of FIG.

9 is a diagram showing a relationship between data stored in the memory 20 of FIG. 7 and each pixel on the display screen. It is a figure which shows the circuit structure of the output control part 34 of FIG.

[Explanation of symbols]

 10 IC 12 clock generation unit 14 A / D conversion unit 16 signal processing unit 18 D / A conversion unit 20 memory

Claims (3)

[Claims] 1. A video signal processing device for converting an analog video signal for displaying a video on a display into a digital signal and performing predetermined signal processing, wherein a sampling clock is generated based on a horizontal synchronizing signal, and the sampling is further performed. A clock generating unit that divides the clock to generate a plurality of parallel conversion clocks having different phases, and a serial analog video signal is sampled based on the sampling clock output from the clock generating unit to generate a digital image. An analog / digital conversion means for converting the signal into a signal, and the digital video signal is sampled based on the parallel conversion clock to be converted into a parallel digital video signal, and predetermined signal processing is performed on the parallel digital video signal. A signal processing unit for performing the signal processing, A video signal processing apparatus characterized by having a digital-to-analog conversion means for converting an analog video signal to the digital video signal is applied. 2. The video signal processing device according to claim 1, wherein the generation order of the plurality of parallel conversion clocks is reset in synchronization with the horizontal synchronization signal. 3. The video signal processing device according to claim 1, wherein the parallel digital video signals are stored in correspondence with a plurality of parallel conversion clocks, respectively. The video signal processing apparatus according to claim 1, wherein the digital video signals respectively stored in the plurality of memory means are signals relating to respective pixels on the same vertical line on the screen of the display.