JP2002311929A - Converting circuit for synchronizing frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert the synchronizing frequency of video signals and to fix its horizontal synchronizing frequency. SOLUTION: Input video signals S11 are written into a memory 43 in synchronism with the horizontal and the vertical synchronizing signals in the signals S11. Then, a discriminating circuit 52, which discriminates to determine the synchronizing frequencies of the horizontal and the vertical synchronizing frequencies of the signals S11, and forming circuits 53 to 55 and 60, which forms reading control signals S5R whose frequency is changed from reference signals S64 corresponding to the discrimination result of the circuit 52, are provided. Then, forming circuits 53 and 54, which form horizontal synchronizing signals Hout having a constant frequency from the signals 64, and forming circuits 53 and 54, which form vertical synchronizing signals Vout whose frequency varies corresponding to the discrimination result of the circuit 52 from signals S64, are provided. Video signals written into the memory 43 are read by reading control signals S5R and the read video signals S13, the signals Hout and the signals Vout are outputted as output signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a circuit for converting a synchronous frequency of a video signal.

[0002]

2. Description of the Related Art A display device used in a personal computer, a workstation or the like often uses a CRT as a display means or a display element.

[0003]

However, the specifications of video signals sent from a computer or the like to a display device are not uniform, and the synchronization frequency, video display period, video retrace period, and the like are various. ing. For this reason,
Among display devices using a CRT, a CRT display called a multi-scan display (CRT)
The monitor is adapted to support multiple sets of horizontal and vertical synchronization frequencies.

In this case, as a method for a CRT display to cope with a plurality of sets of horizontal and vertical synchronization frequencies, the horizontal and vertical deflection frequencies of the CRT are made variable. And the horizontal and vertical deflection frequencies are
Change so as to match the horizontal and vertical synchronization frequencies of the input video signal. The horizontal and vertical deflection frequencies in a CRT are fixed at a single frequency. Then, the horizontal and vertical synchronization frequencies of the input video signal are converted into horizontal and vertical deflection frequencies of the CRT by performing an interpolation process and a thinning process on the input video signal. It has been known.

However, in the case of the method (1), the range of the horizontal deflection frequency is widened. Therefore, in order to stably obtain a high voltage for horizontal deflection and CRT, a separate system in which a horizontal deflection circuit and a high voltage generation circuit are separated from each other. Is the basis.

However, even in such a case, since the horizontal deflection circuit must be synchronized with a wide range of frequencies, it has been difficult to design synchronization performance, for example, jitter performance well.

Further, when the horizontal deflection frequency changes, the horizontal size of the display screen changes. Therefore, it is necessary to control the power supply of the horizontal deflection circuit according to the horizontal deflection frequency. Further, it is necessary to switch the horizontal S-shaped correction capacitor according to the horizontal deflection frequency, and for this switching, it is necessary to use an FET having a high withstand voltage as a switch. Also, tracking adjustment for the frequency characteristics of the horizontal deflection circuit must be performed.

Further, if the frequency of the horizontal drive pulse suddenly changes due to the characteristics of the horizontal deflection circuit, it will result in destruction. Therefore, it is necessary to properly execute a protection procedure. Furthermore, since the response when controlling the main deflection and the high voltage changes depending on the horizontal scanning frequency, setting the design parameters is difficult, and in some cases, the parameters need to be switched according to the horizontal scanning frequency.

Furthermore, in recent years, the synchronization frequency of a video signal has become
As the resolution of the display screen becomes finer, it is becoming higher. As a result, it is desired that the horizontal synchronizing frequency can correspond to 15.75 kHz of the NTSC signal below and 130 kHz or more for high-performance workstations above. . Therefore, the horizontal deflection circuit for multi-scan is considerably more complicated in terms of circuit and system than a horizontal deflection circuit having a single horizontal deflection frequency.

The vertical deflection circuit has the same problem as the horizontal deflection circuit. However, since the frequency of a signal to be handled is much lower than that of the horizontal deflection circuit, the burden is considerably smaller than that of the horizontal deflection circuit. Is easy.

On the other hand, in the case of the method, since there is no need to change the deflection frequency, there is no problem as in the case of the method.

However, in the case of the method (1), interpolation or thinning is performed on an input video signal, so that, for example, a point or a line that should be displayed by one dot is represented by two dots on a display screen. Displayed, or conversely 2
A point or line to be displayed by one dot is displayed by one dot. Moreover, such a phenomenon does not occur uniformly, for example, every three dots.

As a result, when text characters or graphics are displayed, the outline is blurred and the display quality is significantly reduced. In particular, in the case of a display device for a workstation, for example, in which display quality is required to be extremely strict, deterioration in image quality due to interpolation or thinning of display data is not allowed.

Further, a digital filter or the like is used for the interpolation processing, but the digital filter occupies a large proportion in the hardware LSI. Furthermore, since the frequency range of the signal to be handled is wide and high, the operating frequency of the interpolation arithmetic unit also becomes a very high value, and it is difficult to appropriately cope with the operation frequency.

For the above reasons, the following method is generally employed in a multi-scan display.
However, at that time, the above problem has not been solved.

Therefore, a technique described with reference to FIGS. 3 to 6 has been considered. That is, the input video signal is written to the frame memory in synchronization with the horizontal and vertical synchronization frequencies, and the written video signal is read out in synchronization with the horizontal and vertical deflection frequencies of the CRT.

In this case, when writing the input video signal to the frame memory, it is assumed that the input video signal is written for each dot displayed by the video signal. The reading of the video signal from the frame memory is also performed in dot units, and it is assumed that the readout is performed for each dot without excess or deficiency.

The horizontal deflection of a CRT under such conditions is as follows. That is, when a video signal is read from the frame memory, as shown in FIG. 6, each dot displayed on the CRT is associated with each cycle of the read clock CLKR in an arbitrary horizontal line (horizontal and vertical). Since the total number of dots in one second is equal to the number of dots in one line × the number of horizontal lines in one second, the frequency fclkr of the read clock CLKR is fclkr = (nhscn + nhblk) · fhdef (1) ) nhscn: number of dots in horizontal video period (horizontal effective scanning period) nhblk: number of dots in horizontal blanking period fhdef: horizontal deflection frequency (output horizontal synchronization frequency) of CRT

When the read clock CLKR is formed by a PLL, fclkr = N · fref (2) N: frequency division ratio of the variable frequency divider circuit of the PLL fref: frequency of the reference signal of the PLL.

Therefore, from equations (1) and (2), N = fclkr / fref = (nhscn + nhblk) fhdef / fref (3)

However, actually, since the frequency division ratio N is an integer, the equation (3) further satisfies the following equation: N = int (fclkr / fref + 0.5) = int ((nhscn + nhblk) fhdef / fref + 0.5) ... (4)

Here, int (x) is a function that rounds the value x down to the decimal point to make it an integer. Therefore, int (x + 0.
5) is a value obtained by rounding off the decimal part of the value x. Therefore, the dividing ratio N obtained by the expression (4) is a value obtained by rounding off the decimal part of the dividing ratio N obtained by the expression (3) and converting it to an integer. If the error does not matter, It may be rounded down to an integer.

When the frequency division ratio N obtained by the equation (4) (or the equation (3)) is used, the actually obtained frequency fclkr0 of the read clock CLKR is: fclkr0 = int ((nhscn + nhblk) fhdef / fref + 0 .5) fref (5) Therefore, the actual horizontal deflection frequency fhdef0 of the CRT is fhdef0 = 1 / (nhscn + nhblk) .fcrl0 = int ((nhscn + nhblk) fhdef / fref + 0.5)) / (nhscn + nhblk) · fref (6).

The horizontal retrace period thblk0 of the CRT is as follows: thblk0 = nhblk / fclkr0 (7)

That is, when the video signal is read from the frame memory, if the frequency division ratio N is set to the value shown by the equation (4), the frequency fclkr0 of the read clock CLKR becomes the value shown by the equation (5). As shown in FIG. 6, each dot of the video can be associated with each cycle of the read clock CLKR, and each dot can be read and displayed without excess or deficiency.

At this time, even if the resolution changes,
The horizontal deflection frequency fhdef0 of the CRT becomes a value represented by the equation (6), and changes only within the range of the reference frequency fref of the PLL 60. Therefore, its reference frequency fre
If f is set low, the horizontal deflection frequency fhdef0 becomes almost constant.

On the other hand, the vertical deflection of a CRT is as follows. That is, horizontal deflection frequency = vertical deflection frequency × number of horizontal lines per vertical period or vertical deflection frequency = horizontal deflection frequency / number of horizontal lines per vertical period (8).

In this case, the horizontal deflection frequency fhdef
Since 0 is substantially constant, when a video signal is read from the frame memory, the vertical cycle of the readout changes according to the number of horizontal lines (the number of horizontal lines per vertical period) of the video signal to be read. .

Therefore, in the video signal supplied to the CRT, the vertical deflection frequency fvdef0 is fvdef0 = fhdef0 / (nhscn + nhblk) (9) nvscn: the vertical video period (vertical effective scanning period) of the input video signal ) The number of horizontal lines nvblk: The number of horizontal lines in the vertical blanking period. Also, the vertical blanking period tvblk0 in the CRT
Is as follows: tvblk0 = nvblk / fhdef0 (10)

Therefore, the vertical deflection frequency of the CRT also changes. However, as mentioned above, the vertical deflection frequency is much lower than the horizontal deflection frequency,
The burden associated with the vertical deflection circuit is fairly small.

When an image is displayed on a CRT by the above-described method, the image signal is only written and read in the frame memory in dot units of the input image signal. Since no processing such as thinning or thinning is performed, the display quality hardly deteriorates.

Further, since it is not necessary to change the horizontal deflection frequency of the CRT even when the resolution is changed, the configuration of the horizontal deflection circuit is simplified, and appropriate horizontal deflection can be performed even if distortion correction or the like is required. it can.

As is apparent from equation (9), when the number of horizontal lines nvscn increases, the vertical deflection frequency fvdef0 decreases, and flicker on the CRT becomes noticeable. Therefore, when the number of horizontal lines nvscn is the largest input video signal, the horizontal deflection frequency fhdef0 is set so that flicker on the CRT is not noticeable.

FIGS. 3 and 4 show an example in which the display circuit and the synchronous frequency conversion circuit are configured according to the above concept. That is, in FIG. 3, the input video signal S11 is supplied from the input terminal 11 to the synchronous frequency conversion circuit 14 through the input interface circuit 13. A horizontal and vertical synchronizing signal Ssync corresponding to the input video signal S11 is supplied from the input terminal 12 to the interface circuit 1.
3 to the synchronous frequency conversion circuit 14.

In this case, it is assumed that the video signal S11 is a three-primary-color signal composed of red, green and blue signals.
Although the details of the conversion circuit 14 will be described later, the conversion circuit 14 has a frame memory, and converts the synchronization frequency of the supplied video signal S11 and outputs the video signal S14 according to the above idea. is there.

The output video signal S 14 is supplied to a color CRT 17 through a video drive circuit 16 after processing such as gamma correction is performed in a video control circuit 15.

The horizontal synchronizing signal H synchronized with the output video signal S14 is output from the conversion circuit 14, for example, as shown in FIG.
out is taken out, and the horizontal synchronization signal Hout is supplied to the horizontal deflection circuit 21 to form a horizontal deflection current. Then, the horizontal deflection current is supplied to the horizontal deflection coil 22, and the horizontal deflection of the CRT 17 is performed. Note that the horizontal deflection frequency at this time is a value fhdef0.

Further, a horizontal pulse is extracted from the horizontal deflection circuit 21, and the horizontal pulse is supplied to a high voltage generation circuit 23 to form a high voltage. The high voltage is supplied to the CRT 17 as an anode voltage or the like.

Further, the output video signal S
A vertical synchronizing signal Vout synchronized with 14 is taken out, and this vertical synchronizing signal Vout is supplied to a vertical deflection circuit 24 to form a vertical deflection current. This vertical deflection current is supplied to a vertical deflection coil 25 to cause a vertical deflection of the CRT 17 to be performed. Is performed.
Note that the vertical deflection frequency at this time is a value fvdef0.

In this case, the synchronous frequency conversion circuit 1
4 is configured, for example, as shown in FIG. That is,
The input video signal S11 from the interface circuit 13 is
The signal is supplied to the A / D converter circuit 42 and A / D-converted into a digital video signal S12. This signal S12 is supplied to the frame memory 43.

The horizontal synchronizing signal Hin of the synchronizing signal Ssync is extracted from the interface circuit 13 and supplied to the PLL 51 to form a pulse signal S51 having a frequency corresponding to the dot period of the input video signal S11. The pulse signal S51 is supplied to the A / D converter circuit 42.
Is supplied as a clock at the time of the A / D conversion, and the input video signal S11 is A / D converted as described above for each dot when the display is performed by the signal S11.

Further, the horizontal and vertical synchronizing signals Ssync from the interface circuit 13 are supplied to a signal discriminating circuit 52, and the horizontal and vertical synchronizing frequencies of the input video signal S11, the temporal positions of the horizontal and vertical video periods, and the like are provided. Is determined, and the determined output is supplied to the timing control circuit 53.

The timing control circuit 53 is constituted by a microcomputer, a DSP or a hard logic. The control circuit 53 calculates the input video signal S11 and the input video signal S11 from the information indicated by the discrimination output of the signal discrimination circuit 52 by calculation or by referring to a look-up table prepared in advance in a nonvolatile memory or the like. The number of dots in one horizontal period of the output video signal S14, the number of horizontal lines in one vertical period, the temporal position of horizontal and vertical video periods (scanning periods), and the like are required to convert the synchronization frequency of the video signal. Data.

The output of the control circuit 53 is supplied to a timing pulse generation circuit 54. PLL5
The pulse signal S51 from the timing pulse generation circuit 5
4 and the horizontal and vertical synchronizing signals Hin and Vin are taken out of the interface circuit 13 and supplied to the timing pulse generating circuit 54.

Thus, the timing pulse generating circuit 54
, A timing signal S4W is formed. This timing signal S4W is stored in the frame memory 43 as the video signal S12.
Is a signal indicating the timing when writing is performed, and includes a signal indicating the temporal position of the horizontal and vertical video periods.

Then, the timing signal S 4 W is supplied to the memory controller 55, and the pulse signal S 51 from the PLL 51 is supplied to the memory controller 55. Thus, in the memory controller 55, a control signal S5W for writing the input video signal S12 to the frame memory 43 is formed, and this signal S5W is supplied to the frame memory 43.

The control signal S5W includes a write clock, a write address signal, and a write enable signal for writing the video signal S12 in the frame memory 43. These signals include the valid dots of the input video signal S12 and the write enable signal. It is changing in synchronization with the line.

Therefore, of the input video signal S12, the signal of the signal section serving as the display screen is sequentially written into the frame memory 43 for each dot without excess or deficiency.

The input video signal S12 written in the frame memory 43 is read out in synchronization with the horizontal and vertical deflection of the CRT 17. Therefore, the VCO 61
, An oscillation signal S61 having a predetermined frequency is extracted, and the oscillation signal S61 is supplied to the variable frequency dividing circuit 62. The variable frequency dividing circuit 62 and the VCO 61 constitute the PLL 60 together with the circuits 63 to 65.

Then, from the timing control circuit 53, (4)
The frequency dividing ratio N obtained according to the equation is taken out, the frequency dividing ratio N is set in the variable frequency dividing circuit 62, and the oscillation signal S61 is frequency-divided into a frequency of 1 / N from the variable frequency dividing circuit 62. The divided signal S62 is extracted, and the divided signal S62 is supplied to the phase comparison circuit 63. Further, the forming circuit 64 is composed of, for example, a crystal oscillation circuit and a frequency dividing circuit for dividing the oscillation signal to form a reference signal S64 having a stable frequency fref as a reference. Supplied to

In this way, in the comparison circuit 63, the frequency-divided signal S62 is compared in phase with the reference signal S64, and the comparison output is supplied to the loop filter 65 to correspond to the phase difference between the frequency-divided signal S62 and the reference signal S64. A DC voltage having a varying level is extracted. Then, this DC voltage is supplied to the VCO 61 as its control voltage.

Therefore, in the steady state, the signals S62 and S64
Are equal to each other, the expression (2) is established. As a result, the frequency of the oscillation signal S61 of the VCO 61 is set to the frequency fclkr0 shown by the expression (5).

The oscillation signal S61 is supplied as a read clock CLKR to the timing pulse generating circuit 54 to form a horizontal synchronizing signal Hout and a vertical synchronizing signal Vout. 21 and 24, and the CRT 17 has a frequency f
Horizontal and vertical deflections are performed at hdef0 and fvdef0.

In the timing pulse generation circuit 54, a timing signal S4R synchronized with the oscillation signal S61 (read clock CLKR) supplied thereto is formed.
The timing signal S4R is a signal indicating timing when the video signal S13 is read from the frame memory 43, and includes a signal indicating a temporal position of a horizontal and vertical video period.

Then, the timing signal S4R is supplied to the memory controller 55, and a control signal S5R for reading the output video signal S13 from the frame memory 43 is formed. The signal S5R is supplied to the frame memory 43. The control signal S5R includes, for example, a read clock CLKR for reading the video signal S13 from the frame memory 43, a read address signal, and a read enable signal RDEN as shown in FIG.

Accordingly, as shown in FIG. 6, for example, the horizontal synchronization frequency fhd is output from the frame memory 43 regardless of the horizontal and vertical synchronization frequencies of the input video signal S12.
ef0 is almost constant, and the output video signal S whose vertical synchronizing frequency changes corresponding to the number of horizontal lines of the input video signal S11.
13 is taken out.

Then, the extracted video signal S13
Is supplied to the D / A converter circuit 44,
The pulse signal S61 from the VCO 61 is supplied to the D / A converter circuit 44 as a clock for D / A conversion.
Thus, the video signal S13 is output to the D / A converter circuit 44.
In the above, the analog three primary color signals, that is, red, green and blue video signals S14 are D / A converted, and this signal S14 is supplied to the color CRT 17 through the video control circuit 15 and the video drive circuit 16 as described above. .

Thus, according to the display device and the synchronous frequency conversion circuit shown in FIGS. 3 and 4, the horizontal deflection frequency fhdef0 can be made substantially constant for a plurality of sets of synchronous frequencies. Therefore, the horizontal deflection frequency fhdef0 of the CRT 17 becomes substantially constant with respect to a plurality of sets of synchronization frequencies, and the horizontal deflection circuit 22 only needs to synchronize with the frequency fhdef0, so that synchronization performance such as jitter performance is improved.

Moreover, in this case, the video signal S11 is only written and read from the frame memory 43 in dot units of the input video signal S12, and no processing such as interpolation or thinning is performed. Since it is not performed, the display quality hardly deteriorates.

FIG. 5 shows a configuration of a main part of the timing pulse generation circuit 54. That is, the horizontal counter 541 is configured by an up counter, and the read clock CLKR from the PLL 60 is supplied as a count input (clock input). Further, the reset terminal R of the counter 541 is set to “L” level, and the count enable terminal EN is set to “H” level.

Further, a value n TD (= “1”) obtained by subtracting “1” from the number of dots per horizontal period from the timing control circuit 53 is obtained.
nhscn + nhblk-1) is output, and this data is output to the counter 5 through the data terminal DATA of the counter 541.
It is preset to 41. Note that this preset is executed when the synchronization frequency of the input video signal S11 supplied to the terminal 11 changes. Also, the counter 541
It is assumed that the output terminal Q goes to the "H" level when the count value reaches the preset value nTD.

Therefore, the counter 541 operates at the clock CL
Counts KR and counts clock CL
Since it restarts every (nhscn + nhblk) pieces of KR,
The output terminal Q of the counter 541 outputs a pulse Ph having a pulse width of one clock period (one clock period of the clock CLKR) every time (nhscn + nhblk) clocks CLKR are counted. That is, the frequency of the pulse Ph is the horizontal synchronization frequency fhdef0 of the output video signal S13.

Then, the pulse Ph is supplied to the horizontal synchronizing signal forming circuit 542 to form a horizontal synchronizing signal Hout. The horizontal synchronizing signal Hout is supplied to the horizontal deflection circuit 21 as described above, and the CRT 17 operates at the frequency fhdef0. Horizontal deflection is performed.

The vertical counter 543 is constituted by an up counter, and a read clock from the PLL 60
CLKR is provided as a count input (clock input). Further, the reset terminal R of the counter 543 is “L”.
The pulse Ph from the counter 541 is supplied to the count enable terminal EN of the counter 543.

Further, a value nTL (== 1) obtained by subtracting “1” from the number of lines per one vertical period is obtained from the timing control circuit 53.
nvscn + nvblk-1) is output, and this data is output to the counter 5 via the data terminal DATA of the counter 543.
Preset to 43. Note that this preset is executed when the synchronization frequency of the input video signal S11 supplied to the terminal 11 changes. Also, the counter 543
Has a built-in decoder, and when its count value reaches a preset value nTL, the output terminal Q goes to "H" level.

Therefore, the counter 543 outputs the pulse Ph
The clock CLKR is counted every time, and the count is restarted every (nvscn + nvblk) pulses Ph. Therefore, from the output terminal Q of the counter 543, the pulse width becomes 1 every (nhscn + nhblk) pulses Ph.
A pulse Pv for a clock period (one clock period of the clock CLKR) is output. That is, the frequency of the pulse Pv is
The vertical synchronizing frequency fvdef0 of the output video signal S13 is used.

Then, the pulse Pv is supplied to the vertical synchronizing signal forming circuit 544 to form a vertical synchronizing signal Vout. The vertical synchronizing signal Vout is supplied to the vertical deflection circuit 24 as described above, and the CRT 17 has the frequency fvdef0. Performs vertical deflection. Although not shown, the timing signals S4W and S5W supplied from the timing pulse generation circuit 54 to the memory controller 55 include pulses Ph and Pv as signals indicating the timings of the output synchronization signals Hout and Vout. .

As described above, according to the display device and the synchronous frequency conversion circuit described above, a decrease in resolution and an increase in hardware do not occur as in the above method.
The horizontal deflection frequency fhdef0 does not greatly change from, for example, the NTSC signal of 15.75 kHz to 130 kHz or more for a high-performance workstation as in the case of the method (1).

However, as is clear from the equation (6), the horizontal deflection frequency fhdef0 has an error within the range of the reference frequency fref of the PLL 60, and changes within the range of the reference frequency fref. In other words, it does not realize a completely single horizontal deflection frequency, but is a narrow band but multi-scan. For this reason, although slightly, a frequency characteristic occurs in the horizontal deflection circuit, and the performance or characteristic as a display device is changed by the input video signal S11. When canceling this change in performance or characteristics, the number of components of the horizontal deflection circuit increases or adjustment is required.

The present invention has been made in view of the above points,
An object of the present invention is to provide a conversion circuit that does not convert the number of pixels and does not change the horizontal deflection frequency.

[0071]

According to the present invention, for example, a first forming circuit for forming a write control signal which changes in synchronization with a horizontal and vertical synchronizing signal in an input video signal; A memory into which an input video signal is written, a discrimination circuit for determining the horizontal and vertical synchronization frequencies of the input video signal, and a signal having a basic stable frequency, which synchronizes with the signal and determines the discrimination circuit A second forming circuit for forming a read control signal having a frequency that changes in accordance with the result; and forming a horizontal synchronizing signal synchronized with the signal and having a constant frequency from the basic stable frequency signal. Third
And a fourth forming circuit for forming a vertical synchronizing signal synchronized with the signal from the basic stable frequency signal and having a frequency that changes in accordance with the result of the discrimination by the discriminating circuit. Read the video signal written to the memory from the memory by the read control signal,
The read video signal, the horizontal synchronizing signal, and the vertical synchronizing signal are output as synchronizing frequency conversion circuits. Therefore, a video signal having a constant horizontal synchronization frequency is read from the memory regardless of the horizontal synchronization frequency of the input video signal.

[0072]

In FIG. 1, reference numeral 14 denotes an example of a synchronous frequency conversion circuit according to the present invention. Parts corresponding to those of the conversion circuit 14 in FIG. .

However, in the present invention, the PLL 60
The reference signal S64 from the forming circuit 64 is supplied to a frequency dividing circuit 66 and frequency-divided into a signal S66 of a predetermined frequency. The frequency-divided signal S66 is divided into a horizontal counter 541 and a vertical counter 543 as shown in FIG. Is supplied as a count input (clock input).

A constant value nhs is preset in the horizontal counter 541 by the timing control circuit 53 irrespective of the horizontal synchronization frequency of the input video signal S11.
Data of a value nTL that changes according to the horizontal and vertical synchronization frequencies of the input video signal S11 is preset. In addition,
At this time, nhs = fref / fhdef fhdef: horizontal deflection frequency of the CRT 17 The remaining portions of the counters 541 and 543 have the same configuration as that of FIG. Further, the entire display device is configured as described with reference to FIG.

According to such a configuration, the horizontal counter 5
41, a signal S66 of a constant frequency is supplied as a count input irrespective of the horizontal synchronization frequency of the input video signal S11, and its preset value is constant at a value of nhs. , A horizontal pulse Ph having a constant frequency fhdef is output regardless of the horizontal synchronization frequency.

The horizontal pulse Ph is supplied to a horizontal synchronization signal forming circuit 542 to form a horizontal synchronization signal Hout. The horizontal synchronization signal Hout is supplied to the horizontal deflection circuit 21 as shown in FIG. Frequency fhdef
Horizontal deflection is performed. Therefore, the horizontal deflection of the CRT 17 is constant regardless of the horizontal synchronization frequency of the input video signal S11.

At this time, the horizontal retrace period thblk0 on the CRT 17 is given by the following expression from the equation (7): thblk0 = nhblk / fclkr0 = nhblk / (int ((nhscn + nhblk). Although an error occurs between the actual horizontal retrace period thblk0 and the set horizontal retrace period, the PLL 6
By setting the reference frequency fref at 0 sufficiently low, the actual horizontal retrace period fhdef0 can be made substantially constant, and there is no practical problem.

On the other hand, a signal S66 having a constant frequency is supplied as a count input to the vertical counter 543 regardless of the horizontal synchronization frequency of the input video signal S11. Since it changes according to the vertical synchronization frequency, the vertical counter 543
Outputs a vertical pulse Pv having a frequency fvdef0 that changes according to the horizontal and vertical synchronization frequencies of the input video signal S11.

The vertical pulse Pv is supplied to the vertical synchronizing signal forming circuit 544 to form a vertical synchronizing signal Vout. This vertical synchronizing signal Vout is supplied to the vertical deflection circuit 24 as shown in FIG. Frequency fvdef
At 0, vertical deflection is performed.

Although not shown, the counter 54
1 and 543 are supplied to the timing pulse generation circuit 54 as signals indicating the phases of horizontal scanning and vertical scanning (for example, the start time), and are supplied from the timing pulse generation circuit 54 to the memory controller 55. The timing signals S4W and S5W include the pulses Ph and Pv as signals indicating the phases of the output synchronization signals Hout and Vout.

Thus, according to the above-described display device and synchronous frequency conversion circuit, a plurality of sets of synchronous frequencies are
The horizontal deflection frequency can be fixed at a constant value fhdef, that is, a single scan can be performed.
Therefore, the horizontal deflection circuit has no frequency characteristics, and the performance or characteristics of the display device does not change with the horizontal synchronization frequency of the input video signal S11. As a result, since a configuration for canceling a change in performance or characteristics is not required, the configuration of the display device is not complicated, the number of components is not increased, or adjustment is required. There is no.

Furthermore, even if the horizontal synchronizing frequency of the input video signal S11 changes while the display device is in use, the frequency of the horizontal drive pulse does not suddenly change. Become. Further, the response when controlling the main deflection and the high voltage changes depending on the horizontal deflection frequency. However, since the horizontal deflection frequency fhdef is constant, the design parameters can be easily set and there is no need to switch the parameters.

Further, since no interpolation or thinning is performed on the input video signal S11, the display quality does not deteriorate when text characters, graphics, and the like are displayed. Further, since a product-sum calculator required for the interpolation processing is not required, the degree of integration of the LSI can be reduced. Further, since it is not necessary to operate the product-sum operation unit at a very high operating frequency, it is not necessary to cope with such a frequency.

Further, since the phase relationship between the horizontal synchronization and the vertical synchronization in the output video signal S14 can be regulated,
Vertical jitter can be eliminated, and from this point the quality of the display screen can be improved.

In the above description, the input video signal S11
Is a general analog signal, for example, TMD
In the case of the S format or the LVDS format, the signal may be decoded into a general digital video signal in the interface circuit 13 or the like and then supplied to the frame memory 43. When the timing control circuit 53 is configured by a DSP, the timing control circuit 53 can also be used as a DSP for forming a distortion correction signal of the CRT 17.

Further, in the above description, the counter 541
Is an up counter, and when the count value reaches a preset value, the output terminal Q is set to “H” level. However, the counter 541 is set to a presettable down counter and the count value becomes “0”. And a decoder for detecting this. This is the same for the counter 543.

[List of abbreviations used in this specification] A / D: Analog to Digital CRT: Cathode Ray Tube D / A: Digital to Analog DSP: Digital Signal Processor FET: Field Effect Transistor LSI: Large Scale integration LVDS: Low Voltage Differential Signal NTSC: National Television System Committee PLL: Phase Locked Loop TMDS: Transition Minimized Differrential Signa
l VCO: Voltage Controlled Oscillator

[0088]

According to the present invention, the horizontal deflection frequency can be fixed at a constant value for a plurality of sets of synchronization frequencies. Therefore, the horizontal deflection circuit has no frequency characteristics, and the performance or characteristics of the display device does not change with the horizontal synchronization frequency of the input video signal. As a result, since a configuration for canceling a change in performance or characteristics is not required, the configuration of the display device is not complicated, the number of components is not increased, or adjustment is required. There is no.

Further, even if the horizontal synchronizing frequency of the input video signal changes during use, the frequency of the horizontal drive pulse does not suddenly change, so that there is no need to take measures against destruction of the frequency. In addition, the response when controlling the main deflection and the high voltage changes depending on the horizontal deflection frequency. However, since the horizontal deflection frequency is constant, the design parameters can be easily set and there is no need to switch the parameters.

Further, since no interpolation or thinning is performed on the input video signal, when displaying text characters, graphics, and the like, the display quality does not deteriorate. Further, since a product-sum calculator required for the interpolation processing is not required, the degree of integration of the LSI can be reduced. Further, since it is not necessary to operate the product-sum operation unit at a very high operating frequency, it is not necessary to cope with such a frequency.

Further, since the phase relationship between the horizontal synchronization and the vertical synchronization in the output video signal can be regulated, the jitter in the vertical direction can be eliminated, and from this point the quality of the display screen can be improved. .

[Brief description of the drawings]

FIG. 1 is a system diagram illustrating one embodiment of the present invention.

FIG. 2 is a system diagram showing one embodiment of a main part of the present invention.

FIG. 3 is a system diagram for explaining the present invention.

FIG. 4 is a system diagram for explaining the present invention.

FIG. 5 is a system diagram for explaining the present invention.

FIG. 6 is a timing chart for explaining the present invention.

[Description of Signs] 11 and 12: input terminals, 13: interface circuit, 14: synchronous frequency conversion circuit, 15: video control circuit, 16: video drive circuit, 17: color CRT, 21
... horizontal deflection circuit, 22 ... horizontal deflection coil, 23 ... high voltage generation circuit, 24 ... vertical deflection circuit, 25 ... vertical deflection coil,
42 ... A / D converter circuit, 43 ... Frame memory,
44: D / A converter circuit, 51: PLL, 52: signal discrimination circuit, 53: timing control circuit, 54: timing pulse generation circuit, 55: memory controller, 56
... PLL, 61 ... VCO, 62 ... variable frequency dividing circuit, 63 ...
Phase comparison circuit, 64 forming circuit, 65 loop filter, 66 frequency dividing circuit, 541 horizontal counter, 542
Horizontal synchronizing signal forming circuit, 543 ... vertical counter, 544
... Vertical synchronization signal forming circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C020 AA04 AA05 AA17 AA32 AA35 CA13 5C082 AA01 BB15 BB25 BC16 BC19 DA53 DA61 DA76 MM05

Claims (2)

[Claims] A first forming circuit for forming a write control signal which changes in synchronization with horizontal and vertical synchronizing signals in an input video signal; a memory in which the input video signal is written by the write control signal; A discriminating circuit for discriminating the horizontal and vertical synchronizing frequencies of a video signal, and a read control in which a signal is synchronized with the signal from a basic stable frequency signal and the frequency changes in accordance with the discrimination result of the discriminating circuit. A second forming circuit for forming a signal, a third forming circuit for synchronizing with the signal and forming a horizontal synchronizing signal having a constant frequency from the basic stable frequency signal; A fourth formation for forming a vertical synchronizing signal synchronized with this signal from a signal having a stable frequency and having a frequency that changes in accordance with the result of the discrimination by the discriminating circuit. A video signal written to the memory from the memory by the read control signal, and the read video signal, the horizontal synchronization signal, and the vertical synchronization signal are used as output signals. Synchronization frequency conversion circuit. 2. The synchronous frequency conversion circuit according to claim 1, wherein said second forming circuit has a PLL, and wherein said read control signal is formed from an output signal of said PLL. circuit.