KR20030082279A - multi-output system using variable clock - Google Patents

Abstract

PURPOSE: A multiple output system using a variable clock is provided to support various output formats at the same time by using the least variable clock source in a system compensating errors of input and output periods by using variable clocks. CONSTITUTION: A synchronous control signal generating unit(100) locks synchronization of a synchronous signal of a video signal with video signals inputted through bit streams for generating synchronous control signals of a plurality of output video formats. A variable clock source unit(200) varies an output frequency according to the generated synchronous control signals to synchronize and display the input video signal and the output video signal, so that the variable clock source unit outputs a control synchronous signal supporting operational clocks of the plurality of output video formats. A PLL(Phase Locked Loop)(300) synthesizes the operational clocks to match synchronization of the input video signal and the output video signal according to the varied control synchronous signal.

Description

Multi-output system using variable clock

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a format converting apparatus of a digital TV, and more particularly, to an apparatus for locking a multiple output video signal using a variable clock.

If the input video cycle is 59.94Hz and the output video cycle is 59.94Hz in the single input / output system, the cycles of the input / output video will be exactly matched if each signal is stable.

However, in actual cases, since the periods vary slightly due to various external conditions, it is common that the periods of the two signals do not coincide and distort as the period difference of the input / output signals accumulates.

As described above, in order to solve a problem in which output and input cycles do not match in a system that converts an externally input image into a desired format and outputs the image, the input image is sequentially stored in the memory while being outputted. It takes a way to control the order of the images.

However, this type of screen has a lot of annoyance in a dynamic image because output must be performed while skipping or repeating an input data frame.

In addition, the performance also depends on the size of the memory, so that the larger the size of the memory can obtain a good effect, the larger the size of the input image has the problem that the size of the memory must also be larger.

Therefore, when the input signal cycle is minutely changed in the signal having the same input / output cycle, the input / output cycle correction can be performed with a minimum amount of memory by interlocking the cycle of the output image according to the input cycle.

1 is a diagram illustrating a system using a general variable clock.

As shown in FIG. 1, an image processing unit 11 for processing an input image, an input / output period difference generation unit 13 for generating a cycle difference of a variable operation clock, and a variable clock cycle according to a format cycle of an image are controlled. A synchronous control signal generator 10 having a synchronous signal generator 12 for outputting a synchronous signal, a loop filter 21 for outputting an analog level signal by filtering the generated periodic difference, and a filtered analog level Correspondingly, the variable clock source unit 20 having a VCXO 22 for varying the output frequency and outputting a reference clock coincides with the synchronization of the input video signal and the output video signal according to the variable reference clock. It consists of a PLL 30 which is synthesized with an operation clock for making it work.

As described above, the variable clock source unit 20 uses a voltage controlled crystal oscillator (VCXO) 22, which reflects the difference between the input and output of the output signal of the input / output period difference generator 13. The output clock period of the VCXO 22 is adjusted by inputting the average value of the pulse signal to the VCXO 22.

The clock thus adjusted is synthesized into an operation clock through a phase locked circuit (PLL) 30 and input to the synchronous control signal generator 10.

In addition, since the output cycle of the system is changed due to the period of the operation clock which is changed as described above, the input / output cycle difference is corrected.

However, in the system having two or more output image formats as shown in FIG. 2, each independent variable clock source unit 20a or 20b needs to be supported by the number of output formats, so that the system according to the variable clock source unit 20a or 20b is provided. Increasing and resulting in additional costs.

In addition, since the variable clock source units 20a and 20b must be controlled by obtaining the respective period differences, the complexity of the system also increases as the number of output formats increases.

Therefore, we need a way to achieve the same effect with a minimum amount of system resources.

The present invention has been made to solve the above problems, and an object thereof is to provide a multiple output system supporting various output formats for the same input image with a minimum variable clock.

1 is a diagram illustrating a system using a general variable clock.

2 is a diagram illustrating a multiple output system using a general variable clock.

3 is a diagram illustrating a multiple output system sharing a variable clock according to the present invention.

4 (a) is a diagram showing an output center vertical synchronizing signal according to the present invention;

4 (b) shows an output variable vertical synchronization signal according to the present invention.

5 is a diagram showing the structure of a variable synchronization signal generator according to the present invention;

6A and 6B illustrate a method of controlling a period of a horizontal / vertical synchronization signal according to the present invention.

* Explanation of symbols for main parts of the drawings

100: synchronization control signal generator 110: image processing unit

120: center synchronization signal generation unit 130: input and output period difference generation unit

140: variable synchronization signal generation unit 141: control mode determination unit

142: variable range determination unit 143: variable synchronization determination unit

150: output period difference generation unit 200: variable clock source unit

210: loop filter 220: VCXO

300: PLL

A feature of the multiple output system using a variable clock according to the present invention for achieving the above object is to lock the synchronization of the video signal and the video signal input through the bit stream (lock) of the plurality of output video formats A synchronous control signal generator for generating a synchronous control signal, and an output frequency is varied according to the generated synchronous control signal so that the input video signal and the output video signal are displayed in synchronization to support operation clocks of a plurality of output video formats. A phase locked loop (PLL) for synthesizing a variable clock source for outputting a control synchronization signal and an operation clock for synchronizing the synchronization of an input video signal and an output video signal according to a control synchronization signal varied by the variable clock source It is configured to include.

According to another aspect of the present invention, the image processing unit outputs an image according to a variable clock after processing the input image of the synchronous control signal generator, and compares the synchronous signal of the input image with the synchronous signal of the output image. An input / output period difference generation unit for generating a period difference of the operation clock, a center synchronization signal generation unit for feeding back the generated period difference and outputting a center synchronization signal according to a format period of a first image, and the output center synchronization An output period difference generation unit for generating a period difference between a signal and a variable synchronization of another output format, and a period of a variable clock according to a format period of a second image by using the period difference generated by the output period difference generation unit. And a variable sync signal generator for outputting a variable sync signal controlled by the controller.

In accordance with still another aspect of the present invention, a control mode determining unit may select a variable period control mode by receiving a difference between the output period calculated by the output period difference generator and system information, and the host. A variable range determination unit that determines a variable range that is a width of a predetermined variable period by using the period difference reference point information and the output period difference that are input from the control unit, and the variable period control mode selected by the control mode determination unit and the variable range determination unit And a variable synchronization determiner for generating an output variable period according to a variable range.

Another feature of the present invention is that the variable period control mode selected by the control mode determiner is selected from one of a period control mode of horizontal synchronization and a period control mode of vertical synchronization.

Another feature of the present invention is to convert the synchronization signal period in the variable range determiner by increasing or decreasing a blank period.

According to still another aspect of the present invention, a loop filter outputs an analog level signal by performing low pass filtering on the period difference generated by the input / output period difference generation unit, and a low pass filtered analog level by the loop filter. Correspondingly, it is configured to include a VCXO for varying the output frequency and outputting a reference clock.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

A preferred embodiment of a multiple output system using a variable clock according to the present invention will be described with reference to the accompanying drawings.

3 is a diagram illustrating a multiple output system sharing a variable clock according to the present invention.

3 illustrates a case in which two output formats for a single input image are two embodiments for the sake of simplicity, and the case in which three or more output formats are provided may be solved by the same method as described below.

3, a synchronization control signal generator 100 for locking a synchronization of a vertical synchronization signal of a video signal and a video signal input through a bit stream to generate a synchronization control signal of a plurality of output video formats; A control synchronization signal for supporting an operation clock of a plurality of output image formats by varying an output frequency according to a synchronization control signal generated by the synchronization control signal generator 100 so that the input image signal and the output image signal are displayed in synchronization. A phase locked loop for synthesizing an operation clock for synchronizing the synchronization of the input video signal with the output video signal according to a control synchronization signal that is variable in the variable clock source unit 200. PLL) 300.

In this case, the synchronization control signal generator 100 processes the input image and outputs the image according to a variable clock, and the vertical synchronization signal of the input image and the vertical synchronization signal of the output image. Input / output period difference generation unit 130 for generating a periodic difference of the operation clocks by comparing the signals, and a center difference according to the format period of the first image by feeding back the period difference generated by the input / output period difference generation unit 130. A center synchronous signal generator 120 for outputting a synchronous signal, an output cyclic difference generator for generating a cyclic difference between the central synchronous signal output from the center synchronous signal generator 120 and a variable synchronous synchronization in another output format 150 and a variable synchronization signal for outputting a variable synchronization signal controlled by a period of a variable clock according to a format period of a second image using the period difference generated by the output period difference generation unit 150. It is composed of a generation unit 140.

In addition, the variable clock source unit 200 performs a low pass filtering on the period difference generated by the input / output period difference generation unit 130 to output an analog level signal, and the loop filter 210. The VCXO 220 outputs a reference clock by varying the output frequency in response to the low pass filtered analog level.

The PLL 300 synthesizes and outputs an operation clock for synchronizing the input video signal with the output video signal according to the variable reference clock of the VCXO 220.

In this case, the input / output period difference generation unit 130 and the center synchronization signal generation unit 120 for controlling the variable clock source unit 200 must exist as many as the number of the variable clock source units 200.

The number of the variable clock source units 200 is determined according to whether the operation clock of the PLL 300 can be synthesized. For a widely used output format, a single variable clock (usually 27 MHz) output from the VCXO 220 is used. All can be supported.

Therefore, the output synchronizing signal controlled by the period of the variable clock output from the central synchronizing signal generating unit 120 is a central synchronizing signal, and the basic format of the output format cycle control is different from the image format output by the central synchronizing signal. do.

In addition, the center sync signal generator 120 and the input / output period difference generator 130 generally have the same configuration and effect as in the case of FIG. 1.

The variable sync signal generator 140 compares the center sync output from the center sync signal generator 120 with the vertical sync signal of another output image and generates an output period of a variable operation clock. It is controlled by the vehicle generating unit 150.

The operation of the output period difference generator 150 is illustrated in FIGS. 4A and 4B.

In general, since the center synchronizing signal and the variable synchronizing signal share the same clock source, the periods of the mutual synchronisms coincide with each operating clock.

However, as shown in FIG. 4 (a) (b), the instantaneous center is caused by the time delay of synthesizing the operating clock through the PLL, which occurs when the operating clock is changed due to long-term error accumulation of the PLL or conversion of the output format. The period and the variable period are distorted. If this case is repeated several times, the phases between the output synchronization signals will be completely out of phase.

Fig. 4A shows the output center vertical synchronizing signal, and Fig. 4B shows the output variable vertical synchronizing signal.

Reference numerals X and Y denote output period differences. When the output period difference is 0, X is a case where the polarity of the output period difference is negative and Y is a case where the polarity of the output period difference is positive. . This represents the position of the variable sync with respect to the center sync, and the periodic difference represents the distance difference from the reference point of the center sync (falling time in FIG. 4).

4 (a) and 4 (b), when a difference occurs between the output center vertical synchronization signal and the output variable vertical synchronization signal, the output periodic difference generator 150 outputs the center vertical synchronization signal and each variable vertical synchronization. Calculate the difference with the signal.

The period difference between the center synchronization signal calculated by the output period difference generator 150 and the respective variable synchronizations is input to the variable synchronization signal generator 140 generating each variable synchronization signal.

In this case, the structure of the variable synchronization signal generator 140 is illustrated in FIG. 5.

5, a control mode determination unit 141 for selecting a variable period control mode by receiving a difference between output periods calculated by the output period difference generation unit 150 and system information input from a host, A variable range determiner 142 that determines a variable range that is a width of a predetermined variable period by using the difference between the periodic reference point information input from a host and the output period, and the variable selected by the control mode determiner 141. The variable synchronization determiner 143 generates an output variable period according to the period control mode and the variable range determined by the variable range determiner 142.

In this case, the variable period control mode selected by the control mode determiner 141 may be divided into a horizontal control period control mode and a vertical synchronization period control mode.

The horizontal and vertical synchronous signal period control modes have advantages and disadvantages, and since the periodic change using the vertical synchronous signal is performed on a line basis, the relative convergence speed is high, but fine control is difficult, while the cyclic change of the horizontal synchronous signal is reversed. The convergence rate is slow but fine control (one pixel per line down) is possible.

The variable range determination unit 142 may vary the period of the synchronization signal according to the control mode, but both horizontal and vertical synchronization signals may be used to define a blank section defined when the image is displayed on the screen. Adjust by increasing or decreasing.

The blank period means an inactive section of data in the case of a synchronization signal for digital device display, and a deflection section in the case of a synchronization signal for analog device display.

The reason why the blank section is adjusted is a digital display device, for example, a plasma display panel device, since only a valid data section is input as a synchronization signal, regardless of a blank width, and in the case of an analog display device, HD quality In the case of video, the total number of pixels and the number of lines in a frame is much larger than that of existing broadcasts. Therefore, the distortion of the screen is caused by the change of several pixels in the horizontal sync blank section or 1 or 2 lines in the vertical sync blank section. It does not occur.

However, in the case of the analog display type low resolution video format, it may be very sensitive to such blank period variation, so it is recommended to set the low resolution output format as the central synchronization signal of the system and control it directly by the clock cycle variation by the variable clock source. good.

The system information applied from the host is information such as a display type and an image format.

As described above, the horizontal / vertical synchronization period control method is not possible to perform finer period control than the clock period change method. However, the control mode determiner 141 is externally applied. Through the system information and the output period difference, the variable period control mode is selected from the period control mode of horizontal synchronization and the period control mode of vertical synchronization.

When the control mode is selected by the control mode determiner 141, the variable range determiner 142 determines a variable range, wherein the variable range is set by the user based on the selected control mode and the output period difference. You must decide accordingly.

In this case, the periodic difference may be maintained at a specific value other than 0. When the periodic difference reaches its position, the variable range may be set to 0 after receiving information about a desired position (periodic difference reference point).

Finally, the variable synchronization determiner 143 generates an output variable period according to the control mode set by the determiner 141 and the variable range set by the variable range determiner 142. This method is illustrated in FIGS. 6A and 6B.

6A illustrates a method of controlling a period of a horizontal synchronization signal. As shown in FIG. 6A, when the output period difference is negative, the blank width is increased by A by the pixel determined as the variable range, and the output period difference is (+). ), On the contrary, decreases by B.

FIG. 6B illustrates a method of controlling the period of the vertical synchronization signal, similar to the horizontal synchronization method as shown in FIG. 6B. That is, when the output period difference is (-), the blank width is increased by C by the line determined by the variable range, and when the output period difference is (+), it is decreased by D on the contrary.

In this case, in the method of controlling the period of the vertical synchronization signal, in the case of the analog display, it is preferable to limit the variable range to about 1 to 2 lines in consideration of the effect on the screen.

As described above, the multiple output system using the variable clock according to the present invention may simultaneously support various output formats using a minimum variable clock source in a system that compensates for an error in an input / output period using a variable clock. In particular, it can be effectively applied to a device using various output modes such as digital TV.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (7)

A synchronous control signal generator for locking the synchronous signal of the video signal and the video signal input through the bit stream to generate a synchronous control signal of a plurality of output video formats; A variable clock source unit for outputting a control synchronization signal for supporting operation clocks of a plurality of output image formats by varying an output frequency according to the generated synchronous control signal so that the input image signal and the output image signal are synchronized and displayed; And a phase locked loop (PLL) for synthesizing an operation clock for synchronizing the synchronization of the input video signal with the output video signal according to the control synchronization signal variable in the variable clock source unit. Multiple output system. The method of claim 1, wherein the synchronous control signal generator An image processor which processes an input image and outputs an image according to a variable clock; An input / output period difference generation unit configured to generate a period difference of an operation clock that is varied by comparing a synchronization signal of an input image and an output signal of an output image; A center sync signal generator for feeding back the generated difference to output a center sync signal according to a format cycle of a first image; An output period difference generation unit for generating a period difference between the output center synchronization signal and a variable synchronization of another output format; And a variable synchronization signal generation unit configured to output a variable synchronization signal controlled by a period of a variable clock according to a format period of a second image using the period difference generated by the output period difference generation unit. Multiple output system using clock. The variable synchronization signal generator of claim 2, wherein A control mode determiner configured to select a variable period control mode by receiving a difference between the output period calculated by the output period difference generator and system information; A variable range determination unit that determines a variable range that is a width of a predetermined variable period using period difference reference point information and an output period difference input from the host; And a variable synchronization determiner for generating an output variable period according to the variable period control mode selected by the control mode determiner and the variable range determined by the variable range determiner. The method of claim 3, wherein The variable period control mode selected by the control mode determiner is selected from one of a period control mode of horizontal synchronization and a period control mode of vertical synchronization. The method of claim 3, wherein The conversion of the synchronization signal period in the variable range determination unit converts by increasing or decreasing the blank interval (multiple output system) using a variable clock. The method of claim 5, wherein the conversion of the blank interval A multi-output system using a variable clock, wherein the variable period control mode is converted in units of pixels when the period control mode of horizontal synchronization is performed, and in units of lines when the period control mode of vertical synchronization is performed. The method of claim 1, wherein the variable clock source unit A loop filter for outputting an analog level signal by low pass filtering the period difference generated by the input / output period difference generator; And a VCXO for varying an output frequency in response to the low pass filtered analog level in the loop filter and outputting a reference clock.