JPH0720809A - Digital convergence correction device and image display device using it - Google Patents

Abstract

PURPOSE:To deal with every display signal and to simplify circuit constitution without switching characteristic of an LPF used for smoothing a correction waveform in a device by equalizing reading time intervals of correction data from a memory regardless of a scanning frequency of an input signal, in a convergence correction device for a multiscan display device. CONSTITUTION:This device is constituted so that a system clock with the same frequency is supplied from a synchronism oscillator 10 always to an address counter 20 generating a read address of the convergence correction data for the memory 30 regardless of the scanning frequency of the input signal and the address is generated, and the convergence correction data are read out at a fixed time interval regardless of the scanning frequency of an inputted display signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence correction device used for an image display device such as a color television receiver using a CRT (cathode ray tube), a display terminal, etc., and more particularly to a video signal to be displayed. The present invention relates to a digital convergence correction device suitable for a multi-scan type image display device that can be handled by the same device even when the scanning frequency is switched.

[0002]

2. Description of the Related Art As a conventional digital convergence correction apparatus, for example, one described in Japanese Patent Laid-Open No. 3-68296 is known. In such a conventional digital convergence correction device, the horizontal blanking signal and the vertical horizontal blanking signal of the video signal to be displayed are set to P
This is taken into LL (face locked loop circuit), a reference clock synchronized with it is generated, and various timing signals are generated using this clock.

As a timing signal to be generated, a signal supplied as an address clock to an address generation circuit for generating a read address for the memory in which the convergence correction data is written, or an X signal supplied to the crosshatch generation circuit. There is a row Y column signal.

[0004]

In the above-mentioned conventional digital convergence correction apparatus, based on the reference clock generated in synchronization with the synchronizing signal of the video signal to be displayed,
Generate a read address, read the convergence correction data from the memory at the read address,
The read correction data is D / A converted, the obtained analog signal is smoothed by an LPF (low-pass filter), and then the convergence correction is performed.

Such a conventional configuration is only considered when the scanning frequency of the video signal to be displayed is limited to a single scanning frequency, and the scanning frequency is switched to another frequency (for example, the video signal. There is a switch from the one for the TV to the one for the PC), but did not consider the case.

Therefore, in the conventional digital convergence correction device, when the scanning frequency of the video signal to be displayed is switched, one horizontal cycle is generated under the condition that the frequency dividing ratio of the frequency dividing circuit forming the PLL is constant. The number of addresses remains constant even if the frequency changes, and the output intervals of the correction data are almost equal on the screen. However, since the scanning frequency changes, the temporal output interval changes depending on the horizontal frequency.

FIG. 3 is an explanatory view showing the function of the LPF in the digital convergence circuit (function of converting a jagged analog signal obtained by D / A conversion of correction data into a smooth signal). That is, in the digital convergence correction circuit, the correction data read from the memory is D / A converted, and after being converted into a smooth waveform by the LPF,
Convergence correction is performed with this waveform. (A) in Fig. 3 shows an example of a jagged output waveform obtained by D / A conversion, and (b) in Fig. 3 passes this to the LPF. 3 shows a waveform (correction waveform) of a smooth signal obtained after the above.

The cutoff frequency of the LPF must be sufficiently lowered in order to obtain a sufficiently smooth correction waveform free of vibrations (jagged edges). On the other hand, from the viewpoint of reducing the influence of the correction data on each other, the cutoff frequency cannot be lowered so much. Therefore, as seen in the above-mentioned conventional digital convergence correction device, when the time interval of the correction data changes, the characteristics of the LPF also have to be changed accordingly, resulting in a complicated hardware configuration. There was a problem.

The object of the present invention is to overcome the problems of the prior art, and even if the scanning frequency of the video signal to be displayed is switched to another frequency, there is no need to change the characteristics of the LPF accordingly. The object of the present invention is to provide a digital convergence correction device whose hardware configuration is simpler, and an image display device incorporating such a correction device.

[0010]

To achieve the above object, in the present invention, in a digital convergence correction apparatus, a constant frequency (always synchronized with a video signal is used regardless of the horizontal frequency of the video signal to be displayed. The clock generating means for generating the reference clock of 1) as the system clock is provided, and the address counter is operated based on the system clock to generate the read address.

[0011]

Since the address generation cycle is the same regardless of the horizontal frequency of the video signal to be displayed, the time interval of the correction data is always constant. Therefore, it is not necessary to change the characteristics of the LPF. Therefore, the system configuration is simple and easy.

[0012]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a configuration diagram showing a first embodiment of the present invention, and shows a case where the digital convergence correction apparatus according to the present invention is applied to a projection television receiver.

In FIG. 1, reference numeral 10 denotes a synchronous oscillator (which operates in synchronization with a horizontal synchronizing signal of a video signal to be displayed on the screen, but its oscillation frequency is constant regardless of the scanning frequency of the video signal to be displayed. Synchronous oscillator that generates a clock)
The horizontal synchronization signal HD is received from the drive circuit (deflection circuit) 90 of the display device, and the horizontal synchronization signal HD is received based on the received horizontal synchronization signal HD.
It is a circuit for generating a system clock which is always constant and irrespective of the frequency of, and which is synchronized with the horizontal synchronizing signal HD.

FIG. 2 is a circuit diagram showing a configuration example of the synchronous oscillator 10. As seen in FIG. 2, the synchronous oscillator 10
Is composed of a NOR gate 11, an inverter 12, a resistor 13, a coil 14, and a capacitor 15. I / O terminal 1
Reference numerals 50 and 200 correspond to the signal lines having the same numbers in FIG. Although FIG. 2 shows an example of the resonance type oscillator,
It is also possible to use a crystal or ceramic oscillator.

Returning to FIG. 1, 20 is an address counter, which generates a memory address (readout address) synchronized with screen scanning based on the output 200 of the synchronous oscillator 10. Reference numeral 160 is a VD (vertical synchronization signal). Reference numeral 30 denotes a memory that stores convergence correction data, and adjustment can be performed by rewriting the stored correction data from the CPU 80. Address counter 2 when not adjusting
The stored correction data is read according to the output address of 0.

Reference numeral 40 is a D / A converter, which converts the digital data output from the memory 30 into an analog voltage. Reference numeral 50 is an LPF (low pass filter) that smoothly smoothes the output 170 of the D / A converter 40.
Reference numeral 60 denotes a CY amplifier that converts the LPF output 180 into a current that drives a CY (convergence yoke) 110.

Memory 30, D / A converter 40, LPF5
A convergence correction unit 70 composed of 0 and CY amplifier 60 is required for each channel for convergence adjustment. Besides, 80 is a CPU, and the memory 3
Data control (adjustment) of 0 is performed. Reference numeral 90 denotes each drive circuit of the projection television receiver, which includes a deflection circuit, a high voltage circuit,
In addition to the convergence circuits such as the video circuit, tuner circuit, and focus circuit, the CRT (Cathod Ray
Tube) 120 and all circuits necessary for driving the deflection yoke 100.

Reference numeral 110 denotes a CY driven by the CY amplifier 60.
(Convergence Yoke), which generates a correction magnetic field corresponding to the input voltage 180 of the CY amplifier 60. A screen 130 projects an image on the tube surface of the CRT 120. Although an optical system actually exists between the CRT 120 and the screen 130, it is omitted here. 140
Is a video signal input to be displayed, such as NTSC, HD, VGA or the like. At the time of convergence adjustment, the adjuster gives a command to the CPU 80 while monitoring the screen to rewrite the contents of the memory 30.

According to the present embodiment, the correction data is read from the memory 30 at a constant time interval regardless of the scanning frequency of the input display signal (video signal to be displayed), so that the characteristics of the LPF 50 can be changed. The hardware configuration is simple because there is no need to change it according to the scanning frequency of. Further, unlike the PLL, it is not necessary to change the characteristics of the system clock generation circuit according to the frequency of the input signal. Further, in general, a display signal having a long horizontal scanning period has a small number of scanning lines.

Therefore, according to the present embodiment, the number of correction data in one horizontal scanning period increases as the display signal has a longer horizontal scanning period, so that the capacity of the memory 30 for each display signal can be kept substantially constant. is there.

FIG. 4 is a block diagram showing a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is the part of the memory configuration. In FIG. 4, the same numbers as those in FIG. 1 represent the same items, and thus the description thereof will be omitted.

Referring to FIG. The memory 31 is the first memory, and reads the correction data at equal time intervals with the output address of the address counter 20. 32 is the second
And stores correction data for one screen (when a display signal having a certain scanning frequency is input) in a certain mode. Reference numeral 81 denotes a correction data conversion means, which corrects (converts) the correction data in the second memory 32 according to the scanning frequency of the input signal and expands it in the first memory 31. Here, the CPU is also used as the correction data conversion means 81. Of course, it is also possible to install each independently.

FIG. 5 is an explanatory view showing the operation of the correction data converting means 81 in FIG. Even if the scanning frequency of the input display signal (video signal to be displayed) basically changes, in the present invention, since the correction data is output from the memory at a constant time interval, the position where the correction data is output is reversed. The interval (physical position interval on the screen) changes each time (each time the scanning frequency changes).

A square indicated by 300 in FIG. 5 represents the output position of the correction data of a certain mode (scanning frequency), that is, the output position of the correction data stored in the memory 32 on the screen and the correction data. . Further, a circle indicated by 400 represents the relationship between the correction data output position and the correction data output position (when a display signal of another scanning frequency is input) in another mode.
Since the screen positions are different, the correction data values are different, and the position 400 is different depending on the input display signal. Therefore, the correction data conversion means 81 is used to perform an interpolation calculation, and the value is written in the memory 31 to cope with the problem.

Basically, in FIG. 4, the memory 32 needs to store the correction data necessary for the correction of the entire screen in a certain mode, and the correction data used as the basis for creating the correction data necessary for the correction of the entire screen. . Further, the memory 32 may be a line memory that stores all the correction data for one scanning line if the correction data conversion unit 81 is sufficiently fast, but if not, a frame memory that stores the correction data for one screen. Must be

According to the present embodiment shown in FIG. 4, since the correction data is read from the memory 31 at regular time intervals regardless of the scanning frequency of the input display signal, the LPF 50 is read.
The characteristic of does not need to be changed according to the scanning frequency of the input signal, and the hardware configuration is simple. Also, PLL
As described above, it is not necessary to change the characteristics of the system clock generation circuit according to the scanning frequency of the input signal. Further, since the correction data for one display signal having a certain scanning frequency can be used for a plurality of display signals having different scanning frequencies, the adjustment work can be simplified.

FIG. 6 is a block diagram showing the third embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is the generation of the system clock. In FIG. 6, the same reference numerals as those in FIG. 1 represent the same items, and thus the description thereof will be omitted.

In FIG. 6, reference numeral 15 is a PLL for generating a system clock. Reference numeral 16 is a frequency division ratio setting means for switching the frequency division ratio of the frequency division circuit constituting the PLL 15 according to the scanning frequency of the display signal (video signal to be displayed). The frequency division ratio setting means 16 operates to set the frequency division ratio such that the system clock frequency output from the PLL 15 is substantially constant regardless of the scanning frequency of the display signal.

According to this embodiment, since the correction data is read from the memory 30 at a constant time interval regardless of the scanning frequency of the input display signal, the characteristics of the LPF 50 are changed according to the scanning frequency of the input signal. There is no need, and the hardware configuration is simple. Further, it is not necessary to change the characteristics of the VCO (variable voltage oscillator) that constitutes the PLL according to the scanning frequency of the input signal.

[0030]

According to the digital convergence correction apparatus of the present invention, in the multi-scan type image display apparatus, the convergence correction data stores it at a constant time interval regardless of the scanning frequency of the input display signal. Since it is read from the memory, there is no need to change the characteristics of the LPF according to the scanning frequency of the display signal, and there is an advantage that the hardware configuration is simple.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a synchronous oscillator in FIG.

FIG. 3 is an explanatory diagram showing the function of the LPF in the digital convergence circuit.

FIG. 4 is a configuration diagram showing a second embodiment of the present invention.

FIG. 5 is an explanatory diagram showing the operation of the correction data conversion means in FIG.

FIG. 6 is a configuration diagram showing a third embodiment of the present invention.

[Explanation of symbols]

10 ... Synchronous oscillator, 20 ... Address counter, 30 ... Memory, 40 ... D / A converter, 50 ... LPF, 60 ... CY
Amplifier, 70 ... Convergence correction unit, 80 ... C
PU, 90 ... Driving circuit, 100 ... Deflection yoke, 110 ...
CY, 120 ... CRT, 130 ... screen

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H04N 9/28 A 9187-5C (72) Inventor Kuninori Matsumi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Image Information Systems Co., Ltd. (72) Inventor Tomoharu Nagiri 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture

Claims (5)

[Claims] 1. A memory for storing convergence correction data, an address counter for generating a read address for the memory in synchronization with screen scanning, and a convergence read from the memory by a read address generated by the address counter. A D / A converter for inputting correction data and converting it to an analog voltage for output, a low-pass filter for converting the analog voltage output from the D / A converter to a smooth convergence correction waveform and outputting the same, and the low-pass filter Convergence correction including an amplifier that outputs an output voltage as a convergence correction waveform from a filter and converts the output voltage into a current, and a convergence yoke that is driven by the output current from the amplifier and generates a correction magnetic field according to the current. On the device, Regardless scanning frequency of the video signal should exhibit,
By providing a system clock generating means for always generating a system clock of a constant frequency in synchronization with screen scanning, and the address counter for receiving the system clock from the generating means and generating the read address, A digital convergence correction device characterized in that the output time interval of the convergence correction data from the memory is always constant regardless of the scanning frequency of the video signal to be displayed on the screen. 2. The digital convergence correction apparatus according to claim 1, wherein when the memory for storing the convergence correction data is the first memory, the convergence correction data for one screen of a video signal having a certain scanning frequency is used. And a correction data read from the second memory are corrected and converted into correction data suitable for the second memory according to the scanning frequency of the video signal to be displayed on the screen. When the scanning frequency of the video signal to be displayed on the screen is switched, the convergence correction data to be written in the memory is further corrected and converted.
A digital convergence correction device characterized in that the convergence correction data corresponding thereto is used. 3. An image display device, comprising: performing convergence correction on a display screen using the digital convergence correction device according to claim 1. 4. The digital convergence correction device according to claim 1, wherein the system clock generating means operates in synchronization with a horizontal synchronizing signal of a video signal to be displayed on the screen, but its oscillation frequency is displayed. A digital convergence correction device comprising a synchronous oscillator that generates a constant clock regardless of the scanning frequency of the video signal to be reproduced. 5. The digital convergence correction device according to claim 1, which operates in synchronization with a horizontal synchronizing signal of a video signal to be displayed on a screen, the oscillation frequency of which is
A digital convergence correction apparatus, characterized in that the system clock generating means is composed of an oscillator composed of a PLL and frequency division ratio switching means so as to generate a constant clock regardless of the scanning frequency of a video signal to be displayed.