JP2699305B2 - n-speed scanning television receiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a television receiver for performing double-density scanning by converting a video signal to a double speed using a digital circuit.
Particularly, the present invention relates to a television receiver suitable for a case where there are two input signals, a standard signal and a double speed signal, as input signals. [Prior Art] The standard television broadcasting system in Japan employs an interlaced scanning system. This is a method in which one screen (frame) is composed of two coarse screens (fields). Since the entire screen is repeated every 1/60 second, large area flicker is not so noticeable. However, in the part where the scanning line structure is worrisome or the luminance changes greatly in the vertical direction, line flicker occurs every 1/30 second,
These are causes of image quality deterioration. Therefore, as a method of reducing the image quality deterioration due to these disturbances, there is known an apparatus which displays a screen by increasing the number of scanning lines in one field to n times the normal number. Generally, n is 2, so that the following explanation is made on the assumption that n = 2. Conventionally, a circuit as shown in FIG. 6 has been known as a synchronization generating circuit used in this device. In FIG.
42 is a normal horizontal synchronizing signal input terminal, 43 is a double speed horizontal synchronizing signal generating circuit, 44 is a double speed horizontal synchronizing signal input terminal, 45 is a double speed horizontal deflection circuit, and 46 is a double speed horizontal output. Next, the operation will be described. First, when the normal horizontal synchronization is input, the double speed horizontal synchronization generation circuit 43 generates a double speed horizontal synchronization having a half cycle of the normal horizontal synchronization. The generated double-speed horizontal synchronization is input to a double-speed horizontal deflection circuit 45 to output a double-speed horizontal output signal 46 to perform horizontal scanning at double speed. Considering a double-speed RGB signal as an input signal, a double-speed horizontal synchronization signal is input together with this signal.When the double-speed horizontal synchronization 44 is input, the switch is switched to directly input the double-speed horizontal deflection circuit 45. Thus, a double-speed horizontal output signal 46 is output. Here, the double-speed horizontal synchronization generation circuit 43 and the double-speed horizontal deflection circuit
45 will be described. In FIG. 7, (a) shows a double-speed horizontal synchronization generating circuit 43, (b) shows a double-speed horizontal deflection circuit 45, 47 is a phase comparator, and 48 is a low-pass filter (LP).
F) and 49 are a voltage controlled oscillator (VCO), 50 is a 2 frequency divider, and 51 is a flyback transformer. As shown, the double-speed horizontal synchronization generation circuit 43 is a phase synchronization circuit that inputs the normal horizontal synchronization 42 and outputs the double-speed horizontal synchronization signal 44, and the double-speed horizontal deflection circuit 45 receives the double-speed horizontal synchronization 44 and Horizontal output 46
Is output from the phase locked loop. Therefore, when double-speed horizontal synchronization is input as an input signal, double-speed horizontal synchronization is directly input to the deflection circuit and horizontal scanning is performed as in a normal television receiver, but normal horizontal synchronization is input. In this case, horizontal scanning is performed in such a manner that a two-stage phase synchronization circuit of a double-speed horizontal synchronization generation circuit and a double-speed horizontal deflection circuit is connected in cascade. Japanese Patent Application Laid-Open No. 57-152279 is related to this type of apparatus. [Problem to be Solved by the Invention] In the above-described conventional technology, when the input signal is double-speed horizontal synchronization, the circuit configuration is different from that of a normal television receiver only in that the horizontal scanning frequency is doubled. There is no particular problem because it does not change. However, when normal horizontal synchronization is input, a phase synchronization circuit called a double-speed horizontal synchronization generation circuit is added to the circuit configuration when double-speed horizontal synchronization is input, so that synchronization is performed like a normal TV signal. It is good for a stable signal, but when a signal containing noise or a signal containing skew such as a VTR is input, there is a problem that the phase error response is deteriorated. Here, the phase error response will be described. In FIG. 8, (a) shows a screen of a normal television receiver, and (b) shows a screen of a double-density scanning television receiver having a circuit configuration similar to that of the conventional example. Skew etc. does not actually appear on the screen because it occurs within vertical blanking, but if response is poor, it appears up to the top of the screen,
It is also seen on the screen during special playback such as VTR. Now, for the sake of simplicity, the screen is displayed when a signal whose horizontal synchronization phase is suddenly changed near the center of the screen is input as a signal. In (a), the phase error response in the horizontal deflection circuit is The signal appears on the screen as it is, but in (b), a signal to which a phase error response in the double-speed horizontal synchronization generating circuit is added as shown by the broken line appears on the screen. In other words, in (b), the phase-locked loop is connected in cascade in two stages, so that the first-stage phase-locked loop follows the input and the output of the second-stage phase-locked loop follows. The output when you do this will appear on the screen. Therefore,
(B) has a worse phase error response than (a). Also, since there are two stages of phase locked loops, the circuit and the adjustment have to be doubled. An object of the present invention is to provide a similar tracking capability when a normal horizontal sync is input as an input signal and also when a double-speed horizontal sync is input, and a phase error when a normal horizontal sync is input. The goal is to improve the response. It is another object of the present invention to simplify circuits and adjustments. [Means for Solving the Problems] The object of the present invention is to store a signal of an input first video signal over one horizontal period and read out the signal at n times the speed at which the signal was stored (n is an integer of 2 or more). Using a memory circuit,
Signal conversion means for converting the first video signal into a second video signal having a 1 / n horizontal period, and a horizontal deflection processing section having an n-fold horizontal scanning frequency for displaying the second video signal In the television receiver having the following, the horizontal deflection processing section comprises: a phase comparator to which one input terminal is inputted with a synchronization signal related to the first video signal as a reference; and an output of the phase comparator. A voltage-controlled oscillator whose oscillation frequency is controlled by the output of the filter; and a 1 / n horizontal period of the first video signal by dividing the output of the oscillator. First frequency dividing means for outputting a horizontal drive pulse having the following, a horizontal drive circuit and a flyback transformer driven by the output of the frequency dividing means, and frequency division of a return pulse from the flyback transformer And a second frequency divider for obtaining a pulse having the same cycle as the cycle of the first video signal. The output of the second frequency divider is input to the other input terminal of the phase comparator. This is achieved by absorbing the delay time fluctuation in the horizontal deflection processing section. [Operation] According to the present invention, even when switching between the first video signal (standard signal) and the second video signal (double-speed signal) as an input signal, the phase synchronization circuit for horizontal synchronization can be configured with one stage. When the same phase error response is obtained and the first video signal (standard signal) is input, the phase error response is greatly improved and the delay time fluctuation in the horizontal deflection processing unit can be absorbed, so that a high image quality can be obtained. Can be achieved. [Embodiment] Hereinafter, a first embodiment of the present invention will be described with reference to FIG. In FIG. 1, 1 is a normal video signal input terminal, 2 is a normal RGB signal input terminal, 3 is a double-speed RGB signal input terminal, 4 is a demodulation circuit, 5 is a synchronization separation circuit, 6 is a horizontal synchronization divide-by-2 circuit, 7 Is a double speed conversion circuit, 8 is a video output circuit, 9 is a double speed horizontal AFC circuit, 10 is a vertical deflection circuit, and 11 is a cathode ray tube. Next, the overall operation will be described. The input normal video signal 1 is demodulated by the demodulation circuit 4 and switched to the normal RGB signal 2. The switched signal is input to the double-speed conversion circuit 7 and converted into a double-speed signal whose horizontal scanning cycle is 1/2 of the normal one. Here, the double-speed converted signal and the double-speed RGB signal 3 are switched and input to the video output circuit 8 to drive the CRT 11. On the other hand, the synchronization signal is switched between the synchronization separated by the synchronization separation circuit 5 and the synchronization of the normal RGB signal 2, and the double-speed RBG signal 3 having the same horizontal synchronization frequency as the normal horizontal synchronization frequency by the horizontal synchronization 2 frequency dividing circuit 6. The horizontal synchronization is input to the double speed horizontal AFC circuit 9, the vertical synchronization is input to the vertical deflection circuit 10, and the deflection signal is supplied to the deflection yoke. Further, a clock synchronized with the input horizontal synchronization is generated from the double-speed horizontal AFC circuit 9 and output to the double-speed conversion circuit 7 and the like. Hereinafter, the operations of the double-speed horizontal AFC circuit 9 and the double-speed conversion circuit 7 will be described in detail. First, about the double-speed horizontal AFC circuit 9 and its peripheral parts,
FIG. 2 shows the detailed configuration. In FIG. 2, reference numeral 30 denotes a normal horizontal synchronization signal input terminal, 31 denotes a double-speed horizontal synchronization signal input terminal, 32 denotes a switch, 13 denotes a phase comparator, 14 denotes an LPF, and 15 denotes V
CO, 16 is 8f _sc clock, 17 is 4f _sc clock, 18 is 910 divider circuit, 19 is 2 divider circuit, 20 is waveform shaping circuit, 21 is double speed horizontal drive circuit, 22 is double speed horizontal output circuit, and 23 is A horizontal deflection yoke, 24 is a flyback transformer, and 25 is a high voltage limiting circuit. The 4f _sc clock 17 is generated from the 8f _sc clock 16 using the divide-by-2 circuit in the 910 frequency divider circuit 18. First, an operation when a normal video signal is input will be described. Normal horizontal sync 12 input to phase comparator 13
A voltage corresponding to the phase difference between the output of the flyback transformer 24 and the output obtained by dividing the output of the flyback transformer 24 by
Input to CO15. Here, the VCO 15 generates an 8 _fsc clock 16, which is a clock having a frequency eight times the color subcarrier frequency (f _sc ). 4f _sc clock is obtained by the clock divided by two. Although the clock is described later, the double-speed conversion circuit 7
The A / D converter is used for a sampling clock and a write / read clock for a line memory. The horizontal synchronizing frequency (f _H) and the relationship between f _sc from _{(455/2) f H = f sc} , the horizontal sync speed, 2f _H = (1/910) 8f from becoming a 8f _{sc sc} By dividing the clock 16 by 910, double-speed horizontal synchronization can be obtained. Furthermore, normal horizontal synchronization is obtained by dividing the frequency by 2 by the divide-by-2 circuit 19, and the phase synchronization circuit is formed by inputting the result to the phase comparator 13. The double-speed horizontal synchronization output from the 910 frequency dividing circuit 18 is formed and shaped by the waveform shaping circuit 20, is input to the double-speed horizontal drive circuit 21, drives the double-speed horizontal output circuit 22, and is supplied to the horizontal deflection yoke 23. Also,
The output of the double-speed horizontal output circuit 22 is
And is boosted and rectified to generate a power supply voltage required for each circuit. The flyback pulse generated by the flyback transformer 24 is input to the high voltage limiting circuit 25, and when the flyback pulse increases due to a failure in the power supply circuit or the like and the high voltage rises abnormally, the oscillation is stopped.
Horizontal deflection is not performed. Next, an operation when a double-speed video signal is input will be described. When a double-speed video signal is input, switch
Numeral 32 is closed on the opposite side to that shown in the figure, and an output obtained by dividing the double-speed horizontal synchronizing signal by 2 by the frequency dividing circuit 6 is sent to the phase comparator 13.
Since the frequency of this output is exactly the same as that of a normal video signal, the operation of the other parts is the same as described above. Note that the vertical deflection circuit 10 is the same circuit as the vertical deflection circuit of the normal television receiver because the period of the vertical synchronization is the same at about 1/60 second for both the double speed signal and the normal signal. Next, the double speed conversion circuit 7 will be described. Here, the video input signals of the double speed conversion circuit 7 are a normal luminance signal and a color difference signal, and are output in the form of a double speed luminance signal and a color difference signal. FIGS. 3 and 4 show the specific configuration of the double speed conversion circuit 7. FIG. In FIG. 3, reference numeral 26 denotes a video signal input terminal which is a luminance signal or a color difference signal; 27, an A / D converter;
Is a line memory, and 29 is a D / A converter. FIG. 4 is a diagram showing the operation in the line memory. Video signal 26 is
The signal is input to the A / D converter 27, sampled by the _4fs clock 17, and input to the line memory 28. The clock for writing to the line memory is also the 4f _sc clock, but data reading is performed at the double 8f _sc clock 16. D /
By performing D / A conversion by the A converter 29, a double-speed video signal having a half cycle of a normal cycle can be obtained. FIG. 4 shows the operation of this line memory. As shown in FIG. 4, the line memories 1 and 2 are alternately written and read-out is switched to continuously obtain a double-speed video signal. The double-speed-converted video signal is output from the video amplification / output circuit 8 having a band twice as large as that of a normal television receiver to the cathode ray tube 11, and is output by the double-speed AFC circuit 9 into the double-speed horizontal output signal. Is scanned. Here, another embodiment of the double speed AFC circuit 9 will be described with reference to FIG. In FIG. 5, 30 is a normal horizontal synchronization input terminal, 31 is a double speed horizontal synchronization input terminal, 32 is a synchronization changeover switch a, and 33 is a changeover switch b. The operation will be described here. When a normal signal is selected as an input signal, normal horizontal synchronization is input to the phase comparator 13 by the changeover switch a32, and the same operation as in the above-described embodiment is performed. Now, the case where the double-speed horizontal synchronization is input will be described. First, the double speed horizontal synchronization selected by the changeover switch a32 is input to the phase comparator 13. Then, the phase of the signal that does not pass through the frequency dividing circuit 19 is compared by the changeover switch b33, and the voltage corresponding to the phase difference is applied to the VCO 15 that passes through the LPF 14.
Is input to The VCO 15 generates an 8f _sc clock, and divides this by a 910 frequency divider circuit 18 to obtain double-speed horizontal synchronization, which is input to a phase comparator 13 through a waveform shaping circuit 20,
The present invention constitutes a phase locked loop circuit.
Although not shown in the drawing, as shown in FIG. 2 by the line connecting the flyback transformer 24 and the divide-by-2 circuit 19, the flyback pulse is directly passed through the switch b33 without frequency division. Input to the phase comparator 13
This constitutes a phase locked loop. As described above, when the input of the phase comparator 13 is the normal horizontal synchronization, the changeover switch b33 is switched to pass through the divide-by-2 circuit 19, and when the double-speed horizontal synchronization is input, the divide-by-2 circuit 19 , So that double-speed horizontal scanning is always performed by one phase synchronization circuit. In the above embodiment, the case where n = 2 has been described.
The same applies to the case where is a different value. As described above, in the present invention, double-speed horizontal synchronization is generated by one phase synchronization circuit regardless of whether normal horizontal synchronization or double-speed horizontal synchronization is input as an input signal,
Since double-speed horizontal scanning can be performed, the phase error response is the same as that at the time of double-speed horizontal synchronization input even if normal horizontal synchronization is input as an input signal, and it can be greatly improved compared to the conventional method. Become. [Effects of the Invention] According to the present invention, even when switching between a standard signal and a double-speed signal as an input signal, the same phase error response can be obtained because the phase synchronization circuit for horizontal synchronization can be configured with one stage. When a normal signal is input, the phase error response is greatly improved. Further, since there is one phase synchronization circuit, there is also an effect that the circuit configuration and adjustment can be simplified. Further, there is an advantage that the image quality can be improved by absorbing the delay time fluctuation in the horizontal deflection circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a double-speed horizontal AFC circuit, FIG. 3 is a block diagram of a double-speed conversion circuit, and FIG. FIG. 5 is a timing chart showing the operation of the line memory in the conversion circuit, FIG. 5 is a block diagram of a double-speed horizontal AFC circuit as another embodiment, FIG. 6 is a block diagram showing a conventional example, and FIG. FIG. 8 is a block diagram showing details, and FIG. 8 is an explanatory diagram showing a television screen in which phase error responses are compared. Description of reference numerals 1 ... Normal video signal input terminal, 2 ... Normal RGB signal input terminal, 3 ... Double-speed RGB signal input terminal, 4 ... Demodulation circuit,
5: synchronization separation circuit, 6: horizontal synchronization frequency dividing circuit, 7:
Double speed conversion circuit, 8 Video output circuit, 9 Double speed AFC circuit, 10 Vertical deflection circuit, 13 Phase comparator, 14 LP
F, 15: VCO, 16: 8f _sc clock, 17: 4f _sc clock, 18: 910 divider circuit, 19: 2 divider circuit, 20: double-speed horizontal synchronization generator circuit, 21: horizontal Drive circuit, 22 ……
Double-speed horizontal output circuit, 23 horizontal deflection yoke, 24 flyback transformer, 25 high-voltage limiting circuit.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Toshinori Murata               292 Yoshida-cho, Totsuka-ku, Yokohama-shi Co., Ltd.               Hitachi, Ltd. (72) Inventor Toshiyuki Kurita               292 Yoshida-cho, Totsuka-ku, Yokohama-shi Co., Ltd.               Hitachi, Ltd. (72) Inventor Ikuya Arai               292 Yoshida-cho, Totsuka-ku, Yokohama-shi Co., Ltd.               Hitachi, Ltd. (72) Inventor Kazuo Nakagawa               292 Yoshida-cho, Totsuka-ku, Yokohama-shi Co., Ltd.               Hitachi, Ltd.                (56) References JP-A-57-65069 (JP, A)                 JP-A-58-154970 (JP, A)

Claims (1)

(57) [Claims] A first video signal is stored in a memory circuit for storing a signal over one horizontal period of an input normal first video signal and reading out the signal at n times (n is an integer of 2 or more) the stored speed. signal converting means for converting into a second video signal having a horizontal period of / n, and n for displaying the second video signal.
In a television receiver having a horizontal deflection processing unit having a double horizontal scanning frequency, the horizontal deflection processing unit receives a synchronization signal related to the first video signal at one input terminal as a reference. A phase comparator, a low-pass filter connected to the output of the phase comparator, a voltage-controlled oscillator whose oscillation frequency is controlled by the output of the filter, and the first image obtained by dividing the output of the oscillator. A first frequency divider for outputting a horizontal drive pulse having a horizontal cycle of 1 / n of a horizontal cycle of a signal, a horizontal drive circuit and a flyback transformer driven by an output of the frequency divider, and the flyback transformer And a second frequency dividing means for obtaining a pulse having the same cycle as the cycle of the first video signal by dividing the frequency of the return pulse. n times speed scanning television receiver, characterized in that to absorb the delay time variation in the horizontal deflecting unit to the other input terminal of the serial phase comparator.