JPH01132284A - Picture memory control device - Google Patents

Abstract

PURPOSE:To reduce horizontal jitter or large image swinging in a horizontal direction by setting write start timing by a horizontal sync signal, and at the same time, setting read start timing by the frequency divided output signal of a PLL circuit. CONSTITUTION:The horizontal sync signal Hs from a sync separation circuit 25 is given to a write signal input terminal 19a, and the write start timing of the line memory of a 1H delay circuit 11' is set by this signal. Besides, the frequency divided output signal from a frequency divider 28 is given to a read signal input terminal 19b, and the read start timing of the line memory of the 1H delay circuit 11' is set by this signal. The frequency divided output signal of the frequency divider 28 is supplied to a horizontal AFC circuit 29 differently from cusomary way. Thus, the horizontal shift of the vertical line of the picture of a TV receiver comes less.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a control device for an image memory used in a digital television receiver or the like.

(b) Conventional technology In recent years, pre-vision receivers (hereinafter referred to as 'TVTV receivers') have been used to receive standard signals (signals with a constant ratio of horizontal synchronization signal to burst signal frequency) such as on-air broadcasting. ,
It is possible to reproduce both non-standard signals (horizontal synchronization No. 13 and signals where the ratio of the frequency of Verse l- (δ) is not constant) such as the reproduction signal of a video tape recorder (hereinafter abbreviated as rvrR). In other words, in VTRs, the horizontal sync signal varies from the normal frequency (15.7kHz) due to factors such as expansion and contraction of the playback tape (causing sick).
Therefore, the reproduced 1g signal is called a non-standard signal.

Fig. 5 is a block diagram of a general TV receiver, in which a composite video signal applied to a terminal (1) is demodulated by a video chroma circuit (2) to generate R, G, and B primary color signals. , these R, G, and B primary color signals are sent to the cathode ray tube (6) via the R signal, G signal, and B signal drive circuits (3), (4), and (5).
is supplied to On the other hand, the composite video signal is input to a synchronization separation circuit 7), where a horizontal synchronization signal (Hs) and a vertical synchronization signal (Vs) are extracted.
s) is supplied to the vertical deflection circuit (8), and the horizontal synchronizing signal (Hs) is supplied to the horizontal deflection circuit (1o) via the horizontal AFC circuit (9).

In the above TV receiver, when inputting standard signals, A
The time constant of the FC circuit (9) is decreased to speed up the AFC pull-in response, and when a non-standard signal is input, the AFC circuit (9)
The time constant of is increased to slow down the retraction response. The reason for this is that the period of the horizontal synchronizing signal for non-standard signals is not constant and there is jitter. In order to improve this, the output of the horizontal deflection circuit (lO) is slowed down by the horizontal synchronization signal and the output of the horizontal deflection circuit (10) is changed. The output is made to have a constant horizontal period without being affected by the fine jitter of the horizontal synchronization signal.

A skew (SKEW) distortion signal is usually used to study the time constant of an AFC circuit as described above. Kokote M') S
The K E W distortion signal is obtained from the test pattern generator, and the specific horizontal scanning period of each field is 63, s + a I as shown in Figure 6.
Js ('i >, 63.5-a L18 (■)). When such a 5KEW distorted signal is played back on a TV receiver, the CRT screen will look like the one shown in Figure 7. The points where the line (thick line) breaks are the 6th points.
Corresponds to ■■ in the figure. Since the time taken for the recorded part ■■ to return to its original state corresponds to the time constant of the AFC circuit, the time constant of the AFC circuit can be visually evaluated using the 5KEW distortion signal as described above.

Horizontal jitter and large image shaking in the horizontal direction in non-standard signals such as VTR playback signals can be considered to be the same phenomena as the 5KEW distortion signal described above, and therefore, the performance of the TV receiver is limited to the above SKEW distortion. It is said that it is good if the horizontal shift of the screen caused by the signal is small, and the time it takes for the vertical line to return to its original state is appropriately short.

By the way, video signal processing circuits using digital memory are now being installed even in TV receivers that have not kept pace with recent advances in digital technology.

Figure 8 shows the line memory (1
2) shows an IH (H: horizontal period) delay circuit <11) using (13). In the delay circuit (11), (14) is an input terminal into which a digital video signal is input, (15) is an output terminal, (16) is a clock input terminal, (17) is a write changeover switch, and (18) is a readout terminal. The changeover switch (19) is a changeover fd terminal to which a changeover signal such as a horizontal synchronization signal is input, and is also used as a line memory (12) as is well known.
) and (13) are digital memories each capable of storing digital video signals for IH.

FIG. 9 is a timing chart for explaining the operation of the IH delay circuit (11), in which (a) shows the mode of the line memory (12), and (b) shows the mode of the line memory (13). ) mode, and the switching signal [same figure (
c)] is input to the input/input terminal 19), each of the memories (12) and (13) becomes in the opposite mode.

That is, during any IH period, the switch (17)
When (18) is in the position shown in Figure 8, the line memory (12)
) are sequentially written with digital video signals via the switch (17), and at the same time, from the line memory (13), the IH signal just before the IH signal written into the memory (12) is written. It is read out via switch (18). And then, during the next IH period, there will be a swim-? (17)
(18) is switched, the next IH worth of digital video signals are written into the line memory (13), and the above IH worth of signals are read out from the line memory (12). By repeating such operations, it functions as an IH delay circuit. Such an IH delay circuit (11) is used, for example, in a digital TV that doubles the number of horizontal scanning lines to improve vertical resolution.

FIG. 10 shows a block diagram of the main parts of such a digital TV.

The analog composite video signal applied to the input terminal (20) in Fig. 1O is connected to the video chroma CNL path (21).
After being demodulated by the A/D converter (22), it is converted into a digital video signal and sent to the IH delay circuit (
11) is written to the line memory. The digital video signal read from the line memory of the IH delay circuit (11) is converted into an analog video signal by the D/A converter (23) and then output from the output terminal (24).

On the other hand, the analog composite video signal is processed by a synchronization separation circuit (2
5), but the horizontal synchronization signal extracted there (
Hs) is supplied as one input to the phase comparator (26). (27) is N [MH
z] is a VCO [voltage controlled oscillator] that supplies a clock signal, and a frequency-divided output signal is supplied to this vCO as the other input of a phase comparator (26). This phase comparator (26) compares the phases of the horizontal synchronizing signal (Hs) and the frequency-divided output signal of the frequency divider (28), and adjusts the oscillation frequency of vCO (27) so that the comparison result becomes zero. Control. Therefore, these phase comparators (2
6), VCO (27) and frequency divider (2g>4) with PLL (Phas
configuring an etucked 1loop) circuit. Horizontal synchronization signal (Hs) that can be output from the synchronization separation circuit (25)
is connected to the horizontal deflection circuit (30) via the horizontal AFC circuit (29).
). The signal that has been output from the horizontal deflection circuit (30) is output from the terminal (31).

Next, the operation when a non-standard signal is input to the circuit shown in FIG. 10 will be explained by taking as an example the case where the above-mentioned 5 KEW distortion signal is input, with reference to the time chart of FIG. 11.

In FIG. 11, (a) shows the input video signal;
b) is the horizontal synchronization signal, (c) is the divided output signal of V CO (27), (d) is the oscillation frequency of V CO (27), and (e) is the IH delay circuit (11). ), and (f') in the same figure is the video signal read out from the memory of the horizontal deflection circuit (3).
0) output signal (flyback pulse) is shown.

Now, when a 5KEW distortion signal is generated at the 0 point in Fig. 11, the phase comparator (26) compares the phases of the signals shown in Fig. 11 (b) and (c) to determine the oscillation frequency of the V CO (27). Change it as shown in (d). At this time, the switching of the start point for writing and reading the line memory of the 1H delay circuit (11) in Fig. 10 [switching of switches (17) and (18) in Fig. 8] is performed by the horizontal synchronizing signal (Hs) There is no problem since it is performed within the horizontal retrace line.

However, as shown in FIG. 10, the horizontal deflection circuit (30) transmits the horizontal synchronizing signal (Hs) to the horizontal AFC circuit (
29), so the AF
Due to the time constant of C circuit (29), as shown in Fig. 11(f)
The timing of the flyback pulse is approximately the same as that of the frequency-divided output signal shown in FIG.

As a result, as shown in FIG. 11 (f), the phase of the video signal output from the IH delay circuit (11) and the flybank pulse is largely shifted, so that the screen of the TV receiver is
It will look like Figure 2.

In order to eliminate such drawbacks, for example, Japanese Patent Laid-Open No. 55-5
As described in Publication No. 3981 (HO4N 5 /783), measures have been taken to reduce jitter in VTR[, but these have not been sufficient.

(c) One problem that the invention seeks to solve The present invention has been made in view of the above points, and
This is an attempt to reduce horizontal jitter and large horizontal image shaking by devising control of the image memory into which non-standard signals such as the reproduced signals of the above are input.

(d) Means for Solving the Problems The image memory control device of the present invention includes a memory that stores an input video signal for at least one horizontal period, and a synchronization separation circuit that extracts a horizontal synchronization signal from the input video signal. , a PLL circuit whose reference signal is a horizontal synchronization signal provided from the synchronization separation circuit, and a horizontal AFC provided with a frequency-divided output signal synchronized with the horizontal synchronization signal obtained by the PLL circuit.
The memory has a structure in which a write start timing is set by a horizontal synchronizing signal, and a read start timing is set by a frequency-divided output signal of the PLL circuit.

(E) Effect With the above configuration, a signal (divided output signal) synchronized with the memory read timing is manually input to the AFC circuit, so even if the IH period changes, the video signal read from the memory and The phase difference with the output signal of the horizontal deflection circuit is made as small as possible.

(f) Examples An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of the main parts of a digital TV receiver embodying the present invention, and the same parts as in FIG. 10 are given the same reference numerals, and the explanation thereof will be omitted.

That is, in the present invention, the IH delay circuit (11') as shown in FIG. 2, in which the same parts as in FIG.
, that is, an IH delay circuit (11) comprising a write signal input terminal (19a) for switching the switch (17) and a read signal input terminal (19b) for switching the switch (18).
') is used, and the write signal input terminal (19a)
is the horizontal synchronization signal (H-s) from the synchronization separation circuit (25).
) is given, thereby setting the write start timing of the line memory of the IH delay circuit (11').

Further, the read signal input terminal (19b) is connected to a frequency divider (
28), which provides a frequency-divided output signal from I
The read start timing of the line memory of the H delay circuit (11') is set.

It goes without saying that the switches (17) and (18) can be switched alternately as in the conventional case.

Further, unlike the conventional case, the horizontal AFC circuit (29) is supplied with the frequency-divided output signal of the frequency divider (28). FIG. 3 shows an operation timing chart when a 5KEW distortion signal is input to the circuit shown in FIG.
The figure (b) shows the horizontal synchronization signal, and the figure (c) shows the VCO (2g
), the divided output signal of the IH delay circuit (11') is shown in (d) of the same figure.
), the video signal read out from the line memory of
) indicates the output signal (flyback pulse) of the horizontal deflection circuit (30).

As can be seen from the timing chart in Fig. 3 above, the input video signal is written to one line memory at the timing of the horizontal synchronization signal [Fig.
It is read out from the memory at the timing of the frequency-divided output signal of vCO [FIG. 4(C)]. and horizontal deflection circuit (30)
is driven by the frequency-divided output signal of V CO (28) [FIG. 3(C)] via the horizontal AFC circuit (29), so the timing of the horizontal deflection output is as shown in FIG. 3(e), As a result, even if the IH period changes due to the 5KEW distortion signal, the position of the video signal completely read out from the memory [Fig. 3(d)] and the output signal of the horizontal deflection circuit (30) [Fig. 3(e)] The phase difference becomes as small as possible. As a result, the horizontal deviation of the vertical lines on the screen of the TV receiver becomes smaller as shown in FIG.

(G) Effects of the Invention As described above, according to the present invention, it is possible to reduce jitter and large image shake in the horizontal direction that occur when a non-standard signal such as a reproduction signal from a VTR etc. is input. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of a television receiver embodying the present invention, FIG. 2 is a diagram showing details of the main parts, and FIG. 3 is a diagram for explaining the operation of FIG. 4 is a diagram for explaining the present invention in detail, FIG. 5 is a block diagram of main parts of a general television receiver, FIGS. 6 and 7 are diagrams for explaining skew distortion signals, and FIG. Fig. 8 is a diagram showing the IH delay circuit, Fig. 9 is a diagram explaining its operation, Fig. 10 is a block diagram of the main part of a television receiver using the IH delay circuit, Fig. 11 is a diagram explaining its operation, and Fig. 12 The figure is a diagram for explaining the conventional drawbacks. (11')...IH delay circuit (memory), (25)...
... Synchronization separation circuit, (26) ... Phase comparator, (27
)・V C01 (28)... Frequency divider, (29)...
Horizontal AFC circuit.

Claims (1)

[Claims] (1) A memory that stores an input video signal for at least one horizontal period, a synchronization separation circuit that extracts a horizontal synchronization signal from the input video signal, and a PLL that uses the horizontal synchronization signal provided from the synchronization separation circuit as a reference signal. and an AFC circuit to which a frequency-divided output signal synchronized with the horizontal synchronization signal obtained by the PLL circuit is provided, and the memory has a write start timing set by the horizontal synchronization signal and a frequency division output signal of the PLL circuit. An image memory control device in which readout start timing is set by an output signal.