JPH02264583A - Picture display device - Google Patents

Abstract

PURPOSE:To display a picture with no distortion by compressing a standard TV signal in the time direction by a compressing device and displaying the compressed TV signal on a display after expansion CONSTITUTION:When a signal is written into a buffer memory of a compression circuit 117, a clock signal 118 of 8fSC which is 1820 times as much as a horizontal synchronizing frequency fH is produced from a voltage control oscillator VCO 117c. Then a read clock 113 having an (8X4/3fS) frequency is used when a signal is read out of the buffer memory. The read frequency (8X4/3fSC) of the buffer memory is 4/3 times as much as write frequency 8fSC and therefore a signal is compressed down to 3/4 times in the time direction by the circuit 117. This compressed signal is expanded by 4/3 times by a display 121. Thus it is possible to obtain a picture free from any distortion on the display.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to image display devices such as television receivers, monitors, and projection tubes.

[Conventional technology]

2. Description of the Related Art Image display devices, such as television receivers in recent years, are required to have larger screens and higher image quality to provide more impact and a sense of realism.

On the other hand, in order to increase the impact and sense of realism in video information, a lot of horizontal movie-sized wide screen information is being created that has no video information at the top and bottom of the screen (that is, has blanks at the top and bottom).

Under these circumstances, recently the number of scanning lines has been reduced to the current N.
Approximately twice the TSC method, the frequency band is widened,
In addition to increasing the resolution, a television system was proposed in which the aspect ratio of the displayed image was wider than the current 4:3, for example 16:9, and based on this proposal, televisions with horizontal displays were proposed. John receiver has been put into practical use.

Also, if the aspect ratio of the displayed image is 1,
A television receiver with a 6:9 horizontal display has the ability to display images obtained from current television signals with an aspect ratio of 4:3 (hereinafter referred to as standard television signals). A television receiver has also been proposed.

However, in a television receiver equipped with such a function, an image obtained from a standard television signal with an aspect ratio of 4:3 as shown in FIG. , the aspect ratio is 1
When displayed on the entire screen of a 6:9 horizontal display,
As shown in FIG. 7(b), there was a problem that the image was distorted.

That is, in this case, the aspect ratio of the image obtained from the standard television signal is 4:3 = 1279, so if this image is displayed on a horizontal display with an aspect ratio of 16:9, the displayed image will be is 16 horizontally
/12=expanded by 4/3 times.

Therefore, in the past, the deflection current was controlled so that only a part of the screen of the display was scanned with the electron beam, and an image with an aspect ratio of 4:3 was displayed on that part. ) to obtain images without distortion.

In addition, as such a conventional technique, for example, Japanese Patent Application Laid-open No. 6
1-206381 and the like.

By the way, recently, even in television receivers that have a normal display with an aspect ratio of 4:3, the number of scanning lines of the standard television signal has been doubled compared to the current NTSC system. There are some that aim to achieve high resolution.

(Problem to be Solved by the Invention) As mentioned above, conventionally, a horizontally long display with an aspect ratio of 16:9 has the function of displaying images obtained from a standard television signal with an aspect ratio of 4:3. When displaying an image obtained from a standard television signal with an aspect ratio of 4:3 on the television receiver, the deflection current is controlled and only a portion of the display screen is exposed to the electron beam. By scanning the area and displaying the image in that area, an image without distortion was obtained.

Furthermore, some television receivers having a normal display with an aspect ratio of 4:3 have been designed to have a higher resolution by approximately doubling the number of scanning lines of the standard television signal than the current NTSC system.

In the former type of television receiver, only a portion of the display screen is scanned with an electron beam, so if only images obtained from a standard television signal with an aspect ratio of 4:3 are displayed, the display There is a problem in that the scanned portion of the phosphor on the screen deteriorates more quickly than the unscanned portion.

Another problem is that the configuration of the circuit for controlling the deflection current becomes complicated.

On the other hand, with the latter type of television receiver, there is no problem when receiving current TV broadcasts and displaying images, but there are fluctuations in the time axis (jitter) such as in signals reproduced from a video tape recorder etc. When displaying an image by inputting a television signal containing , there is a problem in that the image quality deteriorates due to the low ability to remove time axis fluctuations. Furthermore, if a new time axis correction circuit is provided to solve this problem, there is a problem in that the circuit scale becomes large.

The present invention has been made in view of the problems of the prior art described above, and therefore, an object of the present invention is to provide a display in which the aspect ratio of a displayed image is different from that of a standard television signal (for example, a display with an aspect ratio different from that of a standard television signal). Ratio 16:9
As an image display device with a horizontally long display),
When displaying images obtained from standard television signals, the images can be displayed without distortion, and even when only images obtained from standard television signals are displayed, there is no uneven deterioration of the phosphor on the display screen. It is an object of the present invention to provide an image display device that can be configured with a simple circuit without causing any problems.

Another object of the invention is to provide a display (e.g. a conventional display with an aspect ratio of 4:3) in which the aspect ratio of the displayed image is equal to the aspect ratio of the standard television signal, and the aspect ratio of the displayed image is equal to the aspect ratio of the standard television signal. Let the number of N(
N is an integer of 2 or more An object of the present invention is to provide an image display device capable of displaying images without deterioration of the image quality and without increasing the circuit scale.

[Means to solve the problem]

In order to achieve the former of the above objects, the present invention provides an image display device having a display in which the aspect ratio of a displayed image is different from that of a standard television signal, by oscillating at a predetermined frequency. 1st
oscillation means, horizontal drive pulse generation means for generating horizontal drive pulses for driving the display based on the oscillation output of the first oscillation means; 2 oscillation means and a storage section, inputs the standard television signal, writes it into the storage section in synchronization with the oscillation output from the second oscillation means, and writes the written standard television signal to the storage section. compression means for compressing and outputting the standard television signal in the time direction by reading from the storage section in synchronization with the oscillation output from the first oscillation means; control means for controlling the compression means to read out the standard television signal at least twice during one period of the horizontal drive pulse;
It is now equipped with the following.

Furthermore, in order to achieve the latter of the above objects, the present invention provides an image display device having a display in which the aspect ratio of a displayed image is equal to that of a standard television signal, at a predetermined frequency. a first oscillating means for oscillating, a horizontal driving pulse generating means for generating a horizontal driving pulse for driving the display based on the oscillation output of the first oscillating means, and synchronized with the standard television signal. a second oscillating means for oscillating the signal, and a storage section, inputting the standard television signal, and synchronizing the signal obtained from the standard television signal with the oscillation output from the second oscillating means. By writing the written signal into the storage section and reading the written signal from the storage section in synchronization with the oscillation output from the first oscillation means, the standard television signal has a number of scanning lines N.
(N is an integer greater than or equal to 2) N-times speed means for multiplying and outputting;
It is now equipped with the following.

[Operation] Of the two inventions mentioned above, the former invention will be explained.

The compression means has a storage section therein, and writes the inputted standard television signal into the storage section in synchronization with the oscillation output from the second oscillation means. Then, the written standard television signal is read out from the storage section and output in synchronization with the oscillation output from the first oscillation means. Further, at this time, the control means is configured to read out the written standard television signal at least twice into a video period portion and a black level period portion during one cycle of the horizontal drive pulse. Control the compression means.

Here, for example, if the frequency of the oscillation output from the first oscillation means is 4/3 times the frequency of the oscillation output from the second oscillation means, then the standard television signal is is compressed by 3/4 times in the time direction and output.

Therefore, for example, if the aspect ratio of the standard television signal is 4:3 and the aspect ratio of the image displayed on the display is 16:9, the image will be compressed by 3/4 times in the time direction. When the standard television signal is displayed on the display, it is stretched by 4/3 times in the horizontal direction, but by 3 times in the time direction.
Since the image is compressed by /4 times, the size of the image in the horizontal direction is 4/3×3/4=1 times the original size, and an image without distortion can be displayed.

Moreover, even when displaying images based on the standard television signal, the scanning of the electron beam on the display covers the entire screen, so even if only images based on the standard television signal are displayed, the fluorescence on the screen of the display There is no uneven deterioration of the body, and the circuit configuration itself is simple.

Furthermore, when the standard television signal is read out from the storage section in the compression means, it is read out in synchronization with the very stable oscillation output from the first oscillation means. In addition to compressing the signal, it is also possible to correct the time axis of the signal. In addition, by reading out the signal separately into the video period part and the black level period part, even if the signal is read out so that the video period part is displayed in the center of the screen on the display, the black level period part is not connected to the horizontal retrace line. Since it can be read out so that it is included within the period, the black level can be reproduced correctly.

Next, of the above two inventions, the latter invention will be explained.

The N-time speed means has a storage section therein, and writes a signal obtained from the inputted standard television signal into the storage section in synchronization with the oscillation output from the second oscillation means. Then, the written signal is transferred to the first
By reading from the storage section in synchronization with the oscillation output from the oscillation means, the number of scanning lines of the standard television signal is multiplied by N and output.

In this way, when reading out the signal from the storage section in the N-time speed means, the signal is read out in synchronization with the very stable oscillation output from the first oscillation means, so that the N-time speed conversion At the same time, it is possible to perform time axis correction of the signal.

Therefore, even if a signal containing time axis fluctuations reproduced from a video tape recorder etc. is input as the standard television signal, the time axis fluctuations are sufficiently removed and the signal is double-speed converted without time axis fluctuations. can be displayed on the display without increasing the circuit scale.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, the present invention is applied to a television receiver, which is one of image display devices.

In FIG. 1, 101 is a standard television signal with an aspect ratio of 4:3, 102 is an analog/digital (hereinafter referred to as A/D) converter, and 103 is a motion adaptive luminance signal/chrominance signal (hereinafter referred to as A/D) converter. (referred to as Y/C) separation circuit,
104 is a motion adaptive scanning line interpolation circuit, and 105 is a double speed conversion circuit. This double speed conversion circuit 105 is a line memory 105a.

105b and a switching circuit 105c, it receives the signal from the motion adaptive scanning line interpolation circuit 104, doubles its frequency, and outputs it. Further, 106 is a synchronization separation circuit that separates a horizontal synchronization signal (hereinafter, the frequency of this signal, ie, horizontal frequency will be referred to as fH) from the standard television signal 101, and 107 is a clock generation circuit. This clock generation circuit 107 includes a phase comparator 107a,
Low pass filter 107b, voltage controlled oscillation circuit 107
c.

A phase-locked loop (hereinafter referred to as PL) consisting of a counter 107d
Say L. ) circuit, which generates a clock synchronized with the horizontal synchronization signal from the synchronization separation circuit 106. Also,
108 is a crystal oscillation circuit; 109 is a horizontal drive pulse generation circuit that divides the oscillation output from the crystal oscillation circuit 108 and generates a horizontal drive pulse with a frequency of 2fo; 110 is a horizontal drive pulse generator that divides the oscillation output from the crystal oscillation circuit 108 and generates a horizontal a timing generation circuit which inputs the horizontal drive pulse from the drive pulse generation circuit 109 and creates various signals synchronized with the horizontal drive pulse from the oscillation output; 111 is a gate circuit; 112 is a control signal for controlling the gate circuit 111; 113; 114 is a clock that provides timing for reading in the compression circuit 117, which will be described later; 114 is a read reset signal (RR) that indicates the start position of reading in the compression circuit 117, which will be described later;
15 is a control signal for controlling a gate circuit 119, which will be described later; 116 is a decoder that creates a write reset signal (WR) indicating a write start position in a compression circuit 117, which will be described later; and 117 is a buffer memory for storing the signal. 118 is a clock generation circuit 1 which compresses the signal from the double speed conversion circuit 105 in the time direction.
119 is a gate circuit, 120 is a digital/analog (hereinafter referred to as D/A) converter, and 121 is displayed. This is a horizontal display with an image aspect ratio of 16:9.

The above is the configuration of this embodiment, and next, the operation of this embodiment will be explained.

FIG. 2 is a waveform diagram showing main signal waveforms in FIG. 1.

The input standard television signal 101 with an aspect ratio of 4:3 is processed by the synchronization separation circuit 106 as shown in FIG.
) is separated, and the horizontal synchronization signal is input to the clock generation circuit 107.

The input horizontal synchronizing signal is phase-compared in the phase comparator 107a with a clock from a counter 107d having the same frequency as the frequency fH of the horizontal synchronizing signal. The comparison result is inputted to the voltage controlled oscillation circuit 107c via the low-pass filter 107b, and its oscillation frequency is controlled.
As shown in e), a clock 118 having a frequency of 8 fsc, which is 1820 times the frequency of the horizontal synchronizing signal "H", is generated in synchronization with the horizontal synchronizing signal.

This clock 118 with a frequency of 8fsc is input to the compression circuit 117 as an old clock, and
It is input to the counter 107d. The clock 118 inputted to the counter 107d is counted as 91 by the counter 107d.
The frequency is divided by 0 and input as a clock having a frequency of 2fH to the switching circuit 105C of the double speed conversion circuit 105, and the frequency is divided by 1820 and input as a clock having a frequency of f□ to the decoder 116 and the above-mentioned phase comparator 107a. be done.

In the decoder 116, the input clock having the frequency of fH is decoded and sent to the compression circuit 117 as a write reset signal (WR) with a vertical period as shown in FIG. 2(d).

Further, the standard television signal 101 is transmitted to the A/D converter 1
02, the signal is converted into a digital signal as shown in FIG. In addition, the second
In Figure (b), the numbers in parentheses are the numbers of data in the digital signal, and the same applies hereafter.

The motion adaptive scanning line interpolation circuit 104 creates a real signal and an interpolation signal from the input signal. The created real signal and interpolated signal are respectively sent to the double speed conversion circuit 10.
5, the frequency is doubled, and the result is shown in Figure 2 (C
), the signals are output alternately every 1/2 water cycle. In this way, the double speed conversion circuit 105 outputs a signal with improved image quality. In addition, in FIG. 2(C), R is a real signal, ■ is an interpolation signal, and the same applies hereafter.

The signal shown in FIG. 2(f) output from the double speed conversion circuit 105 is input to a compression circuit 117 having a buffer memory. In the compression circuit 117, the buffer memory is reset by the write reset signal (WR) inputted earlier from the decoder 116, and from that point on, the write clock 11B having a frequency of 8fsc from the clock generation circuit 107 is reset. In synchronization with , the input signal from the double speed conversion circuit 105 is written into the buffer memory.

Moreover, the oscillation output output from the crystal oscillation circuit 108 is
As shown in FIG. 2(i), the horizontal drive pulse generation circuit 109, the timing generation circuit 110. Each is input to the gate circuit 111.

The horizontal drive pulse generation circuit 109 divides the input oscillation output, generates horizontal drive pulses as shown in FIG. 2(n), and outputs them to the timing generation circuit 110 and the display 121, respectively.

The timing generation circuit 110 generates a second signal based on the input oscillation output from the crystal oscillation circuit 108 and the horizontal drive pulse.
A read reset signal (RR) 114 with a vertical period as shown in FIG.

Here, the reset at the time of reading the buffer memory in the compression circuit 117 is performed by the read reset signal (RR) 114 shown in FIG. 2(g), which is the same as the write reset signal (WR) shown in FIG. 2(d). It is performed in cycles, but the phase is shifted by 1/2 water cycle. This is to prevent writing and reading of signals from the buffer memory from competing with each other.

In addition, the timing generation circuit 110 creates a control signal 112 as shown in FIG. The circuit 111 is powered manually. This control signal 112 is a signal that specifies the reading period of the buffer memory in the compression circuit 117.

In the gate circuit 111, the input crystal oscillation circuit 108
The oscillation output from the control signal 112 is ANDed with the control signal 112 to obtain a read clock 113 as shown in FIG. 2(j), which is input to the compression circuit 117.

Therefore, in the compression circuit 117, the signal (data) is read from the buffer memory according to the read clock 113.
When read out, the signals are separated and read out as shown in FIG. 2(k). In FIG. 2(k), A is a video period, B is a black level period, and the rest are non-read periods.

On the other hand, the timing generation circuit 110 generates a control signal 115 as shown in FIG. and input it to the gate circuit 119.

The gate circuit 119 inputs the signal output from the compression circuit 117, and based on the control signal 115, the gate circuit
As shown in , the frame signal, that is, only during the non-read period,
Adding another signal with a predetermined level (shaded area),
Output.

The signal output from the gate circuit 119 is then sent to the D/
The A converter 120 converts it into an analog signal and inputs it to the display 121.

Then, on the display 121, the D/A converter 120
The signal input from the controller is displayed based on the previously input horizontal drive pulse.

As explained above, in this embodiment, the compression circuit 1
To write the signal to the buffer memory in step 17,
A write clock 118 with a frequency of 8fsC is used, and reading of signals from the buffer memory is performed at (32/
3) A read clock 113 with a frequency of fsc is used, and the read frequency in the buffer memory (3) is used.
2/3) fsc is 4/3 times the write frequency 8fsc, so the compression circuit 117 compresses the signal by 3/3 in the time direction.
Compressed by 4 times.

Therefore, when displaying this compressed signal on the display 121, it is expanded by 4/3 times by the display 121, so on the screen of the display 121,
An image without distortion as shown in FIG. 7(C) can be displayed. However, in FIG. 7(c), the difference from the conventional method is that in this embodiment, an image obtained by the above-mentioned frame signal, that is, a frame is displayed at both ends of the screen, and this area is also sufficiently illuminated by the electron beam. This is the point being scanned.

Furthermore, in this embodiment, the very stable read clock 113 obtained from the oscillation output from the crystal oscillation circuit 108 is used to read signals from the buffer memory in the compression circuit 117. In addition to the signal compression described above, it is also possible to perform time axis correction of the signal. Therefore, even if a signal including time axis fluctuations reproduced from a video tape recorder or the like is input as the standard television signal 101, the time axis fluctuations can be sufficiently removed and displayed on the display 121.

Furthermore, in this embodiment, when reading the signal from the buffer memory in the compression circuit 117, the signal is read out separately into the video period portion and the black level period portion, so that the video period portion is placed in the center of the screen on the display 121. Even when the signal is read out so as to be displayed, the black level period portion can be read out so as to be included in the horizontal retrace period, so that the black level can be reproduced correctly.

In this embodiment, the read clock 113 used for reading the signal is obtained from the oscillation output from the crystal oscillation circuit 108, but even if it is not obtained from the oscillation output from the crystal oscillation circuit 10, for example, P L A signal synchronized with the color burst signal included in the standard television signal 101 may be generated by the L circuit, and the signal may be obtained from the generated signal.

In addition, in this embodiment, the frame signal is transmitted to the compression circuit 117.
Although it is added by digital processing in the latter stage,
The signal may be added by switching to a predetermined DC level through analog processing at a stage subsequent to the D/A converter 120.

Next, FIG. 3 is a block diagram showing another embodiment of the present invention,
FIG. 4 is a waveform diagram showing main signal waveforms in FIG. 3.

In FIG. 3, 122 is a frequency divider circuit, 123 is a write clock output from the frequency divider circuit 122, and other components that are the same as those in FIG. 1 are given the same reference numerals.

This embodiment is characterized in that the compression circuit 117 is eliminated by performing the signal compression operation performed by the compression circuit 117 together with the double speed conversion operation in the double speed conversion circuit 105.

The operation of this embodiment is basically the same as that of the embodiment shown in FIG. 1, so only the different parts will be mainly explained.

The frequency dividing circuit 122 divides the clock having a frequency of 8 fsc output from the clock generating circuit 107 by two,
It is output to the double speed conversion circuit 105 as a write clock 123 having a frequency of 4fSc.

Furthermore, the decoder 126 inputs the clock having the frequency fH output from the clock generation circuit 107,
Decode the vertical cycle write reset signal (WR
) is output to the double speed conversion circuit 105.

Next, the double speed conversion circuit 105 manually inputs the actual signal and interpolation signal created by the motion adaptive scanning line interpolation circuit 104.
The data is written to the line memories 105a and 105b, respectively.

At that time, each line memory 105a, 105b is reset by a write reset signal (WR) with a vertical period as shown in FIG. In synchronization with the input write clock 123 having a frequency of 4fsc as shown in FIG. 4(b), the actual signal (FIG. 4(c)) and interpolation signal from the motion adaptive scanning line interpolation circuit 104 are written.

Then, each line memory 105a, 105b is reset by the vertical cycle readout signal (RR) 114 inputted from the timing generation circuit 110, and from that point on, the fourth line memory 105a and 105b inputted from the gate circuit 112
It is read out in synchronization with a read clock 113 as shown in FIG.

In this way, when the signals are read out from each line memory 105a, 105b according to the read clock 113, the first
As explained in the embodiment shown in the figure, the signal is read out separately into the video period part and the black level period part, and the black level period part is read out so as to be included in the horizontal retrace period, It is output as a signal as shown in FIG. 4(e).

As described above, the double speed conversion circuit 105 performs the signal compression operation as well as the double speed conversion operation.

According to this embodiment, by the above-described signal compression operation in the double speed conversion circuit 105, as in the embodiment of FIG.
The signal is compressed by a factor of 3/4 in the time direction. When this compressed signal is displayed on the display 121, it is expanded by 4/3 times by the display 121, so that an image without distortion can be displayed on the screen of the display 121.

Also in this embodiment, the extremely stable read clock 113 obtained from the oscillation output from the crystal oscillation circuit 108 is used to read signals from each line memory 105a, 105b in the double speed conversion circuit 105. The double speed conversion circuit 105 can perform double speed conversion, signal compression, and time axis correction of the signal.

Furthermore, in this embodiment, since the compression circuit is removed, the circuit configuration is simpler than the embodiment shown in FIG.

Now, in each of the above embodiments, the target was a television receiver having a horizontally elongated display with an aspect ratio of 16:9, but next we will discuss a normal display with an aspect ratio of 4:3. Targets television receivers with

FIG. 5 is a block diagram showing another embodiment of the present invention.

In FIG. 5, 124 is a crystal oscillation circuit, 125 is an oscillation output of the crystal oscillation circuit 124, and 126 is a normal display with an aspect ratio of 4:3 for displayed images.
Other components that are the same as those in FIG. 3 are given the same reference numerals.

The operation of this embodiment is basically the same as that of the embodiment shown in FIG. 3, so only the different parts will be mainly explained.

The frequency dividing circuit 122 divides the clock having a frequency of 8 fsc output from the clock generating circuit 101 by two, and
It is input to the double speed conversion circuit 105 as a write clock 123 having a frequency of 4 fsc.

Further, the decoder 126 inputs the clock having the frequency f output from the clock generation circuit 107,
Decode the vertical cycle write reset signal (WR
) is input to the double speed conversion circuit 105.

On the other hand, the oscillation output 12 output from the crystal oscillation circuit 124
5 has the frequency of 8" and is input to the horizontal drive pulse generation circuit 109 and the timing generation circuit 110, respectively, and is also input to the double speed conversion circuit 10 as a read clock.
5 is also input.

The horizontal drive pulse generation circuit 109 divides the input oscillation output 125 to generate horizontal drive pulses having a frequency of 2fo, and outputs them to the timing generation circuit 110 and the display 126, respectively.

Further, in the timing generation circuit 110, the oscillation output 105
A read reset signal (RR) 114 with a vertical period is created based on the horizontal drive pulse and the horizontal drive pulse, and is output to the double speed conversion circuit 105.

Next, the double speed conversion circuit 105 inputs the actual signal and interpolation signal created by the motion adaptive scanning line interpolation circuit 104,
The data is written to the line memories 105a and 105b, respectively.

At that time, each line memory 105a, 105b is reset by the vertical period write reset signal (WR) inputted from the decoder 116, and from that point on,
The actual signal and interpolation signal from the motion adaptive scanning line interpolation circuit 104 are written in synchronization with a write clock 123 having a frequency of 4 fsc inputted from the frequency dividing circuit 122 .

Then, each line memory 105a, 105b is reset by a vertical cycle read reset signal (RR) 114 inputted from the timing generation circuit 110, and from that point on, the oscillation output 125 of the crystal oscillation circuit 124
The data is read out in synchronization with the read clock.

As described above, according to the present embodiment, a very stable read clock, which is the oscillation output 125 of the crystal oscillation circuit 124, is used to read signals from each line memory 105a, 105b in the double speed conversion circuit 105. So,
The double speed conversion circuit 105 can perform double speed conversion and also perform time axis correction of the signal.

Therefore, even if a signal including time axis fluctuations reproduced from a video tape recorder or the like is manually input as the standard television signal 101, the time axis fluctuations can be sufficiently removed.
The double-speed converted signal can be displayed on the display 126, and the circuit scale does not increase.

Next, FIG. 6 is a block diagram showing still another embodiment of the present invention.

In FIG. 6, 127 is a band pass filter, 128
is a clock generation circuit. This clock generation circuit 12
8 is a phase comparator 128a and a low-pass filter 128
b. Voltage controlled oscillation circuit 128c.

It is composed of a PLL circuit consisting of a frequency dividing circuit 128d. Other components that are the same as those in FIG. 5 are given the same reference numerals.

In this embodiment, instead of the crystal oscillation circuit 124,
Clock generation circuit 1 that generates a clock synchronized with the color burst signal included in the standard television signal 101
The feature is that 28 is used.

The operation of this embodiment is basically the same as that of the embodiment shown in FIG. 5, so only the different parts will be mainly explained.

From the input standard television signal 101, only the color signal band is extracted by the bandpass filter 127, and the output color burst signal is sent to the clock generation circuit 12.
8.

The input color burst signal is sent to the phase comparator 128a.
, the phase of the color burst signal is compared with a clock from the frequency dividing circuit 128d having the same frequency as the frequency fsc of the color burst signal. The comparison result is input to the voltage controlled oscillation circuit 128c via the low-pass filter 128b, and the oscillation frequency is controlled by the voltage controlled oscillation circuit 128c.
A clock having a frequency of 8f is generated in synchronization with the color burst signal. This clock is then input to the frequency divider circuit 128d, frequency-divided by 8, and input to the phase comparator 128a as described above as a clock having the same frequency as the frequency fsc of the color burst signal.

In general, color burst signals included in standard television signals, including signals reproduced from video tape recorders, etc., are stable with little time axis fluctuation. By generating a clock based on the burst signal using the clock generation circuit 128 constituted by a PLL circuit, very stable locking can be obtained.

Then, by using this clock as a read clock when reading signals from each line memory 105a, 105b in the double speed conversion circuit 105, the double speed conversion circuit 105 performs double speed conversion, similar to the embodiment shown in FIG. At the same time, it is possible to perform time axis correction of the signal.

Therefore, even if a signal including time axis fluctuations reproduced from a video tape recorder etc. is input as the standard television signal 101, the time axis fluctuations are sufficiently removed.
The double-speed converted signal can be displayed on the display 126, and the circuit scale does not increase.

In each of the above embodiments, the present invention is applied to a television receiver, which is one of the image display devices, as an example. However, the present invention also applies to other image display devices. For example, it can be applied to monitors, projection tubes, etc.

[Effects of the Invention] As described above, according to the present invention, in an image display device having a display in which the aspect ratio of the displayed image is different from that of the standard television signal, the standard television signal is compressed by the compressor. By compressing the image in the time direction and then displaying it on a display, the image can be displayed without distortion. Moreover, even when displaying images based on standard television signals, the scanning of the electron beam on the display covers the entire screen.
Even if only images based on standard television signals are displayed, the phosphor on the display screen will not deteriorate unevenly, and the circuit configuration itself will be simple.

Furthermore, when the standard television signal is read out from the storage section in the compression means, it is read out in synchronization with a very stable oscillation output from a crystal oscillation circuit, etc., so the compression means compresses the signal. At the same time, it is also possible to perform time axis correction of the signal. In addition, by reading out the signal separately into the video period part and the black level period part,
Even if the signal is read out so that the video period part is displayed in the center of the screen on the display, the black level period part can be read out so that it is included in the horizontal blanking period, so the black level can be reproduced correctly. be able to.

Further, according to the present invention, the aspect ratio of the displayed image is equal to the aspect ratio of the standard television signal, and the number of scanning lines of the standard television signal is N.
(N is an integer of 2 or more) In an image display device that displays a standard television signal by multiplying it, when reading a standard television signal from the storage section in the N-times speed means, it is synchronized with a very stable oscillation output from a crystal oscillation circuit, etc. Since the signal is read out, the N-time speed means can perform double speed conversion and also perform time axis correction of the signal.

Therefore, even if a signal containing time axis fluctuations reproduced from a video tape recorder etc. is input as the standard television signal, the time axis fluctuations are sufficiently removed and the signal is double-speed converted without time axis fluctuations. can be displayed on the display without increasing the circuit scale.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram showing main signal waveforms in FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a block diagram showing another embodiment of the present invention. FIG. 6 is a block diagram showing still another embodiment of the present invention. The figure is an explanatory diagram for explaining the display results when an image based on a standard television signal with an aspect ratio of 4:3 is displayed on a horizontally long display with an aspect ratio of 16:9 in the conventional example and the present invention. be. Explanation of symbols 101...Standard television signal, 102...A/
D converter, 103...Motion adaptive Y/C separation circuit, 1
04... Motion adaptive scanning line interpolation circuit, 105... Double speed conversion circuit, 106... Synchronization separation circuit, 107...
Clock generation circuit, 108...Crystal oscillation circuit, 109
...Horizontal drive pulse generation circuit, 110...Timing generation circuit, 111.119...Gate circuit, 116
...Decoder, 117...Compression circuit, 120...
D/A converter, 121...Display. Agent Patent Attorney Akio Namiki Diagram (e) ++s Target feather - [-what ■■ Toto soil (i) 108 m1 plate Hiichi ■Tomo

Claims (1)

[Claims] 1. In an image display device having a display in which the aspect ratio of a displayed image is different from that of a standard television signal, a first oscillating means that oscillates at a predetermined frequency; horizontal drive pulse generation means for generating a horizontal drive pulse for driving the display based on the oscillation output of the oscillation means; a second oscillation means for oscillating in synchronization with the standard television signal; and a storage section. and inputting the standard television signal, writing it into the storage section in synchronization with the oscillation output from the second oscillation means, and oscillating the written standard television signal from the first oscillation means. By reading from the storage unit in synchronization with the output,
compression means for compressing and outputting the standard television signal in the time direction, and compressing the standard television signal written in the storage section of the compression means at least twice during one period of the horizontal drive pulse. An image display device comprising: control means for controlling the compression means so as to read the data separately. 2. In an image display device having a display in which the aspect ratio of a displayed image is different from that of a standard television signal, a first oscillation means that oscillates at a predetermined frequency, and an oscillation output of the first oscillation means are provided. horizontal drive pulse generation means for generating a horizontal drive pulse for driving the display based on the horizontal drive pulse, a second oscillation means for oscillating in synchronization with the standard television signal, and inputting the standard television signal; It has an N-times speed means for multiplying the number of scanning lines of the standard television signal by N times (N is an integer of 2 or more) and outputs it, and a storage section, and inputs the standard television signal from the N-times speed means. , writing into the storage section in synchronization with the oscillation output from the second oscillation means, and reading out the written standard television signal from the storage section in synchronization with the oscillation output from the first oscillation means. Compressing means compresses and outputs the standard television signal in the time direction, and compresses the standard television signal written in the storage section of the compressing means during one period of the horizontal drive pulse.
An image display apparatus comprising: a control means for controlling the compression means so as to read the data in at least two parts. 3. The image display device according to claim 1 or 2,
The control means converts the standard television signal written in the storage section of the compression means into one of the horizontal drive pulses.
An image display device characterized in that the compression means is controlled to read out a video period portion and a black level period portion separately during a period. 4. The image display device according to claim 3, wherein between the video period portion and the black level period portion of the standard television signal compressed in the time direction output from the compression means,
An image display device characterized by adding a frame signal that is displayed as a frame when displayed on the display. 5. In an image display device having a display in which the aspect ratio of a displayed image is different from that of a standard television signal, a first oscillation means that oscillates at a predetermined frequency, and an oscillation output of the first oscillation means are provided. horizontal drive pulse generation means for generating horizontal drive pulses for driving the display based on the standard television signal; second oscillation means for oscillating in synchronization with the standard television signal; input a standard television signal, write a signal obtained from the standard television signal into the storage section in synchronization with the oscillation output from the second oscillation means, and write the written signal into the storage section. N times the speed of reading the standard television signal from the storage unit in synchronization with the oscillation output, increasing the number of scanning lines of the standard television signal by N times (N is an integer of 2 or more), compressing it in the time direction, and outputting the same.・Compression means and the N times speed ・The signal written in the storage section of the compression means,
An image display device comprising: control means for controlling the N-times speed/compression means so as to read data at least twice during one period of the horizontal drive pulse. 6. The image display device according to claim 5, wherein the control means converts the signal written in the storage section of the N-times speed/compression means into a video period part during one cycle of the horizontal drive pulse. controlling the N-time speed/compression means to read the signal separately from the black-level period part, and between the video period part and the black-level period part of the standard television signal outputted from the N-time speed/compression means; An image display device characterized by adding a frame signal that is displayed as a frame when displayed on the display. 7. In an image display device having a display in which the aspect ratio of a displayed image is equal to the aspect ratio of a standard television signal, a first oscillation means that oscillates at a predetermined frequency, and an oscillation output of the first oscillation means. horizontal drive pulse generation means for generating horizontal drive pulses for driving the display based on the standard television signal; second oscillation means for oscillating in synchronization with the standard television signal; input a standard television signal, write a signal obtained from the standard television signal into the storage section in synchronization with the oscillation output from the second oscillation means, and write the written signal into the storage section. N-times speed means for outputting the standard television signal with the number of scanning lines multiplied by N (N is an integer of 2 or more) by reading from the storage unit in synchronization with the oscillation output. An image display device characterized by: 8. In an image display device having a display in which an aspect ratio of a displayed image is equal to an aspect ratio of a standard television signal, a first oscillation means that oscillates in synchronization with a color burst signal included in the standard television signal; , horizontal drive pulse generation means for generating horizontal drive pulses for driving the display based on the oscillation output of the first oscillation means, and second oscillation means for oscillating in synchronization with the standard television signal. and a storage section, inputs the standard television signal, and writes a signal obtained from the standard television signal into the storage section in synchronization with the oscillation output from the second oscillation means. By reading out the signal from the storage section in synchronization with the oscillation output from the first oscillation means, the standard television signal is
An image display device comprising: N times speed means for multiplying the number of scanning lines by N times (N is an integer of 2 or more) and outputting the multiplied number.