JPS62100089A - Ultra-fine signal converting device - Google Patents

Abstract

PURPOSE:To obtain a normal picture even when a jitter is included in a video signal by forming a synchronizing signal phase-locked from a composite video signal of VTR to a horizontal synchronizing signal and making this into the synchronizing signal of the double speed circuit. CONSTITUTION:The composite image signal of VTR is applied to a PLL circuit 9, phase-locked from a 1/2 frequency dividing circuit 14 to the horizontal synchronizing signal, the first synchronizing signal C having the double frequency is outputted and this used through a waveform shaping circuit 16 as the synchronizing signal for the display. The second synchronizing signal D of the same period as the horizontal synchronizing signal from the second 1/2 frequency dividing circuit 15 is outputted, and this is inputted to a load signal generating circuit 17. The load signal generating circuit 17 generates the load signal to a counter circuit 18 for generating the line memory address signal to execute the double speed from the second synchronizing signal D and the quadruple sub-carrier signal 4fSC.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides an image processing system that uses the NTSC method to obtain high-quality images on a desktop. The present invention relates to a high-definition signal converter that converts a high-definition video signal into a high-definition video signal and supplies it to a display. This relates to the low 1 signal generation circuit of the line memory address signal generation counter in the speed doubling circuit.

[The backbone of invention]

Progress in digital processing techniques i and ji for television images 1. This is accompanied by N'rsc, two-way television broadcast waves, 1
'-゛Deodeo diffuser player, television camera, VTR (
The development of high-definition signal converters that can improve the quality of video signals from video tape recorders and other devices by making the most of the image information contained therein is underway.

The conventional high-definition signal conversion device is described in the document (a) [Achiba 1 Ishikura: Proposal of a motion-adaptive high-definition signal conversion method for color television signals: Television Society of Japan 1982 National Annual Conference (7-2)]. As described, it is a signal conversion device that improves the definition of video signals that do not include jitter (time axis fluctuations), such as color television signals, and that converts video signals that do not include jitter (time axis fluctuations), such as color television signals, to high definition. No consideration was given to the possibility of increasing the definition of the included signals.

Regarding conventionally known high-definition signal conversion devices, Part 6
The outline will be explained using figures.

FIG. 6 is a block diagram showing a conventional example of a high-definition signal conversion device. In the figure, a video signal to be converted into a high-definition signal is converted from an analog signal to a digital signal by an AD converter 1, and is input to a frame memory 2 having a capacity equivalent to at least one frame. . The output read from the frame memory 2 is the YC portion IT circuit 3.
Here, it is separated into a luminance signal Y and a color signal C, and the signals are input to a scanning line interpolation circuit 4.

The scanning line interpolation circuit 4 receives the input luminance signal Y and color signal C.
, the 525 scanning lines by the ink-lace scanning method are converted into 525 scanning lines by the non-inclace scanning method and output.

The non-inclaced scanning line output from the scanning line interpolation circuit 4 is input to the doubling speed circuit 5. The doubling speed circuit 5 is composed of a line memory having a storage capacity equivalent to at least one line (scanning line), and the write frequency per 1,000 scanning lines to the memory is 15 degrees, which is the same as the normal horizontal scanning frequency. 734kHz, and the readout speed is twice that, 31.468kHz.
Double the speed. The output of the doubling speed circuit 5 is converted from a digital signal to an analog signal by a DA converter 6, and is supplied to the display as a high-definition signal.

Further, in FIG. 6, 7 is a synchronization separation circuit that separates and outputs horizontal and vertical synchronization signals from the input video signal, and these horizontal and vertical synchronization signals that are separated and output are input to the synchronization signal generation circuit S. be done. Synchronous signal generation circuit S
The frequency is 4fsc (Esc is the subcarrier frequency and 3.
A circuit that generates a clock pulse of 58MH, ) and supplies it to the doubling speed circuit 5, a circuit that generates a signal to control the frame memory 2, a circuit that generates a signal for scanning line interpolation and supplies it to the scanning line interpolation circuit 4. A supply circuit, a circuit that generates a signal to control the line memory in the double speeding circuit 5, and a circuit for supplying the signal to the display.
Consists of circuits that generate signals and other components.

In the conventional high-definition signal converter as described above, when a video signal output from a VTR is input, the video signal contains jitter, so it has the following problems and cannot function normally. It was not possible to display a proper image.

The problems will be explained below. In other words, taking a still image as an example, the phase of the subcarrier in the first frame and the second frame is reversed in the NTSC direction, so if the video signal in the first frame is (Y+C), the phase of the subcarrier in the first frame and second frame is reversed. The video signal in a frame can be expressed as (Y-C). Therefore, the luminance signal Y can be obtained by adding the video signal of the first frame and that of the second frame and dividing the sum by 1/2. Further, the color signal C can be obtained by subtracting the video signal of the second frame from the video signal of the first frame and dividing the signal by half.

As mentioned above, in order to perform YC separation, the current signal (video signal of the first frame), one frame period from it,
In other words, a signal (video signal of the second frame) delayed by a period of 525H (H is a horizontal scanning period of 63.5 μs) is required. In principle, the frame memory 2 shown in FIG.
It can be said that it is for outputting after a period of delay.

On the other hand, in the double speed circuit 5 in FIG. 6, reading and writing to the line memory included therein are as follows.
The output of the counter with the load signal as star 1- is used as the address scanning signal.

As this load signal, a signal H having a repetition frequency obtained by dividing the clock pulse repetition frequency 4f,c (14,318MH,) by 1/910 is used. This relationship is shown in the formula below.

Repetition frequency of load signal H5 -4f, c/910=
15.734kHz, (1) Normal NTSC
In the video signal based on this method, the currently received video signal, the video signal read out from the frame memory and delayed by 525H period, and the load signal H5 have the same phase. This situation is shown in FIG. 7(A).

On the other hand, in the case of a video signal including jitter, such as an output signal from a VTR, the currently received video signal, the video signal read out from the frame memory, and the load signal H9
Their phases do not match. Figure 7(B) shows how they do not match.

For this reason, normal image display cannot be performed.

[Purpose of the invention]

An object of the present invention is to enable normal image display even when a video signal containing jitter, such as an output video signal from a VTR, is converted into a high-definition signal through a high-definition signal converter and supplied to a display. The object of the present invention is to provide such a high-definition signal converting device.

[Summary of the invention]

In order to achieve the above object, the high-definition signal conversion device according to the present invention includes a first 1U1 signal f11 of the same horizontal scanning period that is phase-locked with a horizontal synchronizing signal separated from a video signal from a VTR, and a frequency twice that frequency. P L L outputs a second synchronization signal 2rs having a value of 2 rs.

A circuit is prepared and the second synchronization signal 2f is used as a display synchronization signal.

In addition, the first synchronization signal f is input, and 4f, c(r-
A shift register is supplied with a pulse signal having a repetition frequency of a subcarrier frequency of 3.58 MH, as a clock, and a logical operation circuit performs a logical operation on the output thereof. synchronization signal f
A signal whose phase has been lost to I+ is generated as a load signal for the address signal generation counter of the line memory to double the speed, so that even video signals from a VTR containing jitter can be displayed normally. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. In the figure, 8 is a synchronization separation circuit for separating a horizontal synchronization signal from a composite video signal from a VOR, and 9 is a P1
．． , L circuit (face locked loop circuit), 1
0 is a phase comparator circuit, 11 is ■.

PF (low pass filter), 12 is a vcoc voltage controlled oscillator), 13 is a 4-bit binary counter, 14.1
5 are 1/2 frequency divider circuits each forming the counter 13;
16 is a waveform shaping circuit for setting the pulse width of the output pulse of the frequency dividing circuit 14 to be equal to the pulse width of the horizontal synchronizing pulse; 17 is a loader for generating a load signal for the line memory address signal generation counter; The signal generation circuit 18 is a line memory address signal generation counter circuit.

Figure 2 is a waveform diagram of the signals of each part of the circuit 6 in Figure 1;
It is.

The circuit operation will be explained with reference to FIGS. 1 and 2.

Now, when a composite video signal from a VTR is applied to the input of the synchronization separation circuit 8, a synchronization component h■ output shown in FIG. 2A is obtained. If the equalization pulse is removed from the output shown in FIG. 2A, the signal shown in FIG. 2B is obtained. This horizontal period (6
A signal of 3°5 μs (hereinafter referred to as f) is sent to the phase comparator circuit 1.
0 to one side.

Next, the phase comparison circuit 10 compares the phases of the output of the synchronous separation circuit 8 and the output of the frequency division circuit 15, and the output of the phase comparison circuit 10 is applied to LPFII, and the output is applied to the VCO 12? ;Add two. The output frequency of VCO12 is 4 fH (62,
9k H,).

In addition, the 4-bit binary counter 13 divides the frequency by 1/2, and
By dividing the frequency by /4, the output of the frequency dividing circuit 14 becomes the second
As shown in C in the figure, a signal with a frequency of 2fH is generated, and the output of the frequency dividing circuit 15 is a signal with a frequency of fH as shown in D in FIG.
It becomes a signal. The duty ratio of these pulse signals is 5
It is 0%.

The output of the frequency dividing circuit 14 is made into a pulse width equal to that of the horizontal synchronizing pulse as shown in E in FIG. 2 by the waveform shaping circuit 16, and is sent to the display as a horizontal synchronizing signal. Further, the output of the frequency dividing circuit 15 is input to the load signal generating circuit 17.

FIG. 3 is a circuit diagram showing a specific example of the load signal generation circuit 17 in FIG. 1.

In the figure, numeral 19 denotes a waveform shaping circuit which receives the output of the frequency dividing circuit 15 in FIG. 1 and shapes the waveform. 20
is 4f as the clock, (f, , is the subcarrier frequency 3
．． This is a shift register that uses a pulse signal with a repetition frequency of 58MH, ). In a high-definition signal converter, one line is composed of 910 dots, so the load signal of the line memory address signal generation counter must have the following pulse width.

1 dot period = 63.5μs/910 dots = 70n
s (2) From the above equation, the load signal has a horizontal period and a pulse width of 70 ns. Therefore, the shift register 20 shown in FIG. 3 will be used.

FIG. 4 shows a time chart of various signals in the load signal generation circuit 17 shown in FIG.

Returning to FIG. 3, if the signal whose waveform has been shaped by the waveform shaping circuit 19 is ID, then the outputs of the shift register 20 IQ, 2Q
, 3Q, and 4Q have waveforms as shown in FIG. 4, respectively.

Then, a logical operation is performed according to the following logical formula to generate a load signal.

Load signal -');-2Q・3Q ・・・・・・
(3) The logical operation using this logical formula is the NA in Figure 3.
This can be realized by the ND gate 21.

The signal thus obtained is input as a load signal to the line memory address signal generation counter circuit 18 shown in FIG.

As a result, as shown in FIG. 5, the phase of the horizontal synchronizing signal extracted from the VTR output video signal and the phase of the load signal are always stable even when the VTR output video signal contains jitter. can be matched.

〔Effect of the invention〕

According to the present invention, it is possible to always stably match the phases of the horizontal synchronization signal in the VTR output video signal and the load signal of the line memory address signal generation counter, so that the line memory address signal is always kept in a stable state. This has the advantage that even a video signal including jitter, such as a VTR output video signal, can be effectively made high-definition.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, FIG. 2 is a waveform diagram of signals in each part of the circuit shown in FIG. 1, and FIG. 3 is a specific example of the load signal generation circuit 17 in FIG. A circuit diagram showing an example, Fig. 4 is a time chart of various signals in the circuit of Fig. 3, and Fig. 5 shows how the phases of the video signal, horizontal synchronization signal, and load signal stably match according to the present invention. Fig. 6 is a block diagram showing a conventional high-definition signal conversion device, and Fig. 7 compares cases where the video signal and the phase of load No. 18 are lost and cases where they do not match. FIG. Code explanation

Claims (1)

[Scope of Claims] 1) In a high-definition signal conversion device including a doubling speed circuit, as a load signal generation circuit of a line memory address signal generation counter in the doubling speed circuit, an input image that may include time axis fluctuations is used. A horizontal synchronization signal separated from the signal is input, and a first synchronization signal f_H with a horizontal scanning period whose phase is locked to the horizontal synchronization signal and a second synchronization signal 2f_H with twice the frequency thereof are output. A face-locked loop circuit (hereinafter referred to as PLL)
circuit) and the first synchronization signal f_H from the PLL circuit as input signals, 4f_s_c (however, f_s_
c is a subcarrier frequency), and a logic operation circuit that performs a logic operation on the output from the shift register. A load signal generation circuit configured to generate a load signal whose phase matches that of the first synchronization signal f_H is used, and the PLL
A high-definition signal conversion device characterized in that the second synchronization signal 2f_H outputted from the circuit is outputted toward a display as a display synchronization signal.