JP3118809B2 - Synchronous circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous circuit used for video signal format conversion and the like.

[Summary of the Invention]

The present invention relates to a synchronization circuit, and obtains synchronization using a reference pulse obtained by dividing a synchronization signal of an input video signal and a comparison signal obtained by dividing a clock signal. And the like in such a manner as to achieve good synchronization.

[Conventional technology]

It has been proposed to process a video signal using a video memory having a plurality of ports.

In this case, if the speeds of the write side and the read side of the memory are not synchronized, an overtaking occurs between the write address and the read address, and a temporal skip of one field occurs at that moment. In particular, in the case of a video signal in which the movement of the subject is fast, the image quality may be significantly deteriorated, for example, a step may occur in the image.

Therefore, a synchronization circuit as shown in FIG. 6 has been conventionally proposed. That is, in the figure, the variable frequency oscillator (VX
O) The read-side clock signal generated in (51) is supplied to the synchronization generation circuit (52) to generate horizontal and vertical synchronization signals. The generated horizontal synchronizing signal (HD) is converted into a comparison signal having a duty of, for example, 50% by the pulse generation circuit (53) and supplied to the phase comparator (54). Input terminal (55)
Is supplied with a reference signal having a vertical period on the writing side, and this signal is supplied to the phase comparator (54). The comparison output is converted to a direct current by the low-pass filter (56), inverted, and supplied to the VXO (51).

Therefore, in this circuit, for example, a comparison signal as shown in FIG. 7A is generated from the pulse generator (53), and a reference signal as shown in FIG. B is supplied to the input terminal (55). Is supplied to the phase comparator (54).
As a result, a comparison output as shown in FIG. This comparison output is supplied to a low-pass filter (56) to be a control voltage as shown in FIG.

When the control voltage is supplied to the VXO (51), the control signal is generated in the VXO (51) so that the phase of the comparison signal supplied to the comparator (54) and the phase of the reference signal have a predetermined relationship. The clock signal is controlled, and a so-called PLL is configured to synchronize the writing side and the reading side.

[Problems to be solved by the invention]

However, in the above-described synchronization circuit, when the synchronization frequencies of the writing side and the reading side are different from each other, as in the case of the so-called television system conversion, these synchronizations cannot be obtained. Therefore, the above-mentioned circuit cannot be applied to system conversion.

In the conventional method conversion, a synchronization device having an extremely complicated circuit configuration is used, which causes a problem such as an increase in the price and size of the device.

The present application has been made in view of such a point, and provides a synchronous circuit that can be applied to the system conversion with a simple configuration by applying the above-described circuit.

[Means for solving the problem]

According to the present invention, an input video signal is written to a memory according to a synchronization signal thereof, and the written signal is read out according to a synchronization signal formed from a clock signal generated by a variable frequency oscillator (VXO (14)) to output an output video signal. To form the first horizontal synchronization signal HD 'of the input video signal.
The reference pulse once (n is a positive integer) obtained every n frames obtained by frequency division (frequency divider (7)) at the frequency division ratio of (15)), and is formed only in a period of 1 / m (m is a positive integer) of the reference pulse obtained in the period (Sync ON) of the input video signal (OR circuit (11)). )) The phase of the comparison signal is compared with that of the comparison signal (comparator (12)), and the comparison output is fed back to the variable frequency oscillator to form a PLL.
Is selected based on the common divisor of the synchronization frequency of the input video signal and the output video signal, and the frequency of the clock signal, respectively.

[Action]

According to this, the reference signal and the comparison signal are obtained by dividing the original signal, and the division ratio is selected. Therefore, even when the synchronization frequencies on the writing side and the reading side are different, the synchronization is achieved. , And good synchronization at the time of system conversion can be achieved.

〔Example〕

FIG. 1 shows a circuit for synchronously generating a synchronizing signal (vertical and horizontal addresses) on the reading side based on a video signal on the writing side. Here, the video signal is, for example, a first system having a field frequency of about 60 Hz and 525 scanning lines (hereinafter referred to as NTSC system) and a second system having a field frequency of 50 Hz and 625 scanning lines (hereinafter PAL system). )).

In this figure, (1) and (2) are input terminals to which a vertical synchronizing signal VD and a horizontal synchronizing signal HD of a video signal on the writing side are supplied, respectively. These input terminals (1) and (2)
Is supplied to the timing adjustment circuit (3) to adjust the delay time during processing. The adjusted vertical synchronizing signal VD 'is supplied to the gate circuit (4), and the adjusted horizontal synchronizing signal HD' is supplied to a frequency divider (5) comprising a counter and a decoder. An output signal from the device (5) is supplied to an enable terminal of the gate circuit (4). Further, the output signal of the gate circuit (4) is supplied to the clear terminal of the frequency divider (5). The frequency divider (5) stops counting at a predetermined count value.

Thereby, the vertical synchronization signal V is output from the gate circuit (4).
A signal of sync-on (Sync.ON) corresponding to the period of D 'is output, and this output signal is passed through an inverter (6) to an overtaking control OR circuit (1) provided in a PLL described later.
Supplied to 1).

The horizontal synchronizing signal HD 'is supplied to a frequency divider (7), which will be described later, and the output signal from the frequency divider (7) is supplied to a flip-flop (8). Signal) is formed. This reference signal is supplied to a comparator (12) provided in the PLL.

Further, a comparison output from the comparator (12) is supplied to a variable oscillator (VXO) (14) through a low-pass filter (13). An oscillation signal from the oscillator (14) is supplied to a frequency divider (15) described later, and an output signal from the frequency divider (15) is supplied to a flip-flop (16).
A 50% divided signal is formed. The frequency-divided signal is supplied to an OR circuit (11) through a NOR circuit (17) for overtaking control, and a signal from the OR circuit (11) is supplied to a comparator (12) as a comparison signal.

This forms a PLL, and from the oscillator (14),
A pixel clock signal synchronized with the reference signal from the flip-flop (8) is output.

The pixel clock signal from the oscillator (14) is supplied to the counter (21), and the clock signal is counted. The count value is supplied to the decoder (22), for example, the count value of 909 is decoded, and the output signal at this time is supplied to the clear terminal of the counter (21).

Further, an output signal from the decoder (22) is supplied to an enable terminal of a counter (23), and the pixel clock signal is also supplied to the counter (23).
Therefore, in the counter (23), the clock signal when the signal is supplied to the enable terminal is counted, and this count value is supplied to the decoder (24). The decoder (24) decodes, for example, the count values of 261 and 262 when the read side is of the NTSC system, and 311 and 312 when the read side is of the PAL system, and outputs the output signal at this time to an AND circuit (2
5), and an output signal from the decoder (22) is supplied to an AND circuit (25), and the AND circuit (25)
Is supplied to the clear terminal of the counter (23).

An output signal from the AND circuit (25) is supplied to an enable terminal of a D-type flip-flop (26), and a pixel clock signal is supplied to the flip-flop (26).
The output of the flip-flop (26) is fed back to the D terminal, and an odd / even field identification signal is taken out from the Q output of the flip-flop (26). This Q
The output signal is supplied to the decoder (24),
Switching between 62, 311 and 312 is performed.

As a result, the horizontal counter output (count value) corresponding to the horizontal pixel position and the vertical counter output (count value) corresponding to the vertical scanning line position are extracted from the counters (21) and (23). These count values are supplied to output terminals (27) and (28) connected to an address control system of a video memory (not shown).

At the same time, the vertical counter output from the counter (23) is supplied to the decoder (31). In this decoder (31), for example, the reading side is the NTSC system and the PA
A decoded output as shown in the following Table 1 is taken out according to the case of the L system.

Of the decoded outputs of the decoder (31), A and B are the J terminal and K of the JK flip-flop (32), respectively.
C and D are supplied to the J and K terminals of the JK flip-flop (33), respectively, and E and F
Are supplied to the J terminal and the K terminal of the JK flip-flop (34), respectively, and G and H are supplied to the J terminal and the K terminal of the JK flip-flop (35), respectively.

Further, the above-described pixel clock signal is also supplied to these flip-flops (32) to (35). The Q output signals of the flip-flops (32) and (33) are supplied to the OR circuit (36), and the Q output signals of the flip-flops (34) and (35) are
An output signal is supplied to an OR circuit (37), and output signals of these OR circuits (36) and (37) are supplied to D terminals of D-type flip-flops (38) and (39), respectively. The above-mentioned pixel clock signal is also supplied to these flip-flops (38) and (39), and the signal from the edge detection circuit (9) supplied with the pixel clock signal and the vertical synchronizing signal VD 'is supplied to the flip-flop (38). 38) It is supplied to the enable terminal of (39).

As a result, the Q output of the flip-flop (38)
For example, the phase of the vertical synchronization signal VD 'on the writing side is in the range of 400 to 13 and 143 to 276 (NTSC) in the vertical counter output on the reading side,
Alternatively, a control signal for increasing the frequency (FUP) is output in the range (PAL) of 474-5 and 166-317. On the Q output of the flip-flop (39), the phase of the vertical synchronizing signal VD 'is a vertical counter output in the range of 17-143 and 280-400 (NTSC), or 9-166 and 321-474 (PAL).
At this time, a control signal of frequency drop (FDN) is output.
The FUP control signal from the flip-flop (38) is supplied to the NOR circuit (17), and the flip-flop (3
The FDN control signal from 9) is supplied to the OR circuit (11).

Further, in this circuit, the frequency divider (5)
(7) The frequency division ratio of (15) is determined as shown in Table 2 below.

Accordingly, in this circuit, the frequency dividers (5) and (7) output 1 in the case of NTSC → NTSC, PAL → PAL, and PAL → NTSC, respectively.
A reference signal is generated once per frame and once every three frames in the case of NTSC → PAL, and from the frequency divider (15), NTSC → NTS
1/35 frame cycle for C, PAL → PAL, PAL → NTSC, NTSC
→ In PAL, a frequency-divided signal is generated every 3/35 frame period (however, the frequency-division ratio is alternately the number in Table 2). These signals are compared by the comparator (12), so that mutually synchronized pixel clock signals can be obtained.

That is, in the circuit described above, for example, a comparison signal as shown in FIG. 2A is generated from the OR circuit (11), and a reference signal as shown in FIG. B is generated from the flip-flop (8). Is supplied to the comparator (12). As a result, a comparison output as shown in FIG. This comparison output is supplied to a low-pass filter (13) to be a control voltage as shown in FIG. Further, by supplying this control voltage to the VXO (14), the clock signal generated in the VXO (14) is controlled so that the phase of the comparison signal and the phase of the reference signal have a predetermined relationship, and the PLL is locked. The writing side and the reading side are synchronized.

In this case, the cycle of the comparison signal is 1/35 frame cycle or 3/35 frame cycle, and the cycle of the reference signal is 1
By setting the frame period or the three-frame period, good synchronization can be achieved even when the system is converted from PAL to NTSC or NTSC to PAL.

Further, in this circuit, the above-mentioned control signals for FUP and FDN are prevented from being at the high level at the same time. The control signal (FUP, FDN), the above-mentioned Sync.ON signal, the reference signal, and the frequency-divided signal control the comparison output of the comparator (12) as shown in Table 3 below.

In Table 3, L is low level, H is high level, Z is high impedance, and * is undefined.

And this comparison output is inverted low-pass filter (1
By being supplied to VXO (14) through 3), control is performed so that the oscillation frequency increases when the input voltage is high.

Thus, for example, when the reading side is of the NTSC system, the output of the vertical counter is as shown in FIG. 3A, whereas when the writing side is also of the NTSC system, as shown in FIG.
The control signal of the FDN is generated, and the driving is performed in the range indicated by the double line in the figure. When the writing side is the PAL system (system conversion), control signals for FUP and FDN are generated as shown in FIG.

On the other hand, when the reading side is the PAL system, the vertical counter output is as shown in FIG.
In the case of the L system, control signals for FUP and FDN are generated as shown in FIG. Further, when the writing side is of the NTSC system (system conversion), control signals of FUP and FDN are generated as shown in FIG.

Therefore, in this circuit, PAL
→ In the conversion of NTSC, writing (solid line) and reading (dashed line) are performed as shown in FIG. 5A, and in the conversion of NTSC → PAL, FIG.
As shown in (1), writing and reading are performed, and in either case, the PLL can be locked so that overtaking occurs outside the screen below the screen.

Thus, according to the above-described circuit, the reference signal and the comparison signal are obtained by dividing the original signal, and the division ratio is selected. Therefore, when the synchronization frequencies on the write side and the read side are different, In this case, synchronization can be achieved, and good synchronization can be achieved when performing system conversion.

In the above-described circuit, the lock point of the PLL, that is, the number of periods per frame of the frequency-divided signal is determined by the design concept described below.

The maximum frequency variable width Δf _max of VXO (14) is expressed as a percentage, and x% Then, in order to avoid false lock, the number of lock points during the phase comparison cycle is Or less (integer value), and considering the deviation of the center frequency f and the variation of Δf _max , the maximum lock point
It is better to keep it at about 1/3 or less.

When a simple tri-state buffer or the like is used as the phase comparator, the interval between the lock points is two times the width of the reference signal.
If it is not more than twice, correct operation cannot be expected.

Therefore, first, in the case of PAL → NTSC, the time of 5 fields on the writing side = the time of 6 fields on the reading side, and if the number of clocks in one horizontal period is 910 [CK], Becomes Here, since the comparison signal must be formed by a counter and the time of one frame on the writing side must be divided by an integer, the number of lock points must be a divisor of (1). ‥‥ On the other hand, the above condition is that x = ± 0.3% when lithium tantalate is used for VXO (14), The condition from is 111 or less.

Further, if the above-mentioned condition is such that a signal having a width of, for example, three horizontal periods is used as the reference signal, this width is expressed by the number of clocks on the reading side. And dividing the value of (1) above by this number of clocks,
Is 104 or less.

Therefore, the number of lock points satisfying these conditions is [100,98,91,90,84,78,75,70,65,63,60,52,50,49,4
5,42,39,36,35,30,28,26,25,21,20,18,15,14,13,12,10,
9,7,6,5,4,3,2].

Next, in the case of NTSC → PAL, the time of 6 fields on the writing side = the time of 5 fields on the reading side, and if the number of clocks in one horizontal period is 910 [CK], Becomes Here, similarly to the above, it is necessary to form a comparison signal by a counter and divide the time of one frame on the writing side by an integer. In this case, since the value of (2) is not an integer, the writing side must be divided. as compared with 3 frame periods, the write side 3 frames of time = 5 ⁶ × 7 × 13 [CK] ‥‥ (2 '), and the number of locking points (2' must be a divisor of) . ‥‥ One condition is 111 or less as described above.

Also, assuming that a signal having a width of 3 horizontal periods is used as a reference signal, this width is expressed in terms of the number of clocks on the read side. By dividing the value of (2 ') by the number of clocks, the condition becomes 262 or less.

Therefore, the number of lock points satisfying the conditions of these is [91,65,35,25,13,7,5].

More For NTSC → NTSC, write side frame time = 525 × 910 = 2 × 3 × 5 3 × 7 2 × 13 [CK] ‥‥ (3), and the number of locking points is the (3) Must be divisor. ‥‥ One condition is 111 or less as described above.

As another condition, if a signal having a width of 3 horizontal periods is used as the reference signal, the width is 3 × 910 [CK], and the value of (3) is divided by the number of clocks to obtain
Is less than 87.

Therefore, the number of lock points satisfying these conditions is [78,75,70,65,50,49,42,39,35,30,26,25,21,15,1
4,13,10,7,6,5,3,2].

For PAL → PAL The writing side frame time = 625 × 910 = 2 × 5 5 × 7 × 13 [CK] ‥‥ (4), and the number of locking points is about the number of (4) There must be. ‥‥ One condition is 111 or less as described above.

Another condition is that if a signal having a width of 3 horizontal periods is used as the reference signal, the width is 3 × 910 [CK], and the above value (4) is divided by the number of clocks to obtain
Is 104 or less.

Therefore, the number of lock points satisfying the conditions of these is [91,70,65,50,35,26,25,14,13,10,7,5,2].

Therefore, the number of lock points is appropriately selected from these, and in the above example, the number of lock points is set to 35 in one comparison cycle in all cases.

〔The invention's effect〕

According to the present invention, the reference signal and the comparison signal are obtained by dividing the original signal, and the division ratio is selected. Therefore, even when the write-side and read-side synchronization frequencies are different, Synchronization can be achieved, and good synchronization can be achieved when performing system conversion.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a synchronous circuit according to the present invention, FIG. 2 is a timing chart for explaining the same, and FIG.
Timing chart of run-in in SC mode, 4th
The figure shows the run-in timing chart for the PAL system.
FIG. 5 is a diagram for explaining an overtaking operation, FIG. 6 is a configuration diagram of a conventional circuit, and FIG. 7 is a timing chart for explaining the same. (1) (2) is an input terminal, (3) is a timing adjustment circuit, (4) is a gate circuit, (5) (7) (15) is a frequency divider, (6) is an inverter, and (8) (16) ) (26) (32) ~
(35), (38) and (39) are flip-flops, (9) is an edge detection circuit, (11), (36) and (37) are OR circuits, (12) is a comparator, (13) is a low-pass filter, and (14) ) Is a variable frequency oscillator, (17) is a NOR circuit, (21) and (23) are counters, (22), (24), and (31) are decoders, (25) is an AND circuit, and (27) and (28) are output terminals. It is.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/04-5/12 H04N 7/01 H04N 11/00-11/22 H04N 5/262-5/28

Claims (1)

(57) [Claims] An input video signal is written to a memory according to a synchronizing signal, and the written signal is read according to a synchronizing signal formed from a clock signal generated by a variable frequency oscillator to form an output video signal. A reference pulse once (n is a positive integer) obtained every n frames obtained by dividing the horizontal synchronizing signal of the input video signal at a first dividing ratio, and a second dividing ratio Phase comparison with a comparison signal formed only in a period of 1 / m (m is a positive integer) of the reference pulse obtained by frequency division and in a period of the vertical synchronization signal of the input video signal. The comparison output is fed back to the variable frequency oscillator to form a PLL, and the first and second frequency division ratios are set to a common value between the synchronization frequency of the input video signal and the output video signal and the frequency of the clock signal, respectively. Based on number Synchronous circuit being characterized in that so as to select and have.