JPH06291652A - Pll circuit and liquid crystal display device using the circuit - Google Patents

Abstract

PURPOSE:To provide the liquid crystal display device in a multiscanning system provided with a write/read separate type PLL circuit by outputting the same oscillation frequency at all times even when input image signals different in horizontal synchronizing frequencies are inputted. CONSTITUTION:A synchronizing frequency detector 1 performs digital frequency conversion to the cycle of a horizontal synchronizing pulse fH and sends the result to a divider 6. At the divider 6, and fout is simultaneously inputted from a frequency setter 7 to set the oscillation output frequency fout and a frequency dividing ratio N of a programmable frequency divider 5 is automatically calculated by operating foutdivided by fH=N. The arithmetic result is inputted to the frequency divider 5 and an oscillated output from a VCO 4 is frequency-divided by N and inputted to a phase comparator 2 as a pulse (a) to be compared. It is converted from phase difference to voltage by the comparator 2 and the converted result is fed back to the VCO 4 through an LPF 3 as a control voltage. A series of these feedback operation is repeated, and the output fout is phase-locked at a horizontal synchronizing pulse fH and outputted from the VCO 4 as a stable output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called PLL circuit for a liquid crystal display device capable of coping with a plurality of types of synchronizing signal inputs having different scanning line scan rates of image signals (hereinafter abbreviated as multi-scanning system) and a PLL circuit for the same. The present invention relates to a mounted liquid crystal display device.

[0002]

2. Description of the Related Art A conventional PLL circuit has a practical circuit
It can be said that the configuration used in 116436, that is, the configuration shown in the block diagram of FIG. 4 is general.

It divides the reference signal generated from the reference crystal oscillation circuit 101 by a programmable frequency divider 105 which sets a frequency division ratio in order to extract the oscillation output of the VCO 104 as a desired frequency with which the phase is locked,
The frequency-divided output is input to the phase comparator 102 as a signal to be compared, and the phase is compared with the reference signal output of the reference crystal oscillation circuit 101. This result (phase difference) is converted into a voltage V
It is fed back to the VCO 104 as a control voltage of the CO through the low pass filter 103.

As a result, the oscillation output of the VCO 104 controlled by the feedback voltage is returned to the phase comparator 102 again via the programmable frequency divider 105, and the oscillation output of the VCO 104 is the reference signal output of the reference crystal oscillator. Therefore, a phase lock loop that outputs a stable desired frequency without the phase difference between and is established.

This conventional system is suitable for use as an oscillator having a constant channel bandwidth in a predetermined frequency band, as represented by channel control of radio transmitters and receivers. .

[0006]

However, the above-mentioned PLL is used.
In the circuit, in the multi-scanning type liquid crystal display device, the reference signal conventionally used by the reference crystal oscillating circuit has to be the horizontal synchronizing signal of the input image. There are a wide variety of signal formats that range from 1 to several hundred KHz, and it is almost impossible to support all of them.

Further, in order to cope with a wide variety of input signals by the liquid crystal display device having the same display capacity of the liquid crystal display device, in particular, the same number of pixels, even if the input reference frequency (horizontal synchronization period) changes. A PLL circuit that generates a non-reading frequency is indispensable, but the prior art could not satisfy this.

The present invention solves such a problem. Even when input image signals having different horizontal synchronizing frequencies are input, the same oscillation frequency corresponding to the number of pixels of the liquid crystal display device is always output. It is an object of the present invention to realize a PLL circuit to be realized and a write / read separated dual system PLL circuit that can be used in a multi-scanning type liquid crystal display device.

[0009]

In order to solve the above problems, a PLL circuit of the present invention comprises a sync frequency detector for detecting horizontal sync frequencies of input image signals having different horizontal sync frequencies, a phase comparator, Low-pass filter, VCO,
A frequency setting device for setting the oscillation output frequency of the VCO,
A divider for dividing the output of the frequency setting device by the detection output of the synchronous frequency detector, and the V output according to the output of the divider.
A circuit provided with a programmable frequency divider capable of setting a frequency division ratio of a CO oscillation output, wherein the same oscillation frequency is always output even when input image signals having different horizontal synchronizing frequencies are input. And

The liquid crystal display device of the present invention further comprises a sync frequency detector for detecting the horizontal sync frequency of the input image signal,
Phase comparator, low-pass filter, VCO, and VC
A PLL circuit having a programmable frequency divider capable of arbitrarily setting the oscillation output of O by the output of the synchronous frequency detector in correspondence with the picture element output period of the input image signal source is used for controlling the image capturing timing. In addition, even if the input image signals having different horizontal synchronizing frequencies described above are input, a PLL circuit that outputs the same oscillation frequency at all times can be used for display output timing control of a liquid crystal display device. It is characterized by mounting two PLL circuits with different frequencies.

[0011]

Embodiments Embodiment 1 of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a PLL circuit of the present invention, which is an embodiment for realizing claim 1.

First, the horizontal synchronizing pulse fH of the input image signal which is the lock reference signal of the PLL circuit is applied to the synchronizing frequency detector 1 and the phase comparator 2, and the synchronizing frequency detector 1
Converts the period of the horizontal synchronizing pulse fH into a digital frequency and sends it to the divider 6.

Further, the divider 6 has a PL serving as a numerator of the operation.
The frequency setting device for setting the oscillation output frequency fOUT of L simultaneously inputs fOUT and performs a division of fOUT / fH = N to automatically calculate the division ratio N of the programmable frequency divider 5.

The result of this operation is the programmable frequency divider 5
Is input to the phase comparator 2 and the oscillation output from the VCO 4 is input to the phase comparator 2 as the compared pulse a.

The phase comparator 2 to which fH and the pulse to be compared a are given is subjected to phase difference → voltage conversion by the phase discrimination circuit and the charge pump which are components of the phase comparator, and V
V as a control voltage of CO4 via the low-pass filter 3
It is fed back to CO4.

By repeating a series of feedback operations as described above, fOUT is output from the VCO 4 as a phase locked and stable output to fH.

In this description, the horizontal synchronizing pulse input as fH is approximately ten and several K in various current image signal sources.
Although existing in the range of Hz to hundreds of tens of KHz, the series of configurations including the synchronous frequency detector 1, the divider 6 and the frequency setter 7 is sufficiently compatible with the display device of the multi-scanning method which is the object of the present invention. It has the ability to automatically and instantaneously determine the division ratio N of the programmable frequency divider.

As a result, even if fH changes over a wide range (the input image source changes), a constant reference clock corresponding to the number of pixels, which is a constraint condition in the case of a liquid crystal display device, is displayed. You can always get it.

(Embodiment 2) FIG. 2 is a block diagram showing a schematic configuration of a circuit of a liquid crystal display device according to an embodiment realizing claim 2 of the present invention.

First, the input image signal Vin is input to the sync separation circuit 1
0 and input to the A / D converter 13. Next, as shown in the figure, the horizontal synchronizing signal fH and the vertical synchronizing signal fV separated by the sync separation circuit 10 are fH to PLL (A) 11 and PLL (B) 18, and fV is a write control circuit / read control circuit. It is input to the liquid crystal display device control circuit (hereinafter abbreviated as LCD control circuit).

At this time, the PLL (A) 11 has the configuration shown in FIG. 3, and the fH input to the phase comparator 201 is
In contrast, the output fOUTa of the VCO 203 is the write control circuit 1
2 and a programmable frequency divider 204 provided to obtain a frequency required by the A / D converter 13 and a closed loop of the PLL determined by the frequency division ratio input Nin.

The other processes including the low-pass filter 202 to obtain the phase-locked fOUTa with respect to fH are basically the same as those described in the first embodiment, so the description thereof is omitted here, but the writing to the frame memory 14 is omitted. That is, all the timings for the above are determined by this PLL (A) 11.

The one PLL (B) 18 is the PLL circuit having the structure of claim 1 described in detail in the first embodiment. Therefore, the detailed operation description is omitted,
The effect is that the image input signal V for multi-scanning is
Even if the horizontal sync signal fH of in changes, the reading control of the frame memory 14 and the L corresponding to the number of display pixels of the LCD 16 are performed.
A constant control clock is supplied to the read control circuit 19 and the LCD control circuit 17 to enable CD control.

The frame memory 14 includes a write control circuit 12, a read control circuit 19 and an A / D converter 1.
3 is provided for temporarily storing and generating image-processed video data input via the D / A converter 15 as a display signal of the LCD 16 by a control signal and a video signal input from each of the three.

With the configuration described above, two independent P
In the present embodiment, it is possible to independently control various image capture timings for LCD control and read timings for display control by synchronizing with the input image signal by using LL (A) and PLL (B). Is.

[0027]

According to the PLL circuit of the present invention, even if input image signals having different horizontal synchronizing frequencies are input, the same oscillation frequency corresponding to the number of pixels of the liquid crystal display device is always output.
It is extremely effective in realizing an LL circuit and a write / read separation type PLL circuit that can be used in a multi-scanning type liquid crystal display device, and is widely used in a CRT by using an LCD having a certain limited number of display pixels. It can be said that this is an excellent means for realizing a multi-scanning type display device that is being developed.

Further, it has an excellent effect of preventing the occurrence of interfering clock noise due to the presence of the asynchronous clock, which tends to occur in the read / write separated type image processing circuit, and it is also useful for improving the image quality of the liquid crystal display device using this. is there.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of an embodiment according to claim 1 of the present invention.

FIG. 2 is a circuit block diagram showing a schematic configuration of an embodiment according to claim 2 of the present invention.

FIG. 3 is a circuit block diagram showing a configuration of an embodiment according to claim 2 of the present invention.

FIG. 4 is a circuit block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 synchronous frequency detector 2 phase comparator 3 low pass filter 4 VCO 5 programmable frequency divider 6 divider 7 frequency setter 10 sync separation circuit 11 PLL (A) 12 write control circuit 13 A / D converter 14 frame Memory 15 D / A converter 16 LCD 17 LCD control circuit 18 PLL (B) 19 Read control circuit 101 Reference crystal oscillation circuit

Claims (2)

[Claims] 1. A synchronizing frequency detector for detecting horizontal synchronizing frequencies of input image signals having different horizontal synchronizing frequencies, a phase comparator, a low-pass filter, and a voltage controlled oscillator (hereinafter referred to as V
Abbreviated as CO), a frequency setter that sets the oscillation output frequency of the VCO, a divider that divides the output of the frequency setter by the detection output of the synchronous frequency detector, and the VCO by the output of the divider. A circuit having a programmable frequency divider capable of setting a frequency division ratio of the oscillation output, characterized in that the same oscillation frequency is always output even when input image signals having different horizontal synchronizing frequencies are input. PLL circuit to do. 2. A synchronous frequency detector for detecting a horizontal synchronous frequency of an input image signal, a phase comparator, a low-pass filter, a VCO, and an oscillation output of the VCO are input by an output of the synchronous frequency detector. A PLL circuit provided with a programmable frequency divider that can be arbitrarily set corresponding to a picture element output cycle of an image signal source is used for controlling image capturing timing, and the PLL circuit according to claim 1 is used. 2. A liquid crystal display device having two PLL circuits with different output frequencies, which are configured to be used for controlling the display output timing.