JPH05252438A - Video signal sampling control circuit - Google Patents

Abstract

PURPOSE:To instantaneously switch a frequency of a sampling clock by controlling a clock switching means so that an output of a PLL circuit by which frequency division ratio data is switched is supplied to an A/D converter. CONSTITUTION:PLL circuits 6, 7 are provided with phase comparators 61, 71 and frequency dividers 64, 74, and its outputs SC1, SC2 are inputted to an input terminal of a clock changeover switch 5. As a result, the switch 5 is subjected to switching control by a control signal of a switch 4, and one sampling clock SC selected thereby is supplied to an A/D converter 1. In this case, to the switch 4, a vertical synchronizing signal extracted from a video signal is supplied, and also, from the comparators 61, 71 of the PLL circuits 6, 7, a lock signal for showing a phase locked state of each circuit 6, 7 is supplied. Also, to the frequency dividers 64, 74, an enlargement ratio setting device 10 is connected through frequency division ratio switches 8, 9, and an enlargement ratio of an image is set. In such a way, switching of a clock is executed instantaneously, and the image does not go out of order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a video processing device that performs desired video processing by changing a sampling period when performing D / D conversion.

[0002]

2. Description of the Related Art Conventionally, a video processing apparatus as shown in FIG. 2 has been used for enlarging and reducing an image displayed on an image display apparatus such as a CRT. The apparatus switches the sampling period when A / D converting an analog video signal by the A / D converter (1) according to the image enlargement ratio. Output is video processing unit (2)
After being subjected to necessary signal processing including D / A conversion at, the image is supplied to the image display unit (3) and displayed on the screen.

For example, when enlarging an image twice, A /
When the frequency of the sampling clock SC to be supplied to the D converter (1) is set to twice the standard value and the image is reduced to 1/2, the frequency of the sampling clock is set to 1 of the standard value.
/ 2 is set.

Generally, the sampling clock SC to be supplied to the A / D converter (1) is a phase comparator (61), as shown in FIG.
A well-known PLL (Phase-Locked) including a loop filter (62), a voltage controlled oscillator VCO (63), and a frequency divider (64).
Loop) circuit (60). The phase comparator (61) of the PLL circuit (60) is supplied with the horizontal synchronizing signal extracted from the video signal to be processed, and thereby a sampling clock that matches the phase of the horizontal synchronizing signal is created.

Further, the frequency divider (64) of the PLL circuit (60) is supplied with frequency division ratio data from the frequency division ratio switch (80), whereby the frequency division ratio N of the frequency divider (64) is supplied. Is defined, and a sampling clock that matches the product (f _H × N) of the frequency division ratio N and the horizontal synchronizing frequency f _H is created.

Therefore, if the value N of the division ratio is changed by the enlargement ratio setting device (10) connected to the division ratio switching device (80),
It is possible to change the frequency of the sampling clock, that is, the enlargement ratio of the image.

In order to switch the frequency of the sampling clock within the vertical blanking period of the video signal, a vertical synchronizing signal is supplied to the frequency dividing ratio switching unit (80), whereby the timing of frequency dividing ratio switching is vertically synchronized. Match the signal.

[0008]

However, in the conventional apparatus shown in FIG. 2, when the image enlargement ratio is greatly changed, the phase lock of the PLL circuit (60) is not completed within the vertical blanking period, There was a problem that the image was distorted. That is, when the frequency of the horizontal synchronizing signal pulse input to the phase comparator (61) of the PLL circuit (60) and the frequency of the output pulse of the frequency divider (64) are significantly different, the frequency and phase of both pulses are It takes a long time for the two to coincide with each other, so the output pulse (sampling clock) of VCO (63) within the vertical blanking period.
The frequency is not stable, and the frequency of the sampling clock changes during the video display period, so that part of the image corresponding to the period during which the frequency change occurs is disturbed.

An object of the present invention is to provide a sampling control circuit capable of instantaneously switching the frequency of the sampling clock to be supplied to the A / D converter.

[0010]

A sampling control circuit in a video processing apparatus according to the present invention comprises a plurality of PLL circuits (6) (7) for generating a sampling clock whose phase matches a horizontal synchronizing signal of a video signal to be processed. ) And the plurality of P
The frequency division ratio data is supplied to the LL circuits (6) and (7) respectively, and the frequency division ratio data is converted into new data for the PLL circuit which is not supplying the sampling clock to the A / D converter (1). Frequency division ratio setting means for switching setting, and clock switching means for selectively supplying the output of one PLL circuit among the plurality of PLL circuits (6) and (7) to the A / D converter (1) And detecting the phase locked state of the PLL circuit whose frequency division ratio data has been switched by the frequency division ratio setting means,
There is provided switching control means for switching the clock switching means so as to supply the output of the PLL circuit to the A / D converter (1).

[0011]

When the frequency of the sampling clock is switched, the sampling clock is supplied to the A / D converter (1) among the plurality of PLL circuits (6) and (7) by the operation of the division ratio setting means. The frequency division ratio data corresponding to the frequency of the sampling clock to be newly set is supplied to the PLL circuit that does not exist.

The PLL circuit supplied with the frequency division ratio data generates a sampling clock of a new frequency after a phase lock operation for a fixed period. In this process, the switching control means detects the completion of the phase lock of the PLL circuit, and in response to the detection, switches the clock switching means within the vertical blanking period of the video signal to output the output of the PLL circuit.
(Sampling clock) is supplied to the A / D converter (1).

At this time, since the frequency of the sampling clock is stable, it is possible to set A within the vertical blanking period of the video signal.
The switching of the sampling cycle of the / D converter (1) is completed.

[0014]

According to the video signal sampling control circuit of the present invention, when the sampling period of the A / D converter is switched to enlarge or reduce the image, for example, the image is displayed within the vertical blanking period which does not appear on the screen. Processing is complete and the image is not distorted.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is described below with reference to FIG.
An example of the reduction process will be specifically described. Note that FIG.
The same components as those of the conventional circuit shown in FIG.

The sampling control circuit includes first and second PLs.
It has L circuits (6) and (7). Both the PLL circuits (6) and (7) are the same as the conventional ones, and the phase comparators (61) (71) and the loop filter (6
2) (72), VCO (63) (73), and frequency dividers (64) (74). The outputs SC1 and SC2 of each PLL circuit (6) (7) are connected to the clock switch (5). It is connected to each input terminal.

The clock changeover switch (5) is switching-controlled by a control signal sent from the clock changeover device (4), and one sampling clock SC selected by this is supplied to the A / D converter (1). To be done.

The clock switch (4) is supplied with the vertical synchronizing signal extracted from the video signal, and the phase comparators (61) (71) of the first and second PLL circuits (6) (7) , A phase lock signal representing the phase lock state of each PLL circuit is supplied.

Further, the frequency dividers (64) (7) of both PLL circuits (6) (7)
An enlargement ratio setting device (10) is connected to 4) via frequency division ratio switching devices (8) and (9), respectively. The enlargement ratio setting device (10) is for setting the enlargement ratio of the image, whereby the enlargement ratio data Z1, Z is sent to the first and second frequency division ratio changeover devices (8) (9).
2 is supplied. The frequency division ratio changers (8) and (9) create the frequency division ratio data D1 and D2 according to the enlargement ratio data, and the frequency dividers (64) of the first and second PLL circuits (6) and (7). ) (74).

In the above sampling control circuit, for example, the clock switch (5) is switched to the first PLL circuit (6) side, and the sampling clock SC from the first PLL circuit (6) is sent to the A / D converter (1). If it is supplied and the image is displayed on the video display unit (3) at a certain magnification,
To change the horizontal enlargement ratio of the image, operate the enlargement ratio setter (10) to set a new enlargement ratio.

As a result, the enlargement ratio setting device (10) is connected to the second
New expansion rate data Z2 is supplied to the frequency division ratio switch (9), and the frequency division ratio data D2 created by the second frequency division ratio switch (9) is applied to the frequency divider of the second PLL circuit (7). It is supplied to (74) and the frequency division ratio of the frequency divider (74) is set to a value according to the new enlargement ratio.

In response to this, the second PLL circuit (7) outputs the horizontal synchronizing signal pulse extracted from the video signal and the frequency divider (74).
The sampling clock SC2 having a frequency synchronized with the frequency division ratio of the frequency divider (74) and a phase synchronized with the horizontal synchronizing signal is generated on the basis of the output pulse of, and output from the VCO (73).

In this process, when the second PLL circuit (7) is phase-locked, the phase-locked signal representing this is phase-compared.
It is sent from (71) to the clock switch (4). After detecting the phase lock of the second PLL circuit (7) based on the phase lock signal, the clock switch (4) sends a control signal to the clock switch (5) in synchronization with the vertical synchronizing signal.

According to this, the clock changeover switch (5)
Switches to the second PLL circuit (7) side, and the second PLL circuit
Sampling clock SC from (7) is A / D converter
It is supplied to (1).

After that, when the image enlargement ratio is switched again, new enlargement ratio data Z1 from the enlargement ratio setting device (10) is sent to the first frequency division ratio switching device (8), and the first division ratio is changed. Based on the division ratio data D2 created by the division ratio switch (8),
The first PLL circuit (6) will operate. Then, in the state where the first PLL circuit (6) is phase locked, the clock changeover switch (5) is changed over in synchronization with the vertical synchronizing signal, and the sampling clock of the first PLL circuit (6) is A /
It is supplied to the D converter (1).

As described above, when changing the enlargement ratio of an image, one of the two PLL circuits (6) and (7) which is not in use is used.
A new sampling clock generation operation is started using the L circuit, the sampling clock is switched only when the PLL circuit is phase locked, and A / D conversion is always performed with a stable sampling clock. There is no disturbance.

In the above embodiment, the enlargement / reduction of the image in the horizontal direction has been described. However, the well-known circuit configuration of the video processing unit (2) enables the enlargement / reduction process in the vertical direction to be performed at the same time. is there.

The above description of the embodiments is for explaining the present invention and should not be construed as limiting the invention described in the claims or limiting the scope. The configuration of each part of the present invention is not limited to the above embodiment, and it is needless to say that various modifications can be made within the technical scope described in the claims.

For example, the present invention provides a control circuit for switching the sampling cycle for each video signal, when not only the image enlarging / reducing process but also switching image display of plural kinds of video signals having different formats. Is also applicable.

[Brief description of drawings]

FIG. 1 is a block diagram showing a sampling control circuit according to the present invention.

FIG. 2 is a block diagram showing a conventional sampling control circuit.

[Explanation of symbols]

 (1) A / D converter (4) Clock selector (5) Clock selector switch (6) First PLL circuit (7) Second PLL circuit (8) First division ratio selector (9) Second division ratio Switching device (10) Zoom ratio setting device

[Procedure amendment]

[Submission date] October 9, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art Conventionally, as one technique for enlarging and reducing an image displayed on an image display device such as a CRT, FIG.
An image processing device as shown in is used. The device is
The sampling cycle when A / D converting an analog video signal by the A / D converter (1) is switched according to the image enlargement ratio, and the output of the A / D converter (1) is a video processing unit.
After receiving the necessary signal processing including D / A conversion in (2),
The image is displayed by being supplied to the video display unit (3).

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0027

[Correction method] Delete

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H04N 11/04 D 9187-5C (72) Inventor Akihiro Yamada 2-18, Keihanhondori, Moriguchi-shi, Osaka Address Sanyo Electric Co., Ltd.

Claims (1)

[Claims] 1. A desired video processing is performed by inputting an analog video signal into an A / D converter (1) to convert it into a digital video signal and changing a sampling cycle at the time of the A / D conversion. In a video processing device, a plurality of PLL circuits that generate a sampling clock whose phase matches the horizontal synchronizing signal of the video signal to be processed (6)
(7) and a plurality of PLL circuits (6) and (7) are supplied with frequency division ratio data, respectively, and the A / D converter (1) is not divided with respect to the PLL circuit which is not supplied with the sampling clock. A division ratio setting means for switching and setting the division ratio data to new data, and an output of one PLL circuit among the plurality of PLL circuits (6) and (7) is selectively A / D converter ( 1) detecting the phase lock state of the clock switching means to be supplied to the PLL circuit and the PLL circuit whose frequency division ratio data is switched by the frequency division ratio setting means,
A video signal sampling control circuit comprising switching control means for switching the clock switching means so as to supply the output of the circuit to the A / D converter (1).