KR100907100B1 - Dot clock signal generator for video horizontal synchronous signal - Google Patents

Abstract

The present invention relates to a dot clock signal generator for an image horizontal synchronization signal, and more particularly, to a dot clock signal generator for generating a dot clock signal based on a horizontal synchronization signal, which is implemented as one integrated circuit. The horizontal synchronizing signal is input to the reset stage, and N times the clock signal of the dot clock signal supplied from the system is input to the clock stage and reset when the horizontal synchronizing signal is low, and the horizontal synchronizing signal is high. Is a clock division circuit for dividing the N times clock signal by N times and outputting a dock clock signal, wherein the clock division circuit includes a clock division having a rising edge first among the N times clock signals during an initial operation. A dot clock signal having a rising edge is generated.

Therefore, according to the present invention configured as described above, it is possible to generate a dot clock signal by simply using a clock divider circuit, which is a single device, so that the volume of the circuit can be relatively reduced, and the circuit configuration can be simplified. Pure digital circuitry can be implemented.

Video horizontal sync signal, dot clock signal, clock division circuit, N times, division

Description

DOT CLOCK SIGNAL GENERATOR FOR VIDEO HORIZONTAL SYNCHRONOUS SIGNAL}

1 is a block diagram schematically showing the configuration of a PLL circuit which is a conventional dot clock signal generator;

2 is a block diagram schematically showing the configuration of a dot clock signal generator for an image horizontal synchronizing signal according to the present invention;

3 is a timing diagram illustrating the timing of FIG. 2.

<Description of the symbols for the main parts of the drawings>

10: PLL circuit 11: phase detector

12 loop filter 13 voltage controlled oscillator

14: scaler 100: clock division circuit

CLK: Clock stage RESET: Reset stage

OUT: Output terminal

The present invention relates to a dot clock signal generator, and more particularly, to a dot clock signal generator for an image horizontal synchronizing signal capable of generating a dot clock signal for an image horizontal synchronizing signal.

In general, in order to transmit a video signal from a TV camera to a TV and accurately restore the original video, it is necessary to process timing, that is, synchronization processing at the transmitting side and the receiving side.

The sync signal of the video signal includes a horizontal sync signal H sync and a vertical sync signal V sync. There is also a color burst as a color synchronization signal.

Video signals that can be represented in two dimensions need to arrange each pixel vertically and horizontally. For this reason, the vertical and horizontal synchronization signals are required for the video signal. The sync signal includes each sync of H and V. Usually, the two are combined and transmitted as a composite sync signal, and are separated horizontally and vertically at a receiving side such as a monitor.

Color information is loaded on the horizontal scanning line on the basis of the horizontal synchronization signal, which is loaded on the horizontal scanning line signal in accordance with the dot clock signal. That is, the dot clock signal is a signal that determines the horizontal resolution of the video signal.

Meanwhile, a PLL circuit as shown in FIG. 1 is used to generate such a dot clock signal.

Referring to FIG. 1, the PLL circuit 10 compares a phase difference between an input image horizontal synchronization signal and an externally input clock signal to output a signal corresponding to a phase difference, and a phase detector 11. A loop filter 12 for rectifying a signal outputted from the loop output signal 12 and outputting a signal having a DC characteristic, and a voltage controlled oscillator 13 operated according to the signal of the DC characteristic output from the loop filter 12 to output a clock signal. And a scaler 14 which divides or multiplies the clock signal output from the voltage controlled oscillator 13 and outputs a necessary synchronous clock signal, that is, a dot clock signal.

However, when the dot clock signal is generated using such a conventional PLL circuit, the volume of the PLL circuit is large and the size of the entire circuit is increased, the PLL circuit is made up of many components, and the circuit is complicated because analog devices are used. There is a problem that it is impossible to implement a digital circuit.

Therefore, an object of the present invention is to solve the above problems, it is possible to generate a dot clock signal by simply using a clock divider circuit which is an integrated circuit (relatively) to reduce the volume of the circuit relatively It is possible to simplify the circuit configuration, and to enable the implementation of pure digital circuits.

Features of the present invention for achieving the above object,

A dot clock signal generator for generating a dot clock signal by a horizontal synchronization signal,

The dot clock signal generator includes a clock divider circuit implemented as one integrated circuit, and the clock divider circuit is configured to supply the horizontal sync signal to a reset stage and to supply the dot clock signal from a system. A clock divider circuit which is inputted with a clock signal of N times and resets when the horizontal synchronization signal is low, and divides the N times clock signal by N times and outputs a dock clock signal when the horizontal synchronization signal is high. Characterized in that it comprises a.

Here, the clock divider circuit,

In the first operation, a dot clock signal having a rising edge is generated from a clock having a rising edge first of the N times the clock signal.

Hereinafter, the configuration of the dot clock signal generator for the image horizontal synchronization signal according to the present invention will be described in detail with reference to FIG.

2 is a block diagram schematically illustrating a configuration of a dot clock signal generator for an image horizontal synchronization signal according to the present invention.

Referring to FIG. 2, a dot clock signal generator for an image horizontal synchronization signal according to the present invention includes a clock division circuit implemented as one integrated circuit, and the clock division circuit 100 includes a horizontal synchronization signal. Is a clock division circuit 100 in which a clock signal, which is N times the dot clock signal supplied from the system, is input to the clock terminal CLK.

Hereinafter, the operation of the dot clock signal generator for the image horizontal synchronization signal according to the present invention will be described in detail with reference to FIG.

3 is a timing diagram illustrating the timing of FIG. 2.

First, the clock divider circuit 100 is reset when the horizontal synchronizing signal is low, and outputs the dock clock signal by dividing the N times the clock signal by N times when the horizontal synchronizing signal is high in this state. As described above, the first operation of the N times the clock signal generates the dot clock signal having the rising edge from the clock having the rising edge.                     

On the other hand, whenever a horizontal sync signal occurs from low to high every time the horizontal sync signal occurs, the position of the N times dot clock signal may change little by little. This is because the sources are different and not synchronized with each other. However, since the time interval between the rising edge of the horizontal synchronization signal and the rising edge of the N times dot clock signal varies from a minimum of 0 to a maximum of 1 / N times the clock frequency, this time is the maximum error between the image horizontal synchronization signal and the dock clock signal every time. do. Thus, to reduce this error, setting the N times clock frequency very high can reduce the maximum error to ensure high synchronous stability.

As described above, according to the dot clock signal generator for the image horizontal synchronizing signal according to the present invention, the dot clock signal can be generated by simply using a clock divider circuit implemented as one integrated circuit. By doing so, the volume of the circuit can be relatively reduced, the circuit configuration can be simplified, and a pure digital circuit can be realized.

Claims (2)

A dot clock signal generator for generating a dot clock signal by a horizontal synchronization signal, The horizontal synchronization signal is implemented as one integrated circuit, and the horizontal synchronization signal is input to the reset stage, and N times the clock signal of the dot clock signal supplied from the system is input to the clock terminal and the horizontal synchronization signal is low. A clock divider circuit which is reset when the horizontal synchronization signal is high and divides the N times clock signal by N times and outputs a dock clock signal; The clock divider circuit, And a dot clock signal having a rising edge from a clock having a rising edge first of the N times the clock signal during the first operation. delete

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