JPH0382291A - Phase synchornizing device - Google Patents

Abstract

PURPOSE:To improve tracking to a phase change by detecting directly a phase difference between a color burst and a clock pulse in a PCM video signal and restoring the phase depending on the phase difference. CONSTITUTION:The phase synchronizing device is provided with a flag generating circuit 56, a phase comparison section 76 and a delay quantity control section 81. Then a phase difference between a color burst and a clock pulse in a PCM(Pulse Code Modulation) video signal is directly detected without using a loop filter to restore the phase depending on the phase difference. Thus, momentary reply is attained even to a sudden change in the phase and a cause to a temperature change or drift is compensated and a stable phase synchronization device is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronization device for obtaining a clock signal of an integer multiple of subcarriers synchronized with a color burst of a quantized video signal.

[Conventional technology]

For example, NTS C (National Telev
A color burst is added to a video signal of a color image based on the 2008-2008 System Committee system as phase information of subcarriers necessary for synchronously detecting color information on the receiving side. Such video signals are converted into PCM (Pulse Code Module).
ation) When transmitting the modulated signal, it is necessary to perform quantization based on the signal synchronized with the burst flag. This is because if it is not synchronized with the color burst, the phase of the color burst demodulated on the receiver side will shift, making it impossible to reproduce accurate colors. Conventionally, a clock pulse synchronized with the color burst of a video signal is created using a PLL circuit (phase-locked loop circuit), and quantization is performed based on this pulse.

FIG. 2 shows a circuit configuration of a PLL device that quantizes a video signal based on a signal synchronized with such a color burst signal.

The PLL device includes a buffer amplifier 14 that converts an analog video signal 12 supplied from an input terminal 11 into a low impedance video signal 13. The video signal 13 output from the buffer amplifier 14 is sent to the sync separation circuit 16
, bandpass filter 17 and A/D converter 18
is being supplied to.

The synchronization separation circuit 16 separates the synchronization signal 19 from the video signal 13.
is separated and supplied to the pulse generation circuit 21. The pulse generation circuit 21 outputs a burst flag 22 after a certain period of time has passed since the synchronization signal 19 is supplied, and supplies this to the gate circuit 23 .

The burst flag 22 is output at approximately the center where the phase of the color burst of the video signal 13 is stable.

Bandpass filter 17 extracts a chroma signal 26 consisting of a color burst from video signal 13 and supplies it to comparator 27 . Comparator 27 + 10ma signal 26
is pulsed and the chroma pulse signal 28 is sent to the gate circuit 23.
supply to. The gate circuit 23 uses the burst flag 22 supplied from the pulse generation circuit 21 to extract one arbitrary cycle of the chroma pulse signal 28 located approximately at the center of the color burst. The gate circuit 23 uses the extracted pulse signal as a start pulse 29 and outputs it to the PLL circuit 30.
The signal is supplied to the phase comparator circuit 31 of.

The phase comparator 31 compares the phases of the rising edge of the start pulse 29 and the rising edge of the reproduced subcarrier 32 and outputs an error signal 34 between them. Error signal 34 is supplied to oscillator 37 through loop filter 36. The oscillator 37 outputs a clock pulse 38 having a frequency (Nfsc) that is an integer value N times the subcarrier. The clock pulse 38 is supplied to a counter circuit 41,
Here, after the frequency is divided into l/N, the reproduction subcarrier 32
The signal is fed back to the phase comparator 31 as a signal.

The clock pulse 38 output from the PLL circuit 30 is
The signal is supplied to the output terminal 39, the latch circuit 41, and the A/D converter 18. The A/D converter 18 receives the low impedance video signal 1 by the clock pulse 38.
3 is sampled and quantized, and the output is sent to the latch circuit 41.
latched by the clock pulse 38 to obtain the PCM video signal 42. The PCM video signal 41 is output from an output terminal 43.

In this way, the clock pulse signal 38 output from the PLL circuit is phase-locked with the color burst extracted from the video signal 13, so it is also synchronized with the color burst in the PCM video signal 41 obtained by quantizing the video signal 13. are doing.

[Problem to be solved by the invention]

In such a conventional PLL device, the clock pulse 38 for quantizing the video signal is created by the PLL circuit 30, and the time until phase synchronization depends on the loop characteristics, so the ability to follow sudden changes in phase is poor. There was a limit.

Another disadvantage is that the quantized PCM video signal 42 is not necessarily synchronized with the color burst. That is, the bandpass filter 17 generally drifts. Further, the reference voltage of the comparator 27 varies depending on the offset voltage and temperature drift of the bias current. As a result of these factors, the phase of the start pulse 29, which is the reference signal for the PLL circuit 30, changes, resulting in a non-synchronization with the color burst.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a phase synchronization device that performs quantization in synchronization with color bursts and has good followability for phase changes.

[Means to solve the problem]

The phase synchronization device of the present invention includes (i) pulse generation means for generating a clock pulse, (ii) phase delay means for delaying the phase of the lock pulse, and (iii) an analog video signal from the phase delay means. (iv) a subcarrier creation child actor that creates subcarriers from the clock pulses output from the phase delay means; (V) the subcarriers and the modulation means; (vi) flag generation means for obtaining a burst flag indicating the position of the color burst from the analog video signal; and delay amount control means for receiving the burst flag generated by the means and controlling the phase delayed by the phase delay means in accordance with the phase difference determined by the phase comparison means.

That is, the phase synchronization device of the present invention directly detects the phase difference between a color burst and a clock pulse in a PCM video signal, and performs phase pullback based on the phase difference.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows a circuit configuration of a phase synchronization device in an embodiment of the present invention.

The phase synchronizer includes a buffer amplifier 51. The buffer amplifier 51 converts the analog video signal 53 supplied from the input terminal 52 into a low impedance video signal 5.
4 and supplies it to the flag generator 56 and clamp circuit 57. The clamp circuit 57 fixes the pedestal portion of the low-impedance video signal 54 based on the burst flag 68 generated by the flag generator 56 and supplies the video signal 69 to the A/D converter 71. The A/D converter 71 quantizes the video signal 69 according to the delayed clock pulse 72 to generate a PCM video signal 73, and supplies the PCM video signal 73 to an output terminal 74 and a phase comparator 76.

The phase synchronizer includes a crystal oscillator 78 that oscillates clock pulses 77 at four times the frequency of the subcarriers. A clock pulse 77 generated by a crystal oscillator 78 is supplied to a variable length circuit 72 . The variable extension circuit 79 receives the phase control value 82 supplied from the delay control section 81.
The phase of the clock pulse 77 is delayed by an angle of 45 degrees, and the delayed clock pulse 72 is supplied to the A/D converter 71, the output terminal 83, and the counter circuit 84.

The counter circuit 84 divides the delayed clock pulse 72 into four parts.
The subcarrier 85 is frequency-divided to operate the subcarrier 85 and supplied to the variable length shift register 86. The variable length shift register 86 delays the phase of the subcarrier 85 in units of one clock based on the phase control value 82 supplied from the delay amount control circuit 81, and transfers the delayed subcarrier 87 to the output terminal 88 and the phase comparator 76. supply.

The phase comparator 67 logically calculates the phase difference θ between the color burst in the PCM video signal 73 and the delayed subcarrier 87 and supplies it to the delay amount controller 81 . Delay amount control section 8
1 determines the phase control value 82 from the supplied phase difference θ. The delay amount control section 81 outputs the phase control value 82 to the latch circuit 8.
9 and when the burst flag 68 is supplied from the flag generating section 56, it is supplied to the variable length shift register 86 and the variable extension circuit 79.

Next, the operation of the phase synchronization device configured as described above will be explained.

An analog video signal 53 supplied from an input terminal 52 of the phase synchronizer is converted into a low impedance video signal 54 by a buffer amplifier 51. Buffer amplifier 5
A video signal 54 output from the circuit 1 is supplied to a clamp circuit 57 and a flag generating section 56.

A synchronization separation circuit 91 of the flag generation section 56 separates a synchronization signal 92 from the supplied video signal 54 and supplies it to a burst flag generation circuit 93.

The burst flag generation circuit 93 generates a burst flag 68 indicating the position of the color burst after a predetermined time has elapsed since the synchronization signal 92 is supplied, and supplies it to the clamp circuit 57 . Clamp circuit 57 fixes the pedestal portion of low impedance video signal 54 based on burst flag 68 and supplies the video signal 69 to A/D converter 71 .

A/D converter 71 quantizes video signal 69 according to delayed clock pulse 72 and converts it into PCM video signal 7
3 is outputted from the output terminal and also supplied to the phase comparator 76.

The phase comparator 76 logically compares the phases of the color burst in the PCM video signal 73 and the modulated subcarrier 87 to determine the phase difference θ between them. That is, the four-phase expansion circuit 94 of the phase comparator 76 sets the pedestal potential to 81
When the peak value of the color burst is Am and the sampling phase shift is θ, a signal whose phase is shifted by 90 degrees as shown by the following four equations (1) to (4>) is created.

B+Am5inθ −・−・(1) B+Am5inθ ・・・・・・(2) B−Amsin
θ-...-(3) B-Amcosθ...(4) These equations (1> and (2) are sent to the first subtraction circuit 95, and the equations (3) and (4) are > is supplied to the second subtraction circuit 96.The subtraction value 97 of the first subtraction circuit 95 is 2AS1nθ, and the second subtraction value 98 is 2ACO8θ.These subtraction values 97.
98 is supplied to a phase calculation ROM 99. Phase calculation RO
The M99 has an arctangent table burned in in advance. Therefore, the phase calculation ROM 99 has a subtraction value of 9.
7.98, the phase difference θ between the color burst in the PCM video signal 73 and the modulation subcarrier 87 is output. The phase difference θ obtained by the phase comparison section 76 is supplied to the delay amount control section 81.

The addition circuit 100 of the delay amount control section 81 calculates the sum of the supplied phase difference θ and the phase difference 101 of one line before, and supplies the sum 102 to the remainder calculation circuit 103. The remainder calculation circuit 103 divides the supplied addition value 102 by the cycle of one color burst cycle and supplies the remainder value 104 to the latch circuit 89 . The latch circuit 89 has a remainder value of 104
is held, and the burst flag 6 is sent from the flag generating section 56.
8 is supplied, it is supplied as a phase control value 82 to the variable extension circuit 79 and the variable length shift register 86.

By supplying the phase control value 82, the variable extension circuit 79 delays the phase of the clock pulse 77 by a time of one clock or less, and the variable length shift register 86 delays the phase of the subcarrier 85 in units of one clock. This performs a phase pullback, and the color burst in the PCM video signal 73 is brought into phase synchronization with the delayed subcarrier 87.

In the embodiment described above, since the phase difference between the color burst of the PCM video signal and the delayed subcarrier is determined by logical processing, the circuit can be easily integrated into an IC, and the device can therefore be miniaturized. It is possible.

〔Effect of the invention〕

As described above, according to the present invention, the phase difference between the color burst and the clock pulse in the PCM video signal is directly detected without using a loop filter, and the phase is pulled back based on the phase difference. You can also respond instantly. Furthermore, since the configuration is capable of compensating for factors such as temperature changes and drift, a stable phase synchronization device can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a phase synchronization device according to an embodiment of the present invention, and FIG. 2 is a circuit configuration diagram of a conventional PLL device that quantizes a video signal based on a signal synchronized with a color burst signal. . 56...Flag generation circuit, 71...A/D converter, 76...Phase comparator, 78...Crystal oscillator, 79... - Variable extension circuit, 81...Delay amount control unit, 84...Counter circuit, 86...Variable length shift register.

Claims (1)

[Claims] Pulse generation means for generating clock pulses, phase delay means for delaying the phase of the clock pulses, and quantizing analog video signals according to the clock pulses output from the phase delay means to generate PCM video signals. a modulating means for generating a subcarrier from a clock pulse output from the phase delay means; and a subcarrier generating means for generating a subcarrier from a clock pulse outputted from the phase delaying means; a phase comparison means for obtaining a burst flag indicating the position of a color burst from the analog video signal; and a flag generation means for obtaining a burst flag indicating the position of a color burst from the analog video signal; A phase synchronization device comprising: delay amount control means for controlling the phase delayed by the phase delay means according to the phase delay means.