JPS63108875A - Video signal synchronizing device - Google Patents

Abstract

PURPOSE:To eliminate a synchronizing deviation or a hunting by fixing a PLL by making the output of a phase comparator '0' during a period corresponding to the vertical synchronizing signal of an external synchronizing signal and maintaining the output frequency of a frequency divider to a value immediately before. CONSTITUTION:An external composite synchronizing signal SYNC extracted in a synchronizing separating circuit 10 is applied to a switching pulse generator 11 and a change over switch SW is switched from a contact (b) to a contact (a) during the period corresponding to the vertical synchronizing signal. Consequently, since an external synchronizing signal is commonly supplied to both the input ends of the phase comparator 2, the output of the comparator 2 goes to '0' and the output of a low pass filter 3 also goes to '0'. Therefore, the oscillating frequency of a voltage control oscillator 4 is fixed to the value immediately before a time t1 and an internal horizontal synchronizing signal HS is successively outputted under a previous state even during the vertical synchronizing period.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a video signal synchronization device suitable for use in creating an internal synchronization signal synchronized with an external synchronization signal in a superimposer, digitizer, or the like.

"Prior Art" FIG. 4 is a block diagram showing the configuration of a conventional synchronization signal generation circuit used in a superimposer or the like. In the figure, 1 is a synchronization separation circuit which separates and outputs horizontal synchronization signals H, 5YNC and vertical synchronization signals V, 5YNC from an external video signal supplied to an input terminal. The horizontal synchronization output H, 5YNC is supplied to the two input terminals of the phase comparator 2, and the output signal of the phase comparator 2 is smoothed by the low-pass filter 3 and then supplied to the control input terminal of the voltage controlled oscillator 4. . The output signal of the voltage controlled oscillator 4 is a clock signal 6
The signal CK is supplied to the synchronization signal generator 5 as the signal CK. The synchronization signal generator 5 divides the clock signal CK to generate an internal horizontal synchronization signal HS. This internal horizontal synchronization signal HS is supplied to the other input terminal of the phase comparator circuit 2, and is also supplied to the other input terminal of the internal circuit. It is supplied to a predetermined portion. A PLL (phase locked loop) is configured by the above-mentioned horizontal synchronization signal generator of the phase comparator circuit 2, low-pass filter 3, voltage-controlled oscillator 4, and synchronization signal generator 5. is the external horizontal synchronization signal H,5
It is designed to synchronize accurately with YNC.

Further, the synchronization separation circuit 1 creates a frame reset signal from the vertical synchronization signal in the video signal, and supplies this to the synchronization signal generator 5. In this case, the synchronization separation circuit l creates a frame reset signal at the timing of the vertical synchronization signal of an even field when the external video signal is based on an interlaced system, and creates a frame reset signal at the timing of the vertical synchronizing signal of each field when the external video signal is based on a non-interlaced system. A frame reset signal is created at the timing of the synchronization signal.

The synchronization signal generator 5 outputs the horizontal synchronization signal 1-IS created by the PLL as an internal horizontal synchronization signal, and also creates and outputs an internal vertical synchronization signal VS based on the frame reset signal.

"Problems to be Solved by the Invention" By the way, the synchronization signal included in the external video signal has a fifth
There is a standard type (2:I interlace) as shown in Figure (A), and a modified type as shown in Figure (B). Examples of modified types include those that do not include a horizontal synchronizing signal during the vertical synchronizing signal period, those that do not include an equalization pulse, or those that do not include both as shown in Figure 5 (b). and so on.

In this case, in the conventional synchronization signal generation circuit, if the synchronization signal in the video signal is a modified type of synchronization signal, horizontal synchronization cannot be extracted during the vertical retrace period, and as a result, the internal horizontal synchronization signal cannot be extracted. The PLL to be created may become unstable, resulting in out-of-synchronization or disturbances.

The present invention was made in view of the above-mentioned circumstances, and provides a video signal synchronization method that does not cause synchronization deviations or disturbances even when an external video signal with a synchronization signal different from the standard pattern is supplied. is intended to provide.

"Means for Solving the Problems" In order to solve the above problems, the present invention provides a phase comparator to which a horizontal synchronizing signal among external signals is supplied to one input terminal, and an output of this phase comparator. A low-pass filter smoothes the signal, a voltage-controlled oscillator to which the output of this low-pass filter is supplied as a control voltage, and when the output signal of this voltage-controlled oscillator is frequency-divided, the frequency-divided output is transmitted to the other phase comparator. A phase-locked loop consisting of a frequency divider supplied to the input terminal and a period corresponding to the vertical synchronization signal of the external signal, and during this detection period, the frequency divider is supplied to the other input terminal of the phase comparator. The frequency divider is characterized in that it is provided with a shift switching means for supplying the external horizontal synchronizing signal in place of the output signal of the frequency divider, and extracting the internal horizontal synchronizing signal from the output terminal of the frequency divider.

"Operation" During the period corresponding to the vertical synchronization period of the external synchronization signal, the external horizontal synchronization signal is commonly supplied to both input terminals of the phase comparator, and as a result, the output of the phase comparator becomes 0 and the phase A locked loop is fixed and the output frequency of the frequency divider maintains its previous value.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure, the same reference numerals are given to the parts corresponding to those in FIG. 4, and the explanation thereof will be omitted.

In the figure, IO is a synchronization separation circuit, which extracts a horizontal synchronization signal and a composite synchronization signal from an external video signal. External horizontal synchronization signal HSYN extracted by this synchronization separation circuit IO
C is supplied to one input terminal of the phase comparator 2, and the external composite synchronization signal 5YNC is supplied to the switching pulse generation circuit 11. Further, the synchronization separation circuit 10 creates a frame reset signal in an open frame with the synchronization separation circuit l shown in FIG. 4, and supplies this signal to the synchronization signal generator 12.

The synchronization signal generator 12 has a frequency divider that frequency-divides the output pulse of the voltage-controlled oscillator 4, and uses the output of this frequency divider as an internal horizontal synchronization signal H8 to the switching terminals of the switching element SW. Output to internal circuit not shown. Furthermore, the synchronization signal generator 12 creates an internal vertical synchronization signal VS based on the output pulse of the frequency divider and the frame reset signal supplied from the synchronization separation circuit IO.

The switching pulse generation circuit 11 detects a vertical synchronization signal from the external composite synchronization signal 5YNC supplied from the synchronization separation circuit IO, and during the detection period of this vertical synchronization signal, the control signal Sc supplied to the switching element SW is The switching element SW has a switching terminal a supplied with an external horizontal synchronizing signal [ISYNC, and a common terminal C connected to the other input terminal of the phase comparator 2. This switching element SW is connected to
When the control signal Sc is an "l" signal, it is switched to the terminal a side, and when the control signal Sc is "0", it is switched to the terminal a side.

Next, the operation of this embodiment with the above configuration will be explained.

Now, the external composite synchronization signal 5Y extracted by the synchronization separation circuit 10
Assume that the NC has the waveform shown in FIG. 2(a). This waveform is a non-standard type synchronization signal that does not have an equivalent pulse and does not include a horizontal synchronization signal in the vertical synchronization signal period.

First, until the time tl when the vertical synchronization signal is output, the output signal Sc of the switching pulse generation circuit 11 is "0", so the switching element SW selects the terminal side, and as a result, the synchronization signal is generated. Internal synchronization signal H output by device I2
S is supplied to the other input terminal of the phase comparator 2 via the switching element SW. As a result, a phase-locked loop is configured by the phase comparator 2, the low-pass filter 3, the voltage-controlled oscillator 4, and the frequency divider in the synchronization signal generator 12, and the internal horizontal synchronization signal HS is converted into the external horizontal synchronization signal H.
It becomes a synchronization signal equal to S Y N C.

Next, at time 1+, the vertical synchronization signal is output.
The control signal Sc output by the switching pulse generator 11 is “l”
The switching element SW selects the terminal a side. As a result, the external horizontal synchronizing signal HSYNC is commonly supplied to both input ends of the phase comparator 2, and the input phase difference of the phase comparator 2 becomes zero. Therefore, the low pass filter 3
The output signal of becomes O, and the oscillation frequency of the voltage controlled oscillator 4 changes to the time 1. Fixed to the previous value. As a result, the internal horizontal synchronization signal H9 continues to be output in the previous state during the vertical synchronization period.

Then, at the end time of the vertical synchronization signal, the switching pulse generator +1 sets the signal Sc to a "0" signal, and the switching element SW again selects the terminal side.

As a result, from time t onward, the internal horizontal synchronizing signal 1-IS that matches the external synchronizing signal HSYNC is generated by the idle locked loop.

Note that if an equivalent pulse is created in the synchronization signal generator 12 and added to the internal synchronization signal, the internal composite synchronization signal is supplied to the switching pulse generation circuit 11, and this switching pulse generation The control signal Sc may be configured to be the "l" signal while the circuit 11 is detecting the equivalent pulse (time t in FIG. 2 (c)).
0~t.

reference). Furthermore, the switching pulse generation circuit 11 may detect the vertical synchronization period (and equivalent pulse period) using both the external composite synchronization signal 5YNC and the internal composite synchronization signal 5YNC, and perform the detection operation using either one of the synchronization signals. You should try to do it.

Next, FIG. 3 is a block diagram showing a specific example of the configuration of the above embodiment.
3 and Motorola M CI-1066, M
CI 4538, N (each I using CI-1013 etc.)
C name and terminal number are shown.

In the figure, the input terminal 2o is supplied with an internal horizontal synchronizing signal (with equivalent pulses) generated by a phase-locked loop, and the time constant τ of the monostable multivibrator 21 is approximately 3/4H (H is l
(horizontal scanning period).

The external synchronization signal is supplied from the terminal 25, and the synchronization signal is extracted by the synchronization separation circuits 26 and 27. The external synchronization signal extracted by the synchronization separation circuit 26 is supplied to one input terminal of a phase comparator 28. Further, the external synchronization signal extracted by the synchronization separation circuit 27 is supplied to one switching terminal of the switching element 22, and is integrated by the OR integration circuit, whereby an external vertical synchronization signal is extracted at point P1. After the external vertical synchronization signal obtained at point P+ is inverted by an inverter,
The flip 70 is supplied to the reset terminal of the knob 23. The switching element 22 is controlled on/off by the output signal of the flip-flop 23, and the other switching terminal is supplied with an internal synchronization signal.

According to the above configuration, since the flip-flop 23 is set in the internal horizontal synchronization signal during periods other than the vertical synchronization period, the phase comparator 28 compares the internal synchronization signal and the external synchronization signal, and when the vertical synchronization period comes, Flip-flop 22 is reset by the output of the inverter, thereby providing an external synchronization signal to both inputs of phase comparator 28.

"Effects of the Invention" As explained above, according to the present invention, there is provided a phase comparator to which a horizontal synchronizing signal in an external signal is supplied to one input terminal, and a low-pass filter that smoothes the output signal of this phase comparator. a voltage controlled oscillator to which the output of this low-pass filter is supplied as a control voltage; and a frequency divider that divides the output signal of this voltage controlled oscillator and supplies the divided output to the other input terminal of the phase comparator. and a period corresponding to the vertical synchronization signal of the external signal, and during this detection period, the signal is applied to the other input terminal of the phase comparator instead of the output signal of the frequency divider. Since the internal horizontal synchronization signal is created based on the output signal of the frequency divider, even if the external synchronization signal is of a non-standard type, the synchronization can be easily performed. A stable internal synchronization signal can be created without causing any disturbance or deviation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
Figure 2 is a waveform diagram for explaining the operation of the same embodiment;
FIG. 4 is a block diagram showing a more specific circuit configuration of the embodiment, FIG. 4 is a block diagram showing the configuration of a conventional synchronization signal generation circuit, and FIG. 5 is a waveform diagram showing types of synchronization signals. 2... Phase comparator, 3... Low pass filter, 4... Voltage controlled oscillator, 11...
...Switching pulse generator (switching means), 12...
Synchronous signal generator (frequency divider), SW...Switching means (switching means).

Claims (1)

[Claims] A phase comparator to which a horizontal synchronizing signal among external signals is supplied to one input terminal, a low-pass filter that smoothes the output signal of this phase comparator, and a voltage-controlled oscillator to which the output of this low-pass filter is supplied as a control voltage. and a frequency divider that divides the output signal of the voltage controlled oscillator and supplies the divided output to the other input terminal of the phase comparator, and corresponds to the vertical synchronization signal of the external signal. switching means for detecting a period during which the frequency divider is detected, and supplying the external horizontal synchronizing signal to the other input terminal of the phase comparator in place of the output signal of the frequency divider during the detection period; A video signal synchronization device characterized in that an internal horizontal synchronization signal is created based on an output signal of a video signal synchronization device.