JPS62114330A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To cut the great variance of the output of a phase comparator for asynchronization to stabilize the output frequency of a voltage controlled oscillator by providing a synchronization/asynchronization discriminating circuit and a synchronism acquisition allowable range discriminating circuit and switching a phase comparison voltage and a fixed voltage. CONSTITUTION:A PLL of a phase synchronizing circuit is provided with a synchronization/asynchronization switching circuit 3 and a synchronism acquisition allowable range discriminating circuit 4. When an asynchronization discrimination signal is inputted from the circuit 3, the fixed voltage is selected instead of the phase comparison voltage from an LPF 5 by a switch 6 and is supplied to a voltage controlled oscillator 7, and the great variance of the output voltage of a phase comparator 2 for asynchronization is cut to stabilize the oscillation output of the oscillator 7 to a fixed frequency. If a stabilized pulse is obtained from the circuit in this state and it is discriminated that the phase variance of the input signal is small, the switch 6 selects the output of the LPF 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronization circuit for an encoding device that encodes an image signal with high efficiency.

[Conventional technology]

Generally, when converting a television signal (TV signal) into a digital signal, sampling is often performed using a clock that is phase-synchronized with the synchronization signal of the input TV signal. A conventional phase-locked circuit that creates a clock that is phase-synchronized with the synchronization signal of a TV signal is
As shown in the figure, there is a phase comparator 12 that compares the phase of the synchronizing signal of the input TV signal to the input terminal 11 with the phase of the 1/H frequency divider circuit output, and a low-pass filter that filters the phase comparator output. wave generator 13, a voltage controlled oscillator 14 whose frequency is controlled by the low-pass filter output voltage, and a voltage controlled oscillator 14 whose frequency is controlled by the output voltage of the low-pass filter.
A low-pass filter filters the output of the phase comparator 12 by comparing the phase of the input signal and the phase of the output of the 1/H frequency dividing circuit. A phase synchronization method is adopted in which the voltage controlled oscillator 14 is controlled by the output of the generator 13. In such a phase locked circuit, a clock whose phase is synchronized with the synchronizing signal of the TV signal is obtained at the output terminal 16 of the voltage controlled oscillator 14.

[Problem that the invention seeks to solve]

In the conventional phase synchronization circuit described above, when a signal such as a video tape recorder signal (VTR signal) in which the phase of the synchronization signal of the input signal has large fluctuations is input manually, the voltage controlled oscillator 1
Since the fluctuation in the output signal of the low-pass filter 13 that controls the voltage-controlled oscillator 14 is large, it exceeds the control range of the voltage-controlled oscillator 14 and phase synchronization cannot be achieved, and the oscillation frequency of the voltage-controlled oscillator 14 fluctuates and becomes unstable. For this reason, the clock of the image encoding/decoding device is not stable, so when used in the image encoding/decoding device, there is a drawback that the image is distorted.

[Means for solving problems]

The present invention includes a phase comparator that compares the phase of an input signal and a phase of a 1/H frequency divider circuit output, a low-pass filter that filters the output of the phase comparator, and an output of the low-pass filter. A phase synchronized circuit comprising a voltage controlled oscillator whose oscillation frequency is controlled by a voltage of
A synchronous/asynchronous determination circuit detects the magnitude of the phase difference with the output of the frequency dividing circuit and determines synchronous/asynchronous based on whether the phase difference is smaller or larger than a preset value; a pull-in permissible range determination circuit that detects a value and determines whether the phase is stable/unstable depending on whether it is smaller or larger than a preset value; It is equipped with a switch that switches between the input voltage and a preset constant voltage based on the output of the asynchronization determination circuit and the output of the pull-in allowable range determination circuit, and stabilizes the synchronous/asynchronous state and the phase of the input signal.
It is characterized in that the input control voltage of the voltage controlled oscillator is switched depending on an unstable state.

〔Example〕

FIG. 1 is a block diagram of one embodiment of the present invention. The phase synchronization circuit of this embodiment includes a phase comparator 2 that compares the phase of the horizontal synchronization signal of the input signal a from the input terminal l with the phase of the output of the 1/H frequency dividing circuit 8; a low-pass filter 5 that filters the output d of the low-pass filter 5; a switch 6 that switches and outputs the output voltage e of the low-pass filter 5 and a fixed (constant) voltage f;
A voltage controlled oscillator 7 whose frequency is controlled by the output voltage of this switch 6, a 1/H frequency dividing circuit 8 which divides the oscillation frequency of the output i of the voltage controlled oscillator 7 into 1/H, and a synchronous/asynchronous state. It is composed of a synchronous/asynchronous determining circuit 3 that determines whether the input phase is stable or unstable, and a pull-in permissible range determining circuit 4 that determines whether the input phase is stable or unstable.

The synchronous/asynchronous determination circuit 3 determines synchronous/asynchronous based on whether the difference between the phase of the horizontal synchronizing signal of the input signal a and the phase of the l/N frequency divider circuit output is smaller or larger than a predetermined value, and determines whether the input signal is synchronous/asynchronous. The asynchronous determination signal C is input to the switch 6. In this embodiment, when the difference is larger than a predetermined value four or more times in a row, it is determined that an asynchronous state exists and an asynchronous signal is output. This asynchronous signal causes the switch 6 to switch to supply the fixed voltage to the voltage controlled oscillator 7.

The pull-in permissible range determination circuit 4 detects the phase fluctuation of the input signal a, and determines whether the phase is stable or unstable depending on whether the magnitude of the F-th fluctuation is smaller or larger than a preset value, and determines whether the phase is stable or unstable. Pulse g is input to switch 6. In this example, if the stable state continues for 256 x 15 lines or more,
Generates a stable pulse. When a stable pulse is input to the switch 6 in the asynchronous state, the switch 6 assumes that synchronous pull-in is possible, and the switch 6 switches the fixed voltage [from the low-pass filter 5
Switch to output voltage C. 4. The switch 6 is provided with a selection circuit that selects the input voltage of the switch.

In the phase synchronized circuit having the above configuration, the switch 6
When an asynchronous signal is input from the asynchronous determination circuit 3, the switch 6 determines that the asynchronous state is present due to the asynchronous signal, and switches the input of the voltage controlled oscillator 7 from the low-pass filter output e to the fixed voltage f, thereby preventing the asynchronous state. become a state. Since the fixed voltage f is input to the voltage controlled oscillator 7, large fluctuations in the output voltage of the phase comparator 2 during non-synchronization can be cut, and even in the non-synchronized state, the frequency of the oscillation signal i of the voltage controlled oscillator 7 is constant. It becomes stable. When a stable pulse is received from the pull-in permissible range determination circuit 4 in this state, it is determined that the phase fluctuation of the input signal a is small, and the input of the voltage controlled oscillator 7 is switched from the fixed voltage to the low-pass filter output e, and the input signal Starts the phase synchronization operation with the synchronization signal of a, and enters the synchronization state. Therefore, a stable clock can be obtained at the output terminal 9 of the voltage controlled oscillator 7.

Next, the specific configurations of the synchronization/asynchronous determination circuit 3 and the pull-in allowable range determination circuit 4 in this embodiment will be explained.

FIG. 2 shows the configuration of the pull-in allowable range determination circuit 4.

This pull-in permissible range determination circuit 4 converts the input signal a into 1/25
A counter 141 that divides the frequency by 6, a counter 1142 that counts the output pulse interval of the counter +41 by the output of the 1/N frequency divider circuit 8, and a register 4 that launches the counter [I42 at the output timing of the counter I41.
4, a read-only memory U-(ROM) 45 that generates stable/unstable pulses depending on whether the output of the resistor 44 is smaller or larger than a predetermined value, and a 1/N frequency dividing circuit output (1/ 256)X (1/15) Counter l1143 divides the frequency, counts the ROM output, resets with the output of counter I[143, monitors stable/unstable pulses from ROM45 between 2'56X15 lines, 2
It is composed of a counter rV46 which determines that the stable state is stable if it continues for 56×15 lines or more and generates a stable pulse g.

FIG. 3 shows the configuration of the synchronization/asynchronous determination circuit 3.

This synchronization/asynchronous determination circuit 3 includes a differentiation circuit 3I that differentiates the input signal a, and a monostable multi-high break (hereinafter abbreviated as monomulti) I32 that stretches the output of the 1/N frequency dividing circuit 8 to a constant value. , an AND gate 33 which performs the logical operation between the signal j differentiated by the differentiating circuit 31 and the signal stretched to a constant value by the mono multi [32], and the mono multi (su, trigger type, mono multi). 34. In this synchronous/asynchronous judgment circuit,
The constant value expanded by the monomulti 32 gives a phase width that is determined to be a synchronous state, and the AND gate 33 determines that when the output j of the differentiating circuit 31 is within the phase width of the monomulti + 32, it is determined to be a synchronous state. Judge the synchronization pulse and apply it to AND gate 3
Output as the output signal of 3, mono multi
If an asynchronous state occurs consecutively more than once, a synchronization determination signal C indicating asynchronous state is output. The time width of Mono Multi 1134 is set to the length of 3 lines of TV signal, and 4
When an asynchronous state occurs more than once in a row, it is determined to be an asynchronous state.

In the above embodiment, the phase of the horizontal dome υ− of the input signal and l
Although the switching device 6 is controlled by comparing the phase of the output of the /N frequency dividing circuit, the control method is not limited to this embodiment.
A method may also be considered in which an A/D converter is provided after the phase comparator and the level value obtained by A/D converting the output of the phase comparator is compared with a previously set level value to control the switch.

In addition, in the above embodiment, the output of the synchronous/asynchronous judgment circuit that judges synchronous/asynchronous, and the pull-in permissible range judgment circuit that detects the phase fluctuation value of the input signal and judges whether it is smaller or larger than a preset value. The switch is provided with a selection circuit that selects the input voltage of the switch based on the output, but the selection circuit is not limited to this, and the selection circuit may be provided in the pull-in tolerance range determination circuit section or the synchronous/asynchronous circuit section, The signal may be output as a switching signal of a switch to switch the input control voltage of the voltage controlled oscillator.

Further, in the above embodiment, the switching device is placed between the low J/Y filter 5 and the voltage controlled oscillator 7, but the switch is not limited to this, and the switching device is placed between the phase comparator 2 and the low frequency filter 6JL filter 5. It may be placed between.

〔Effect of the invention〕

As explained above, according to the present invention, the phase comparator voltage (
By providing a switch that switches between low-pass filter output (including low-pass filter output) and fixed voltage, a synchronous/asynchronous judgment circuit and a pull-in tolerance judgment circuit that control the switch, large phase fluctuations such as VTR signals can be avoided. When a signal is used as an input signal, the synchronous/asynchronous determination circuit determines that it is in an asynchronous state, and by selecting a constant voltage as the output of the switch, it is possible to cut large fluctuations in the output voltage of the phase comparator during an asynchronous state. Also, the output frequency of the voltage controlled oscillator remains constant and stable. In addition, in the case of an asynchronous state, when the pull-in permissible range determination circuit determines that the phase fluctuation of the synchronizing signal of the input signal has become small and a stable state has been reached, the phase comparator voltage is selected by the switch and the circuit is brought into a synchronized state7. The phase synchronized circuit of the present invention can supply a stable clock to the image j, 1° encoding iU encoding device, so when used in an image encoding/decoding device, it has the effect of correctly reproducing images without disturbance. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an example of a configuration of a pull-in permissible range determination circuit, FIG. 3 is a block diagram of an example of a configuration of a synchronous/asynchronous determination circuit, and FIG. The figure is a block diagram showing a conventional phase synchronization circuit. 1... Input terminal 2... Phase comparator 3... Synchronous/asynchronous judgment circuit 4... Pull-in allowable range judgment circuit 5... Low-pass filter 6... Switcher 7... Voltage controlled oscillator 8... 1/N frequency divider circuit 9... Output terminal

Claims (2)

[Claims] (1) A phase comparator that compares the phase of the input signal and the phase of the 1/N frequency divider circuit output, a low-pass filter that filters the output of the phase comparator, and a low-pass filter that filters the output of the low-pass filter. In a phase synchronized circuit comprising a voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and the 1/N frequency dividing circuit that frequency divides the output of the voltage controlled oscillator, the input signal and the 1/N frequency dividing circuit A synchronous/asynchronous determination circuit detects the magnitude of the phase difference with the output and determines synchronous/asynchronous based on whether the phase difference is smaller or larger than a preset value; a pull-in permissible range determination circuit that detects and determines whether the phase is stable/unstable depending on whether the phase is smaller or larger than a preset value; and the synchronization/asynchronous determination circuit provided between the phase comparator and the voltage controlled oscillator. The output of the voltage controlled oscillator is provided with a switch that switches between the input voltage and a preset constant voltage based on the output and the output of the pull-in allowable range determination circuit, and the voltage controlled oscillator is controlled depending on the synchronous/asynchronous state and the stable/unstable state of the phase of the input signal. A phase-locked circuit characterized by switching input control voltage. (2) In the phase-locked circuit according to claim 1, the switch switches to the constant voltage when the synchronization/asynchronous determination circuit detects an asynchronous state, and switches the voltage to the constant voltage when the synchronization/asynchronous determination circuit detects an asynchronous state; A phase synchronized circuit characterized in that when an allowable range determining circuit determines that the phase of the input signal is in a stable state, the circuit switches to the input voltage.