KR100207633B1 - Phase locked loop circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop circuit, wherein a vertical blanking signal is synchronized with a horizontal sync signal so that the vertical blanking signal is synchronized with each other in the even field and the odd field of the video signal for interlaced scanning. It is possible to prevent the top of the screen from warping due to instability of the horizontal synchronization signal on the magnetic tape or during the special playback of the VTR.

Description

Phase locked loop circuit

1 is a block diagram showing a conventional phase locked loop.

2 is a block diagram according to an embodiment of a phase locked loop circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

21: phase comparator 22: low pass filter

23: voltage controlled oscillator 24: clock divider

25: switching signal generator 26: switching unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit. In particular, in a phase locked loop circuit using horizontal synchronization of an image signal, an entire circuit is prevented from becoming unstable due to horizontal instability during a vertical blanking period of the image signal. It relates to a phase locked loop circuit.

FIG. 1 is a block diagram showing a conventional phase synchronous loop circuit. The phase comparator 11 detects a phase difference between a horizontal synchronous signal fr and an N divided clock signal fv, and an error pulse voltage corresponding to the phase difference is a low pass filter ( 13 is applied to the voltage-controlled oscillator 15 by changing to DC voltage. The voltage controlled oscillator 15 outputs a clock signal whose oscillation frequency is controlled by the output voltage of the low pass filter 13. The clock divider 17 divides the frequency of the clock signal oscillated by the voltage controlled oscillator 15 by N. Here, the characteristics of the entire phase synchronizing loop which is synchronized with the speed of the low pass filter 13 are affected.

As described above, the conventional phase synchronization loop circuit has some equalization pulses and horizontal synchronization signals for interlaced scanning during the vertical blanking period of the video signals when operating using the horizontal synchronization signals of the video signals. During or during the special playback of the VTR, it is difficult to reproduce the accurate horizontal sync signal from it, and the top of the screen is bent due to the unstable horizontal sync signal.

Accordingly, an object of the present invention is to provide a phase synchronization loop circuit for preventing the upper part of the screen from bending due to the instability of the horizontal synchronization signal in some VTR magnetic tapes or during special playback of the VTR in order to solve the above problems. .

In order to achieve the above object, a phase locked loop circuit according to the present invention

A switching signal generator for generating a vertical blanking signal synchronized with the horizontal synchronization signal as a switching signal;

A switching unit for selectively outputting a horizontal synchronization signal or an N-divided clock signal in accordance with a vertical blanking signal synchronized with the horizontal synchronization signal output from the switching signal generator;

A phase comparator for outputting an error voltage corresponding to a phase difference by comparing a phase of a horizontal synchronization signal or an N divided clock signal and an N divided clock signal selectively output from the switching unit;

A low pass filter for outputting the error voltage output from the phase comparator as a DC voltage;

A voltage controlled oscillator for outputting a clock signal whose oscillation frequency is varied according to the DC voltage output from the low pass filter; And

And a clock divider for dividing the clock signal output from the voltage controlled oscillator by N and outputting the clock signal to the phase comparator and the switching unit.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

2 is a block diagram according to an embodiment of a phase-locked loop circuit according to the present invention, in which a phase comparator 21, a low pass filter 22, a voltage controlled oscillator 23, and a clock divider 24 are shown in FIG. The same as in Fig., In addition to the switching signal generator 25 and the switching unit 26 is added. The switching signal generator 25 is a D flip-flop for applying a vertical blanking signal to the D input terminal and a horizontal synchronous signal to the clock terminal.

Operation according to the configuration of Figure 2 is as follows.

The switching signal generator 25 is for generating a vertical blanking signal synchronized with the horizontal synchronizing signal as a switching signal. The vertical blanking signal synchronized with the horizontal synchronizing signal is a vertical blanking signal even for interlaced scanning. This is to synchronize the horizontal synchronization between the field and the odd field.

The switching unit 26 selectively outputs the horizontal synchronizing signal or the N-divided clock signal in accordance with the vertical blanking signal synchronized with the horizontal synchronizing signal output from the switching signal generator 25.

The phase comparator 21 compares the phase of the horizontal synchronizing signal fr or the N-divided clock signal fv and the N-divided clock signal fv selectively output from the switching unit 26, and corresponds to the phase difference. Output voltage.

The low pass filter 22 low-pass filters the error voltage output from the phase comparator 21 as in FIG. 1 and outputs it as a DC voltage.

The voltage controlled oscillator 23 outputs a clock signal whose oscillation frequency is varied according to the DC voltage output from the low pass filter 22 as in FIG.

The clock divider 24 divides the clock signal output from the voltage controlled oscillator 23 by N, and outputs the N divided clock signal fv to the phase comparator 21 or the switching unit 26.

As described above, in the phase-locked loop circuit according to the present invention, the vertical blanking signal is synchronized with each other in the even field and the odd field of the video signal for interlaced scanning by using the vertical blanking signal synchronized with the horizontal sync signal. On some VTR magnetic tapes or during special playback of the VTR, there is an advantage that the upper part of the screen can be prevented due to instability of the horizontal synchronization signal.

Claims (2)

A switching signal generator for generating a vertical blanking signal synchronized with the horizontal synchronization signal as a switching signal; A switching unit for selectively outputting a horizontal synchronization signal or an N-divided clock signal in accordance with a vertical blanking signal synchronized with the horizontal synchronization signal output from the switching signal generator; A phase comparator for outputting an error voltage corresponding to a phase difference by comparing a phase of a horizontal synchronization signal or an N divided clock signal and an N divided clock signal selectively output from the switching unit; A low pass filter for outputting the error voltage output from the phase comparator as a DC voltage; A voltage controlled oscillator for outputting a clock signal whose oscillation frequency is varied according to the DC voltage output from the low pass filter; And a clock divider for dividing the clock signal output from the voltage controlled oscillator by N and outputting the clock signal to the phase comparator and the switching unit. The phase difference is detected by the horizontal synchronization signal and the N divided clock signal when an image signal is input. And when the vertical blanking signal is input, detect a phase difference using only the N-divided clock signal. 2. The phase locked loop circuit of claim 1, wherein the switching signal generator comprises a D flip-flop for applying a vertical blanking signal to a D input terminal and a horizontal synchronous signal to a clock terminal.