JPH0322773A - Phase locked type oscillation circuit - Google Patents

Abstract

PURPOSE:To stabilize the oscillation frequency and to improve responsiveness to a skew by switching the outputs of filters when video heads are switched, and supplying a voltage-controlled oscillator with the output of a 2nd filter which passes even a frequency component higher than a frequency component passed through a 1st normal filter. CONSTITUTION:When the scanning of the video heads is switched from a specific track to an adjacent track, a control circuit 5 generates a control signal for a specific time, and consequently a switching circuit 4 is put in switching operation tc supply the output signal 200 of the 2nd filter 3 to the voltage- controlled oscillator 6 through the switching circuit 4. The 2nd filter 3 passes the higher frequency component than the 1st filter 2, so when the output signal 200 of the 2nd filter 3 is supplied to the voltage-controlled oscillator 6, the response characteristics of a PLL system becomes faster than usual. Consequently' the frequency is stabilized with the simple circuit constitution and excellent response characteristics to variation of a synchronizing signal are obtained.

Description

[Detailed description of the invention] [Purpose of the invention] 《Industrial application field〉 The present invention relates to a phase-locked oscillator circuit.

(Prior Art) As a means for generating a signal with a frequency N times higher than a synchronization signal in a video signal reproduced by a video tape recorder,
Generally, a phase-locked oscillation circuit (referred to as a P and L circuit) is used.

This phase-locked oscillator circuit includes a phase comparator, into which the horizontal synchronizing signal in the reproduced video signal is input to one input terminal, and to which the output signal of the 1/N frequency dividing circuit is guided to the other input terminal; A filter that passes only a predetermined frequency component from the output signal of this phase comparator, and a voltage controlled oscillator (V
CO) and a frequency dividing circuit that divides the output signal of this oscillator by 1/N and feeds it back to the phase comparator.

In a helical scan type video tape recorder, one field's worth of video signals is usually recorded on one track formed diagonally on the tape. Therefore, the period of the horizontal synchronizing signal included in the video signal inside the track is determined by the accuracy of the scanning speed of the head, and is generally 1% or less. However, when switching from one track to the next, the time from the immediately previous horizontal synchronizing signal to the immediately following horizontal synchronizing signal may deviate greatly from the period of the horizontal synchronizing signal (so-called skip 1-1). ).

Conventionally, such problems have been left to the tracking performance of the PLL system. That is, a PLL system loop was used to speed up the response characteristics and quickly respond to changes in the input signal. By speeding up the response characteristics of the PLL system in this way,
This results in a disadvantage that the loop becomes vulnerable to external noise and responds as if the input signal has changed even though the input signal has not changed. In this regard, in the past, it was desirable to have a relatively small division ratio (i.e., low oscillation frequency) and a high stability of the oscillation frequency (i.e., stability with respect to jitter in the oscillation frequency). Because the school did not have the above-mentioned drawbacks, it did not become a major problem.

However, in recent years, for example, the Sengawa method has appeared, which performs arithmetic processing (correlation processing, etc.) on one pixel in the time axis direction, and there is a need for stabilization of the oscillation frequency and good response characteristics in skew. Therefore, the above-mentioned drawbacks become a very big problem.

(Problems to be Solved by the Invention) As described above, stabilization of the oscillation frequency and good response to skew have been required.

Therefore, the present invention is intended to eliminate the above problems.
It is an object of the present invention to provide a phase-locked oscillator circuit that can stabilize the frequency and provide good response characteristics to changes in the synchronous signal ε with a simple circuit configuration.

[Structure of the Invention] <<Means for Solving the Problems>> In order to achieve the above object, a first aspect of the phase synchronized oscillation circuit of the present invention is as follows. a phase comparator to which a synchronizing signal is introduced to one input terminal; a first filter to which the output signal of the phase comparator is supplied and which passes a predetermined frequency component; and a first filter to which the output signal of the phase comparator is supplied. a second filter that passes even frequency components higher than the frequency components passed by the first filter; a switching circuit for switching the output signal of the second filter; and a switching circuit for controlling the switching circuit, the switching circuit for switching the switching circuit for a predetermined period when the scanning of the video head switches from a predetermined track to an adjacent track. k! from the first filter output! a control circuit that switches to a second filter output; a voltage controlled oscillator that is supplied with the output signal of the first or second filter from the switching circuit and outputs a signal with a frequency proportional to the output signal; A frequency dividing circuit divides the output signal of the oscillator by 1/N (N is an integer) and returns the frequency to the other input terminal of the phase comparator.

Further, as a second aspect of the present invention, the control circuit includes:
J1 set in advance after the video head is switched
The - switching circuit may be configured to switch from the first filter output to the second filter output during both the interval and the period during which dropout occurring between the tape and the head is detected. can.

Furthermore, a third aspect of the phase-locked oscillator circuit according to the present invention includes a phase comparator to which a doro signal in a reproduced video signal of a video tape recorder equipped with a plurality of video heads is guided to one input terminal; a first filter to which the output signal of the phase comparator is supplied and which passes a predetermined frequency component; and a first filter which is supplied with the output signal of the phase comparator and which passes even frequency components higher than the frequency components passed by the first filter. a second filter that switches between the output signals of the first and second filters; and a switching circuit that switches the output signals of the first and second filters; the switching circuit supplies the output signals of the first or second filters, and a frequency proportional to the output signals; a voltage t, llt[l oscillator that outputs a signal of and a pulse generation circuit that generates a pulse of a predetermined width based on the output signal of this frequency dividing circuit; and a pulse generation circuit that checks the presence or absence of the synchronization signal within a period in which the pulse is input from this pulse generation circuit, and generates a synchronization signal. A discriminating circuit that outputs a discriminating signal when there is no discriminating circuit and the switching circuit, and for a predetermined period after the discriminating signal is input from the discriminating circuit, the switching circuit is switched to the first filter output. and a control path for switching from the second filter output to the second filter output.

Further, as a fourth aspect of the present invention, the IfJIIl1 circuit in the third aspect operates during a preset period after inputting the discrimination signal from the discrimination circuit and during a period during which dropout occurring between the tape and the head is detected. The switching circuit may also be called a kankai in which the switching circuit is switched from the first filter output to the second filter output during both periods.

(Operation) In the first and twelfth aspects of the present invention, when the video head is switched, the output of the filter is switched, and the second filter passes through the frequency components higher than the frequency components passed by the normal first filter. The output of is the voltage υj
tlB oscillator. Therefore, the response characteristics of the PLL system become faster than in the past, and the time required for re-engaging the PLL system when the video head is switched is shortened. Therefore, frequency stability is also improved.

Further, in the third and fourth aspects of the present invention, when the period shift of the synchronization signal in the reproduced video signal exceeds a predetermined tolerance range, the output of the filter is switched and
The output of the second filter, which passes frequency components higher than those passed by the second filter, is supplied to the voltage controlled oscillator.

Therefore, as described above, the response characteristics of the PLL system become faster than before, and the time required for re-engaging the PLL system when the video head is switched is shortened.

(Example) The present invention will be described below based on the example shown in the drawings.

FIG. 1 is a block diagram showing an in-phase fill type oscillation circuit according to an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG.

In FIG. 1, the phase-locked oscillator circuit includes a phase comparator 1
, 1.12 filters 2 and 3, a switching circuit 4, a υ+m circuit 5, a voltage controlled oscillator 6, and a frequency dividing circuit 7. The phase comparator 1 receives the horizontal synchronizing signal separated from the reproduced video signal at one input terminal, and receives the output signal from the 1/N frequency dividing circuit 7 at the other input terminal.

The first filter 2 is a filter that passes only a predetermined frequency component behind the output signal of the phase comparator 1, and the second filter 3 is a filter that passes frequency components higher than the predetermined frequency component that is passed by the filter 2. It is. The switching circuit 4 is a circuit that selects and outputs either the output signal 100 of the filter 2 or the output signal 200 of the filter 3. This switching circuit 4 normally outputs the output signal 100 of the first filter 2 to the terminal a side, but when the control signal l; is given from the control circuit 5, the second output signal 100 input to the terminal b side
The output signal 200 of the filter 3 is output. ilI1
The rn circuit 5 generates a control signal for a predetermined period of time after the scanning of a video head (not shown) is switched.
This ill control signal is generated, for example, by measuring a predetermined number of horizontal synchronization signals supplied to the other input terminal from the time when the state of the head switching signal supplied to one input terminal changes.

The voltage controlled oscillator 6 oscillates a frequency M corresponding to the voltage output from the switching circuit 4, and is, for example, an RC oscillator.
type oscillator. LC type oscillator. Or it is composed of a crystal oscillator, etc.

The frequency dividing circuit 7 divides the output signal of the voltage ill control oscillator 6 into 17
This circuit divides the frequency into N and feeds it back to the phase comparator 1. Note that the time during which the switching circuit 4 supplies the output signal @200 of the second filter 3 to the voltage 1i1J all oscillator 6 according to the 11Jtll signal is such that the output signal 200 of the filter 3 is supplied to the voltage 11i11rIA oscillator 6 after head switching; The output signal of the voltage i, IJ control oscillator 6 is sent to the frequency dividing circuit 7
It is necessary to set it to Rrta until the transient state of the output state has elapsed. Further, the horizontal synchronizing signal input to the phase comparator 1 may be a horizontal synchronizing signal whose frequency is divided to 1/M via a 1/M frequency dividing circuit (not shown). When configured as follows, the output frequency fo of the voltage II1 controlled oscillator 6
is fo − (N/M)·fH (fH is the frequency of the horizontal synchronization signal).

Next, the operation of the circuit configured as described above will be explained with reference to the signal waveforms shown in FIG.

Assume that a horizontal Jllll signal as shown in FIG. 2(b) is supplied to one input terminal of the phase comparator 1.

The output signal of the voltage υIlil oscillator 6 is frequency-divided by 1/N by a frequency divider circuit 7. The phase comparator 1 is shown in FIG. 2(b).
The horizontal synchronizing signal shown in FIG. 2(C) and the frequency dividing circuit 7 shown in FIG. 2(C)
The output signals of are compared in phase. The output signal of the phase comparator 1 is supplied to first and second filters 2 and 3. The output signal υ100 of the first filter 2 is supplied to the terminal a side of the switching circuit 4, and the output signal 2 0 0 t,
t l; Supplied to the terminal b side of the 7J switching circuit 4.

Normally, the output signal 100 of the first filter 2 is connected to the switching circuit,
4 to the voltage controlled oscillator 6, as shown in FIG.
When the state of the head switching signal changes as shown in a),
As shown in FIG. 2(d), a control signal is generated from the ilIIJ Miusuji 5 for a predetermined period of time, whereby the switching circuit 4 performs a switching operation, and the output signal 200 of the second filter 3 is transmitted to the switching circuit 4. The voltage υ1 is supplied to the control oscillator 6 via the voltage υ1. Since the second filter 3 passes frequency components higher than those of the first filter 2, the output signal 20 of the second filter 3
0 is the voltage 2I11 oscillation i? PL when supplied to ii6
The response characteristic of the L system becomes faster than usual, and the time required for re-engaging the PLL system when the video head is switched is shortened.

In the above embodiment, the control circuit 5 is configured to create a control signal using the head switching signal and the horizontal synchronization signal, but the control circuit 5 is not limited to this configuration. It may also be created using a monostable multivibrator or the like based on the point in time.

Further, in the above embodiment, the switching circuit 4 is switched for a predetermined period after head switching is performed to supply the output signal of the second filter 3 to the voltage & IJ III oscillator 6, but in the present invention, this configuration is adopted. Instead of the configuration, an OR condition is taken between a predetermined period after head switching is performed and I1 when a dropout (missing signal) occurring between the tape and the head is detected, and the output period is determined by the switching circuit 4.
It is also possible to adopt a configuration in which the output signal of the second filter 3 is supplied to the voltage controlled oscillator 6 by switching. In addition, stills (
During special playback such as still image playback, the above switching is performed for a predetermined period immediately after the re-41 signal disappears, based on the noise that occurs when playing back a track recorded at an azimuth angle different from the azimuth angle of the playback head. The configuration may be such that the circuit 4 is switched to supply the output signal of the second filter 3 to the voltage controlled oscillator 6.

FIG. 3 is a block diagram showing a phase synchronized oscillator circuit according to another embodiment of the present invention, and FIG. 4 is a signal waveform diagram of each part of the circuit shown in FIG.

In FIG. 3, components having the same functions as those in the embodiment of FIG. 1 are given the same reference numerals. Also, the phase comparator 1, the first .
The second filter 2.3, switching circuit 4, control circuit 5, voltage controlled oscillator 6, and frequency dividing circuit 7 have the same circuit functions as in the embodiment of FIG. The difference from the embodiment shown in FIG. 1 is that a pulse generation circuit 8 and a discrimination circuit 9 are provided, and the control circuit 5 is supplied with a discrimination signal from the discrimination circuit 9 instead of the head switching signal shown in FIG. This is what I did. The pulse generating circuit 8 is a circuit that generates a pulse of a predetermined width based on the output signal of the frequency dividing circuit 7. The discrimination circuit 9 is a circuit having a function of checking whether or not a horizontal synchronization signal is present within the period in which the pulse is outputted from the pulse generation circuit 8, and outputting a discrimination signal when there is no horizontal synchronization signal. be.

The control circuit 5 generates a υ1 control signal for a predetermined period of time after the discrimination signal from the discrimination circuit 9 is input. Then, a predetermined number of horizontal synchronizing signals to be supplied to the other input terminal are measured and created. Other precepts are the same as in Figure 1. In the case of the embodiment shown in FIG. 3 as well, the time during which the switching circuit 4 supplies the output signal 200 of the second filter 3 to the voltage controlled oscillator 6 according to the Moeki control signal is equal to the output signal of the filter 3 after head switching. 20
0 is supplied to the voltage controlled oscillator 6, the output signal of the voltage controlled oscillator 6 is divided by the frequency dividing circuit 7 and supplied to the phase comparator 1, and is set to the time until the transition period of the output state has elapsed. It is necessary to keep it. Further, the horizontal synchronization signal input to the phase comparator 1 may be a horizontal synchronization signal whose frequency is divided to 17M via a 1/M frequency division circuit (not shown). However, when configured in this way, the output frequency 0 of the voltage controlled oscillator 6 is f'o - (N/M)·f II (f
11 is the frequency of the horizontal synchronization signal).

Next, the operation of the circuit configured as described above will be explained with reference to the signal waveforms shown in Figure 4.

Assume that a horizontal synchronizing signal 2} as shown in FIG. 4(a) is supplied to one input terminal of the phase comparator 1.

The output signal of the voltage υl control oscillator 6 is divided into 1 by the frequency dividing circuit 7.
/N. The phase comparator 1 compares the phases of the horizontal synchronous signal 8 shown in FIG. 4(a) and the output signal of the frequency dividing circuit 7 shown in FIG. 4(b). The output signal of phase comparator 1 is the first
and is supplied to the second filter 2.3. The output signal 100 of the first filter 2 is supplied to the terminal a side of the switching circuit 4, and the output signal 200 of the second filter 3 is supplied to the terminal b side of the switching circuit 4.

The output signal of the frequency dividing circuit 7 is input to the pulse generating circuit 8,
In the pulse generation circuit 8, based on the output signal of the frequency dividing circuit 7,
A pulse having a predetermined pulse width as shown in FIG. 4(C) is output. The pulses output from the pulse generation circuit 8 are input to the discrimination circuit 9. The discrimination circuit 9 checks whether there is, for example, a falling edge portion of the horizontal synchronizing signal within the period during which the pulse is input, and if there is no falling edge portion, it is determined as shown in FIG. 4(d). Outputs a discrimination signal as shown. When the discrimination signal is output from the discrimination circuit 9, II
I1t11 circuit 5 is 111m as shown in button 4 (e)
A signal is generated for a predetermined period of time, and the switching circuit 4 performs a switching operation based on the Ill control signal. That is, normally the first filter 2
An output signal 100 is supplied to the voltage controlled oscillator 6 via the switching circuit 4, but when the discrimination signal is output from the discrimination circuit 9, a control signal is generated from the control circuit 5 for a predetermined time, and the switching circuit 4 switches. In operation, the output signal 200 of the second filter 3 is supplied to the voltage υ1111 oscillator 6 via the switching circuit 4. Since the second filter 3 passes frequency components higher than those of the first filter 2, the second filter 3
When the output signal 200 of υIt11 is supplied to the voltage υIt11 oscillator 6, the response characteristics of the PLL system become faster than normal, and the time required for re-engaging the PLL system when the period of the horizontal synchronizer A3 is greatly shifted is shortened. Ru.

In the embodiment shown in FIG. 3, the δJim circuit 5 is configured to create the 1 and II control signals using the discrimination signal and the horizontal synchronization signal, but the illill control circuit 5 is not limited to this configuration. The signal may be generated using a monostable multivibrator or the like at the time when determination A8 is input.

Further, in the embodiment shown in FIG. 3 above, the discrimination signal is
The configuration is such that the switching circuit 4 is switched over for a predetermined period of time after the input signal is input to the voltage controlled oscillator 6 to supply the output 3 of the second filter 3 to the voltage controlled oscillator 6. However, in the present invention, instead of this configuration, the discrimination signal is controlled. A predetermined period after being input to the circuit 5,
The output signal of the second filter 3 is changed to the voltage υ1lI by making an OR condition with the period in which dropout occurring between the heads is detected, and switching the switching circuit 4 during that output period.
It may be configured such that the signal is supplied to the l oscillator 6. Zarani? During special playback such as chill (still image) playback, the switching is performed for a predetermined period immediately after the playback signal disappears based on the noise that occurs when playing back a track recorded at an azimuth angle different from the azimuth angle of the playback head. The circuit 4 may be switched to supply the output signal of the second filter 3 to the voltage 111311 oscillator 6.

[Effects of the Invention] As described above, according to the present invention, with a simple circuit configuration,
Good response characteristics can be obtained with respect to changes in the synchronization signal. Therefore, since the pull-in to the Doro signal is fast,
The oscillation frequency of the PLL can be stabilized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a phase-locked oscillation circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit in FIG. 1, and FIG. 3 is a diagram showing another embodiment of the present invention. Block diagram shown, No. 4
The figure is a signal waveform diagram of each part of the 3rd liiJ circuit. 1... Phase comparator, 2... First filter, 3...
・Third filter, 4... switching circuit, 5... 111
11 circuits, 6...voltage controlled oscillator, 7...frequency dividing circuit, 8...pulse generation circuit, 9...discrimination circuit.

Claims (4)

[Claims] (1) A phase comparator to which a synchronizing signal in the reproduced video signal of a video tape recorder equipped with a plurality of video heads is guided to one input terminal; a first filter that allows the output signal to pass; a second filter that is supplied with the output signal of the phase comparator and that allows even frequency components higher than the pass frequency components of the first filter to pass; and the first and second filters. a switching circuit for switching the output signal of the first switching circuit; and a switching circuit for switching the switching circuit, the switching circuit controlling the switching circuit for a predetermined period when the scanning of the video head switches from a predetermined track to an adjacent track. a control circuit that switches from the filter output to the second filter output; and a voltage controlled oscillator that is supplied with the output signal of the first or second filter from the switching circuit and outputs a signal with a frequency proportional to the output signal. and a frequency dividing circuit that divides the output signal of the voltage controlled oscillator by 1/N (N is an integer) and feeds it back to the other input terminal of the phase comparator. Oscillation circuit. (2) In the phase-locked oscillator circuit according to claim 1, the control circuit controls both a preset period after the video head is switched and a period in which dropout occurring between the tape and the head is detected. A phase synchronized oscillation circuit characterized in that the switching circuit switches from the first filter output to the second filter output during a period. (3) A phase comparator to which a synchronizing signal in the reproduced video signal of a video tape recorder equipped with a plurality of video heads is guided to one input terminal; a first filter that allows the output signal to pass; a second filter that is supplied with the output signal of the phase comparator and that allows even frequency components higher than the pass frequency components of the first filter to pass; and the first and second filters. a switching circuit that switches the output signal of the first or second filter; a voltage controlled oscillator that is supplied with the output signal of the first or second filter and outputs a signal with a frequency proportional to the output signal; A frequency dividing circuit that divides the output signal by 1/N (N is an integer) and feeds it back to the other input terminal of the phase comparator, and generates a pulse of a predetermined width based on the output signal of this frequency dividing circuit. a pulse generating circuit that checks the presence or absence of the synchronizing signal within a period in which the pulse is input from the pulse generating circuit, and outputs a determination signal when there is no synchronizing signal, and switching control of the switching circuit. and a control circuit that switches the switching circuit from the first filter output to the second filter output for a predetermined period after the discrimination signal is input from the discrimination circuit. Phase synchronized oscillator circuit. (4) In the phase-locked oscillator circuit according to claim 3, the control circuit has a preset period after inputting the discrimination signal from the discrimination circuit and a period during which dropout occurring between the tape and the head is detected. A phase synchronized oscillation circuit characterized in that the switching circuit switches from the first filter output to the second filter output during both periods.