JPH01198828A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To prevent transient phenomenon from being occurred in the changeover of a band width of a loop by providing the 1st frequency division means frequency-dividing into n to an input, outputting the result of giving direct output. CONSTITUTION:The 1st frequency division means 2 frequency-divides into n to an input signal by a switching signal from a synchronizing detection means 4, gives an output or outputs the signal directly. The 2nd frequency division means 5 frequency-divides into n to an output signal of a voltage controlled oscillator 13 by a switching signal from a synchronizing detection means 4, gives an output or outputs the signal directly. When the synchronizing detection means 4 detects the synchronization of the output of the voltage controlled oscillator 13 with the input signal, a switching signal is sent to the 1st and 2nd frequency division means 2, 5 to apply the result frequency-divided into n to the input signal and the output of the voltage controlled oscillator 13. Thus, the modulation sensitivity is 1/n than before synchronization and the band width of the loop is made narrow. Thus, since the input/output characteristic of the phase detector 3 is kept as it is at switching, no transient phenomenon takes place.

Description

[Detailed Description of the Invention] [Summary] For example, regarding a phase-locked loop circuit used when extracting a clock synchronized with data, the present invention aims to prevent transient phenomena from occurring when switching the loop bandwidth. A first frequency dividing means that divides the input signal by n and outputs the frequency divided by n in response to the state of the switching signal from the synchronization detection means, or outputs the frequency directly, and Detecting that a second frequency dividing means correspondingly divides the output of the voltage controlled oscillator by n and outputs it or outputs it directly, and the outputs of the first and second frequency dividing means enter a synchronized state. synchronization detection means for sending out switching signals in different states when the second frequency division means is applied; a phase detector for phase detecting the output of the tenth frequency division means using the output of the second frequency division means; and an output of the phase detector. and a voltage controlled oscillator whose oscillation frequency is controlled so that the outputs of the first and second frequency dividing means are synchronized by the output of the loop filter. do.

[Industrial application field]

The present invention relates to a phase-locked loop circuit used, for example, when extracting a clock synchronized with data.

A phase-locked loop circuit is used to synchronize the phase of the output of a voltage controlled oscillator with the phase of the reference input signal.
Not only do the phases match, but the 9 frequencies also completely match, so it is widely used in clock extraction, carrier wave regeneration, 9-frequency synthesizers, etc. (although this circuit takes a short time to synchronize, and after synchronization Highly pure synchronous output must be sent out.

For this reason, the parameters of the phase-locked loop are switched when synchronization is achieved, but it is necessary to prevent transient phenomena from occurring during this switching.

[Conventional technology]

FIG. 4 shows a block diagram of a conventional example. The operation of the diagram will be described below assuming that the resistance value of the resistor R4 is higher than the resistance value of the resistor R2.

For example, if a clock buried in noise is detected by a phase detector (hereinafter referred to as
(abbreviated as PD) 11, where a voltage controlled oscillator (hereinafter referred to as
Since the output of 13 (abbreviated as VCO) is applied,
The phase of the above clock is detected by the output of the vCO to obtain a detected output.

This detection output is generated by the resistors R, , R, , R3, C and the operational amplifier 14. A phase difference signal is extracted through a loop filter made up of a resistor R1 and is applied to the VCO 13 as a control signal. Therefore, the oscillation frequency is controlled so that the output of the VCO 13 is shifted by 1, for example, 180 degrees with respect to the input clock.

Here, when the synchronization detector 12 detects that there is a phase difference of 180 degrees between the input clock and the output of the VCO, it determines that the synchronization state is established, and sends a switching signal to the switch 15 to switch from R4 to R3 and switch the operational amplifier. 14, and the loop bandwidth of the phase-locked loop circuit (hereinafter abbreviated as PLL) is made narrower than above.

Therefore, the VCO 13 sends out an output with less jitter, that is, a reproduced clock.

Now, the PLL pull-in time T and the PLL bandwidth BL
The relationship with John Wiley &
Floyd M, Gard, published by Son.
rl'hase Lock written by ner, Ph, D
Techniques J, page 76, formula 5.11 (formula (1) below). That is, however, BL is P
The bandwidth of LL is shown, and as shown in Examples and Table 3.1 on pages 15 and 31 of the same book, for example, the higher the modulation sensitivity of vCO, the wider it becomes, and the lower it becomes, the narrower it becomes. Further, Δf indicates an offset frequency from the center frequency.

That is, as described above, until the PLL is pulled in, that is, until synchronization is achieved, BL is widened and TP is shortened.

Select R4 with a large resistance value using switch 15 to increase the gain (multiple) of the operational amplifier, and increase the modulation sensitivity of the VCO by the gain times 0.

On the other hand, after synchronization is achieved, in order to narrow the BL and minimize the jitter of the recovered clock, the switch 15 selects Rs, which has a small resistance value, and lowers the gain of the operational amplifier.
For CO modulation sensitivity. be smaller than the above.

[Problem to be solved by the invention]

That is, until synchronization is achieved, the resistance of the operational amplifier 14 is R4.
When synchronization is achieved, switch 15 is used to switch to R3 to change the gain, but when switching, the PLL
However, there is a problem in that a transient phenomenon as shown in FIG. 5 occurs and it takes time for it to stabilize.

During this transient phenomenon, jitter is added to the recovered clock, so that, for example, the error rate may deteriorate.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 2 is a first circuit which divides the input signal by n and outputs it or directly outputs it, depending on the state of the switching signal from the synchronization detection means.
5 is a second frequency dividing means which divides the output of the voltage controlled oscillator by n and outputs the divided frequency or directly outputs the frequency divided by n in accordance with the state of the switching signal from the synchronization detection means; is the first
and a synchronization detection means that sends out a switching signal of a different state when it is detected that the output of the second frequency dividing means enters a synchronization state.

Further, 3 is a phase detector that detects the phase of the output of the first frequency dividing means using the output of the second frequency dividing means, and 6 is a loop that extracts a phase difference signal from the output of the phase detector. 13 is the voltage controlled oscillator whose oscillation frequency is controlled so that the outputs of the first and second frequency dividing means are synchronized by the output of the loop filter.

[Effect]

Generally, a phase detector 3. The bandwidth of the PLL composed of the loop filter 6 and the voltage controlled oscillator 13 increases as the modulation sensitivity of the voltage controlled oscillator increases.

It is widely known that the lower the area, the narrower it becomes.

In the present invention, when the synchronization detection means 4 detects that the output of the voltage controlled oscillator 13 is synchronized with the input signal, the gain of the operational amplifier, which is a component of the loop filter 6, is not switched but remains constant. A switching signal is sent to the first frequency dividing means 2 and the second frequency dividing means 5, and the frequency of the input signal and the output of the voltage controlled oscillator 13 is divided by n, respectively, and the resulting signal is divided by n to the phase detector 3.
I added it to As a result, as is well known, the modulation sensitivity becomes (1/n) more than before synchronization, and the bandwidth of the PLL becomes narrower.

Incidentally, at the time of switching, the input/output characteristics of the 1-phase detector 3 are maintained as they are, so no transient phenomenon occurs.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2.

Note that the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG. Here, the frequency divider 21. The switch 22 is a component of the first frequency dividing means, the synchronization detector 41 is a component of the synchronization detection means 4, the frequency divider 51 . Switch 52. The inverter 53 is a component of the second frequency dividing means 5, and a resistor RI"'
R3+ R6+ Capacitor C1 Operational amplifier 61 represents a component of loop filter 6.

Also, the same reference numerals indicate the same objects throughout the figures.

The operation of FIG. 2 will be described below with reference to FIG. 3 assuming n=2.

(If the input clock 11 and the VCO output are asynchronous, for example, if the input clock and the output of the VCO 13 shown on the left side of Figure 3 - ■, ■, ■, ■ are asynchronous, Therefore, the input clock is input to the phase detector 11 as is.

On the other hand, since the output of the VCO 13 is applied here via the inverter 53° switch 52, the above input clock is phase detected by the inverted output of the VCO, and the third
The detection output shown on the left side of Figure 2 is obtained.

This detection output is passed through a loop filter consisting of a resistor R1 + R1 + R3 + a capacitor C1, and an operational amplifier 61 to extract a phase difference signal, which is then output as a control signal to V.
vCO added to CO13 and inverted with the input clock
The oscillation frequency is controlled so that the phase difference with the output of is 1, for example, 180°.

Note that the loop bandwidth at this time is BL.

(2) When the input clock and VCO output are synchronized, the input clock and
When the phase difference with the CO output is 1, for example 180°, v
Since the output of CO is determined to be synchronized with the input clock, the synchronization detector 41 detects this state and switches switch 2.
2.Switch 52 from side a to side b at the same time.

As a result, the phase detector 3 receives the input clock and the VCO.
The output obtained by dividing the frequency by two is input, but there is no phase discontinuity during this switching as shown in FIG.

Here, the bandwidth B of the PLL is the modulation sensitivity K of the VCO.

As mentioned in the conventional example section, if the frequency is high, it is wide, and if it is low, it is narrow. However, by setting the frequency of the input clock to , the modulation sensitivity becomes 0, as is known.

Bandwidth BL becomes narrower.

Moreover, since the gain of the operational amplifier 61 is the same value without switching both terms (1) and (2), even if the PLL bandwidth BL is narrowed when entering the synchronized state from the asynchronous state, transient phenomena will not occur. does not occur.

〔Effect of the invention〕

As described above in detail, the present invention has the effect that no transient phenomenon occurs even when the PLL bandwidth is switched.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram of an embodiment of the present invention. Fig. 3 is an explanatory diagram of the operation of No. δ, Figure 4 is a block diagram of the conventional example. FIG. 5 shows an explanatory diagram of the operation of FIG. 4. In the figure, 2 is a first frequency dividing means; 3 is a phase detector, 4 is a synchronization detection means; 5 is a second frequency dividing means; 6 is a loop filter, 13 indicates a voltage controlled oscillator. ■

Claims (1)

[Claims] a first frequency dividing means (2) that divides the input signal by n (n is a positive integer) and outputs the divided signal or directly outputs the divided signal according to the state of the switching signal from the synchronization detecting means (4); Synchronization detection means (4
) in response to the state of the switching signal from the voltage controlled oscillator (1
3), which divides the output by n and outputs it, or outputs it directly.
a frequency dividing means (5), and the first and second frequency dividing means (2,
synchronization detection means (4) that sends a switching signal of a different state when it detects that the output of 5) enters a synchronization state, and the output of the second frequency division means (5) to a phase detector (3) for phase detecting the output of the frequency dividing means (2); a loop filter (6) for extracting a phase difference signal from the output of the phase detector; A phase-locked loop circuit comprising the voltage controlled oscillator (13) whose oscillation frequency is controlled so that the outputs of the second frequency dividing means (2, 5) are synchronized.