CN110324036B - Clock and data recovery circuit - Google Patents

Clock and data recovery circuit Download PDF

Info

Publication number
CN110324036B
CN110324036B CN201810265465.8A CN201810265465A CN110324036B CN 110324036 B CN110324036 B CN 110324036B CN 201810265465 A CN201810265465 A CN 201810265465A CN 110324036 B CN110324036 B CN 110324036B
Authority
CN
China
Prior art keywords
signal
clock
coupled
data recovery
recovery circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810265465.8A
Other languages
Chinese (zh)
Other versions
CN110324036A (en
Inventor
王建中
翁孟泽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to CN201810265465.8A priority Critical patent/CN110324036B/en
Publication of CN110324036A publication Critical patent/CN110324036A/en
Application granted granted Critical
Publication of CN110324036B publication Critical patent/CN110324036B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

A clock and data recovery circuit comprises a first phase detector, a first charge pump, a first voltage controlled oscillator and an auxiliary module, wherein the auxiliary module comprises an auxiliary clock generator for generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, for comparing the phases of the auxiliary clock signal and a first clock signal output by the first voltage-controlled oscillator; and a multiplexing selection unit for outputting a multiplexing output signal to the first charge pump according to a selection signal.

Description

Clock and data recovery circuit
Technical Field
The present invention relates to a clock and data recovery circuit, and more particularly, to a clock and data recovery circuit capable of preventing a lock release.
Background
Due to the rapid development of the process technology, the operation speed of the integrated circuit is greatly increased. In high-speed transmission communication systems, clock and Data Recovery (CDR) circuits are often used to ensure that the transmitted input Data can be correctly read. The clock and data recovery circuit needs to sample the data signal at a time corresponding to the rising edge or the falling edge of the data signal transmitted from the transmission end (i.e. the time of the data signal from 0 to 1 or from 1 to 0, or referred to as transition time) for correct phase and frequency tracking operation, and the phase/frequency tracking capability of the clock and data recovery circuit depends on the stability of the data signal and the occurrence of transition events continuously.
However, for a specific communication system application, the transmitter may transmit a data signal with a duration of 1 or a duration of 0, in which case the data signal may not transition for a long time, and the frequency of the clock signal output by the clock and data recovery circuit is gradually unlocked (Lock).
Disclosure of Invention
It is therefore a primary objective of the claimed invention to provide a clock and data recovery circuit that prevents the lock-out, so as to improve the drawbacks of the prior art.
The invention discloses a clock and data recovery circuit, comprising a first phase detector for comparing the phase of a data signal with the phase of a first clock signal to output a first output signal, wherein the first output signal indicates that the data signal leads or lags the phase of the first clock signal; an auxiliary module including an auxiliary clock generator for generating an auxiliary clock signal; a second phase detector, coupled to the auxiliary clock generator, for comparing phases of the auxiliary clock signal and the first clock signal to output a second output signal, wherein the second output signal indicates that the auxiliary clock signal leads or delays the phase of the first clock signal; and a multiplexing selection unit, coupled to the first phase detector and the second phase detector, for outputting a multiplexing output signal according to a selection signal; a first charge pump, coupled to the multiplexing selection unit, for outputting a control signal according to the multiplexing output signal; and a first voltage controlled oscillator coupled to the first charge pump for generating the first clock signal according to the control signal.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a block diagram of a clock and data recovery circuit according to an embodiment of the present invention.
FIG. 2 is a waveform diagram of a plurality of signals according to an embodiment of the present invention.
FIG. 3 is a block diagram of a phase detector according to an embodiment of the present invention.
FIG. 4 is a block diagram of a phase detector according to an embodiment of the present invention.
FIG. 5 is a block diagram of a multiplexing selection unit according to an embodiment of the invention.
FIG. 6 is a circuit diagram of a charge pump according to an embodiment of the present invention.
FIG. 7 is a circuit diagram of an auxiliary clock generator according to an embodiment of the present invention.
FIG. 8 is a block diagram of a clock and data recovery circuit according to an embodiment of the present invention.
FIG. 9 is a block diagram of a clock and data recovery circuit according to an embodiment of the present invention.
Description of the symbols:
1. 8, 9 clock and data recovery circuit
10a, 10b, 30a, 30b phase detector
11. 71 auxiliary clock generator
12. Auxiliary module
13. 33, 73 multiplex selection unit
14. 34, 82, 92 charge pump
16. 75 voltage controlled oscillator
33U, 33D multiplexer
72. 81 phase frequency detector
74. 83 low pass filter
76. 84 frequency divider
91. Frequency detector
C CP Capacitor with a capacitor element
CK _ AX, CK _ CDR, CK _ IN clock signals
CK _ D frequency-dividing signal
D a 、D b DN down signal
DF1a, DF2a, DF1b, DF2b delay unit
DS1, DS2, DS3, DS4 delayed signals
DT data signals
O1, O2, OMX output signals
Q1, Q2 transistor
S1, S2 switch
SEL select signal
T 1 、T 2 Time
U a 、U b UP rising signal
Vcc positive voltage
VCTL control signal
XOG1, XOG, XOG, XOG XOR gate
Detailed Description
FIG. 1 is a block diagram of a Clock and Data Recovery (CDR) circuit 1 according to an embodiment of the present invention. The clock and data recovery circuit 1 includes a Phase Detector (Phase Detector) 10a, an auxiliary module 12, a Charge Pump (Charge Pump) 14, and a Voltage Controlled Oscillator (VCO) 16. The phase detector 10a receives a data signal DT and a first clock signal CK _ CDR, and compares phases of the data signal DT and the first clock signal CK _ CDR to output a first output signal O1. The charge pump 14 is coupled to the phase detector 10a for outputting a control signal VCTL. The vco 16 is coupled to the charge pump 14 for generating the first clock signal CK _ CDR according to the control signal VCTL. When the charge pump 14 receives the first output signal O1 and the first output signal O1 represents that the phase of the first clock signal CK _ CDR lags behind the phase of the data signal DT, the charge pump 14 increases the voltage or amplitude of the output control signal VCTL thereof, so that the frequency of the first clock signal CK _ CDR generated by the vco 16 increases; when the charge pump 14 receives the first output signal O1 and the first output signal O1 represents that the phase of the first clock signal CK _ CDR leads the phase of the data signal DT, the charge pump 14 decreases the voltage or amplitude of the control signal VCTL outputted therefrom, so that the frequency of the first clock signal CK _ CDR generated by the vco 16 decreases.
In this way, the clock and data recovery circuit 1 can lock the frequency of the first clock signal CK _ CDR to be related to the Symbol Rate (Symbol Rate) or Bit Rate (Bit Rate) of the data signal DT, wherein the Symbol Rate (Bit Rate) is the reciprocal of a Symbol (Bit) interval in the data signal DT. For example, the frequency of the first clock signal CK _ CDR may be an integer multiple (e.g., 2 times) of the symbol rate (or bit rate) of the data signal DT.
When the data signal DT is 0 for a long time (i.e., the data signal DT is 0 for a plurality of consecutive Clock intervals (Clock cycles)) or 1 for a long time (i.e., the data signal DT is 1 for a plurality of consecutive Clock intervals), the Clock and data recovery circuit may be unlocked (Lock). That is, when the data signal DT is 0 for a long time or 1 for a long time, the clock and data recovery circuit 1 may not be able to lock the frequency of the first clock signal CK _ CDR to the symbol rate/bit rate of the data signal DT, i.e. the frequency of the first clock signal CK _ CDR and the symbol rate/bit rate of the data signal DT gradually lose correlation. In order to avoid the lock-out phenomenon caused by the data signal DT being 0 for a long time or 1 for a long time, the clock and data recovery circuit 1 includes an auxiliary module 12 coupled between the phase detector 10a and the charge pump 14, wherein the auxiliary module 12 is used for providing an appropriate auxiliary clock signal to assist the clock and data recovery circuit 1 when the data signal DT is 0 for a long time or 1 for a long time so as not to lock-out.
Specifically, the auxiliary module 12 includes an auxiliary clock generator 11, a phase detector 10b and a multiplexing selection unit 13. The auxiliary clock generator 11 is used for generating an auxiliary clock signal CK _ AX. The phase detector 10b is coupled to the auxiliary clock generator 11 and the vco 16 for receiving the auxiliary clock signal CK _ AX and the first clock signal CK _ CDR, and the phase detector 10b is similar to the phase detector 10a for comparing phases of the auxiliary clock signal CK _ AX and the first clock signal CK _ CDR to output a second output signal O2, wherein the second output signal O2 represents that the phase of the auxiliary clock signal CK _ AX leads the phase of the first clock signal CK _ CDR, or that the phase of the auxiliary clock signal CK _ AX lags the phase of the first clock signal CK _ CDR. When the charge pump 14 receives the second output signal O2 and the second output signal O2 represents that the phase of the first clock signal CK _ CDR lags the phase of the auxiliary clock signal CK _ AX, the charge pump 14 increases the voltage or amplitude of the output control signal VCTL thereof, such that the frequency of the first clock signal CK _ CDR generated by the vco 16 increases; when the charge pump 14 receives the second output signal O2 and the second output signal O2 represents that the phase of the first clock signal CK _ CDR leads the phase of the auxiliary clock signal CK _ AX, the charge pump 14 decreases the voltage or amplitude of the control signal VCTL output by the charge pump, so that the frequency of the first clock signal CK _ CDR generated by the vco 16 decreases.
The multiplexing selection unit 13 is coupled to the phase detectors 10a and 10b and an external control circuit (not shown in fig. 1), and the multiplexing selection unit 13 receives a selection signal SEL from the external control circuit to selectively output a multiplexing output signal OMX as the first output signal O1 or the second output signal O2. When the external control circuit knows in advance that the data signal DT has a long time of 0 or a long time of 1 at a specific time, the external control circuit may generate the selection signal SEL to control the multiplexing selection unit 13 to output the multiplexing output signal OMX as the second output signal O2 to the charge pump 14, at this time, the charge pump 14 outputs the control signal VCTL according to the second output signal O2, and the voltage controlled oscillator 16 generates the first clock signal CK _ CDR according to the control signal VCTL associated with the second output signal O2. On the contrary, when the data signal DT has a stable and continuous transition state, the multiplexed output signal OMX is the first output signal O1 to the charge pump 14.
Referring to fig. 2, fig. 2 is a waveform diagram of a data signal DT, an auxiliary clock signal CK _ AX, a first clock signal CK _ CDR, and a selection signal SEL according to an embodiment of the invention. In the general case (corresponding to the time interval T) 1 ) The clock and data recovery circuit 1 treats the data signal DT as the target of frequency locking, and the selection signal SEL generated by the external control circuit is in the time interval T 1 The multiplexing selection unit 13 is controlled to output the multiplexing output signal OMX as the first output signal O1 to the charge pump 14, i.e. to lock the frequency of the first clock signal CK _ CDR so as to be related to the data signal DT. When the external control circuit determines in advance that the data signal DT has a long time of 0 or a long time of 1 at a specific time (e.g. during the time interval T) 2 ) The clock and data recovery circuit 1 regards the auxiliary clock signal CK _ AX as the target of frequency locking, and the selection signal SEL generated by the external control circuit is in the time interval T 2 The multiplexing selection unit 13 is controlled to output the multiplexed output signal OMX as the second output signal O2 to the charge pump 14, i.e. the frequency of the first clock signal CK _ CDR is locked and related to the auxiliary clock signal CK _ AX, such that the first clock signal CK _ CDR is in the time interval T 2 The lock can not be unlocked.
The phase detectors 10a, 10b are not limited to a particular circuit configuration, for example, the phase detectors 10a, 10b may be implemented using Hogge phase detectors, which are well known to those skilled in the art and are briefly described below.
Please refer to fig. 3 and fig. 4, wherein fig. 3 and fig. 4 are respectivelyA block diagram of a phase detector 30a and a phase detector 30b according to an embodiment of the present invention is shown. Phase detectors 30a and 30b are used to implement phase detectors 10a and 10b, respectively. Phase detector 30a includes delay elements DF1a, DF2a and Exclusive OR gates (Exclusive OR Gate) XOG, XOG, and phase detector 30b includes delay elements DF1b, DF2b and Exclusive OR gates XOG, XOG, wherein delay elements DF1a, DF2a, DF1b, DF2b may be D-flip-flops (D flip-flops). The delay unit DF1a receives the data signal DT and the first clock signal CK _ CDR to generate a delayed signal DS3, the delay unit DF2a receives the delayed signal DS3 and the first clock signal CK _ CDR to generate a delayed signal DS4, the delay unit DF1b receives the auxiliary clock signal CK _ AX and the first clock signal CK _ CDR to generate a delayed signal DS1, and the delay unit DF2b receives the first delayed signal DS1 and the first clock signal CK _ CDR to generate a delayed signal DS2. The XOR gate XOG XORs the auxiliary clock signal CK _ AX and the delay signal DS1 to generate a rising signal U b The XOR gate XOG XORs the delay signal DS1 and the delay signal DS2 to generate a down signal D b The XOR gate XOG XORs the data signal DT and the first delay signal DS3 to generate a rising signal U a XOR gate XOG XORs delay signal DS3 and delay signal DS4 to generate a falling signal D a . Wherein the rising signal U a And a falling signal D a Forming a first output signal O1, a rising signal U b And a falling signal D b Forming a second output signal O2, i.e. the first output signal O1 is formed by the rising signal U a And a falling signal D a The second output signal O2 is composed of a rising signal U b And a falling signal D b Thereby forming the structure.
In addition, in order to respond to the rising signal U generated by the phase detector 30a a And a falling signal D a (first output signal O1) and rising signal U generated by phase detector 30b b And a falling signal D b (second output signal O2), the multiplexer selection unit 13 may include two multiplexers. Referring to fig. 5, fig. 5 is a block diagram of the phase detectors 30a and 30b, the multiplexing selection unit 33 and the charge pump 34, wherein the multiplexing selection is performedThe selection unit 33 and the charge pump 34 can be used to realize the multiplexing selection unit 13 and the charge pump 14, respectively. As shown in fig. 5, the multiplexer selection unit 33 includes multiplexers 33U and 33D. The multiplexer 33U receives the rising signal U a And a rising signal U b For outputting a rising signal UP according to the selection signal SEL, the rising signal UP can be a rising signal U a Or up signal U b . The multiplexer 33D receives the down signal D a And a falling signal D b For outputting a falling signal DN according to the selection signal SEL, wherein the falling signal DN can be a falling signal D a Or a falling signal D b . The UP signal UP and the down signal DN form a multiplexing output signal OMX, which is composed of the UP signal UP and the down signal DN.
In addition, referring to fig. 6, fig. 6 is a circuit diagram of the charge pump 34, wherein fig. 6a is a circuit diagram of the charge pump 34, and fig. 6b is a specific circuit diagram of the charge pump 34. In fig. 6a, the charge pump 34 includes switches S1 and S2 and a capacitor C CP One end of the switch S1 receives a positive voltage Vcc and the other end is coupled to the capacitor C CP One end of the switch S2 is grounded (i.e. receives a ground voltage) and the other end is coupled to the capacitor C CP Capacitor C CP For outputting the control signal VCTL. The switch S1 is controlled by a rising signal UP and the switch S2 is controlled by a falling signal DN. As shown in fig. 6b, the switches S1 and S2 can be implemented by transistors Q1 and Q2, respectively. Additional details are known to those skilled in the art and will not be described herein.
The auxiliary clock generator 11 is not limited to a specific circuit structure, and may be a Free Run Oscillator (FRO) or an Oscillator of a Phase Locked Loop (PLL) like structure. Referring to fig. 7, fig. 7 is a circuit diagram of an auxiliary clock generator 71 according to an embodiment of the present invention, wherein the auxiliary clock generator 71 can be used to implement the auxiliary clock generator 11. As shown in fig. 7, the auxiliary clock generator 71 includes a Phase Frequency Detector (PFD) 72, a charge pump 73, a low pass filter 74, a voltage controlled oscillator 75 and a Frequency divider 76. The vco 75 outputs the auxiliary clock signal CK _ AX, the frequency divider 76 generates a frequency divided signal CK _ D according to the auxiliary clock signal CK _ AX, and the pfd 72 receives an input clock signal CK _ IN and compares the phases and frequencies of the input clock signal CK _ IN and the frequency divided signal CK _ D to generate an output signal thereof to the charge pump 73. The remaining details are known to those skilled in the art and will not be described in detail herein.
It should be noted that the foregoing embodiments are provided to illustrate the concept of the present invention, and those skilled in the art should be able to make various modifications without departing from the scope of the invention. For example, the auxiliary module 12 can be applied to a clock and data recovery circuit capable of receiving an external reference clock signal or a clock and data recovery circuit capable of performing frequency detection, please refer to fig. 8 and 9, where fig. 8 and 9 are block diagrams of a clock and data recovery circuit 8 and a clock and data recovery circuit 9, respectively, according to an embodiment of the present invention. The clock and data recovery circuit 8 is similar to the clock and data recovery circuit 1, so the same elements are denoted by the same symbols, and unlike the clock and data recovery circuit 1, the clock and data recovery circuit 8 further includes a phase frequency detector 81, a charge pump 82, a low pass filter 83, and a frequency divider 84, and the connection relationship between the elements is shown in fig. 8. The phase frequency detector 81 is coupled to the vco 16, and receives a reference clock signal CK _ REF from the outside, and the clock and data recovery circuit 8 can lock the frequency and phase of the reference clock signal CK _ REF from the outside by using the phase frequency detector 81. Clock and data recovery circuit 90 is similar to clock and data recovery circuit 1/8, so like elements follow the same sign. Unlike the clock and data recovery circuit 1/8, the clock and data recovery circuit 9 further includes a Frequency Detector (FD) 91 and a charge pump 92, and the connection relationship between the elements is shown in fig. 9. The frequency detector 91 is coupled to the vco 16, and the clock and data recovery circuit 9 can first lock the frequency of the data signal DT by the frequency detector 91 and then lock the phase of the data signal DT by the phase detector 10 a. Details of clock and data recovery circuits capable of receiving and locking to an external reference clock signal, clock and data recovery circuits capable of performing frequency detection, and (phase) frequency detectors are well known to those skilled in the art and will not be described herein.
Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (11)

1. A clock and data recovery circuit comprising:
a first phase detector for comparing phases of a data signal and a first clock signal to output a first output signal indicating whether the data signal leads or lags the phase of the first clock signal;
an auxiliary module comprising:
an auxiliary clock generator for generating an auxiliary clock signal;
a second phase detector, coupled to the auxiliary clock generator, for comparing phases of the auxiliary clock signal and the first clock signal to output a second output signal, wherein the second output signal indicates that the auxiliary clock signal leads or lags the phase of the first clock signal; and
a multiplexing selection unit coupled to the first phase detector and the second phase detector for outputting a multiplexing output signal according to a selection signal;
a first charge pump, coupled to the multiplexing selection unit, for outputting a control signal according to the multiplexing output signal; and
a first voltage controlled oscillator coupled to the first charge pump for generating the first clock signal according to the control signal;
wherein the auxiliary clock generator comprises:
a phase frequency detector receiving an input clock signal;
a second charge pump coupled to the phase frequency detector; and
a second voltage controlled oscillator coupled between the second charge pump and the phase frequency detector for generating the auxiliary clock signal.
2. The clock and data recovery circuit of claim 1, wherein the second phase detector comprises:
a first delay unit for receiving the auxiliary clock signal and the first clock signal to generate a first delay signal;
a second delay unit coupled to the first delay unit for receiving the first delayed signal and the first clock signal to generate a second delayed signal;
a first XOR gate for performing XOR operation on the auxiliary clock signal and the first delay signal to generate a first rising signal; and
a second XOR gate for performing XOR operation on the first delayed signal and the second delayed signal to generate a first down signal;
wherein the first rising signal and the first falling signal form the second output signal.
3. The clock and data recovery circuit of claim 2, wherein the first phase detector comprises:
a third delay unit for receiving the data signal and the first clock signal to generate a third delayed signal;
a fourth delay unit, coupled to the third delay unit, for receiving the third delayed signal and the first clock signal to generate a fourth delayed signal;
a third XOR gate for performing XOR operation on the data signal and the third delayed signal to generate a second rising signal; and
a fourth XOR gate for performing XOR operation on the third delayed signal and the fourth delayed signal to generate a second falling signal;
wherein the second rising signal and the second falling signal form the first output signal.
4. The clock and data recovery circuit of claim 3, wherein the multiplexing selection unit comprises:
a first multiplexer for receiving the first rising signal and the second rising signal and outputting a third rising signal according to the selection signal; and
a second multiplexer for receiving the first and second falling signals and outputting a third falling signal according to the selection signal;
wherein the third rising signal and the third falling signal form the multiplexed output signal.
5. The clock and data recovery circuit of claim 4, wherein the first charge pump comprises:
a capacitor for outputting the control signal;
a first switch, one end of which receives a first voltage and the other end of which is coupled to the capacitor, the first switch being controlled by the third rising signal; and
and a second switch, one end of which receives a second voltage and the other end of which is coupled to the capacitor, wherein the first switch is controlled by the third falling signal.
6. The clock and data recovery circuit of claim 5, wherein the first switch is a first transistor, the second switch is a second transistor, the first voltage is a positive voltage, and the second voltage is a ground voltage.
7. The clock and data recovery circuit of claim 1, wherein the auxiliary clock generator further comprises:
a frequency divider coupled between the second VCO and the PFD for generating a frequency divided signal according to the auxiliary clock signal;
wherein the phase frequency detector receives the frequency divided signal.
8. The clock and data recovery circuit of claim 1, wherein the auxiliary clock generator further comprises:
a low pass filter coupled between the second charge pump and the second voltage controlled oscillator.
9. The clock and data recovery circuit of claim 1 wherein the multiplexing selection unit is coupled to a control circuit, the control circuit generating the selection signal.
10. The clock and data recovery circuit of claim 1, further comprising a phase frequency detector coupled to the first voltage controlled oscillator and receiving a reference clock signal.
11. The clock and data recovery circuit of claim 1, further comprising a phase frequency detector coupled to the first voltage controlled oscillator.
CN201810265465.8A 2018-03-28 2018-03-28 Clock and data recovery circuit Active CN110324036B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810265465.8A CN110324036B (en) 2018-03-28 2018-03-28 Clock and data recovery circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810265465.8A CN110324036B (en) 2018-03-28 2018-03-28 Clock and data recovery circuit

Publications (2)

Publication Number Publication Date
CN110324036A CN110324036A (en) 2019-10-11
CN110324036B true CN110324036B (en) 2023-04-14

Family

ID=68109992

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810265465.8A Active CN110324036B (en) 2018-03-28 2018-03-28 Clock and data recovery circuit

Country Status (1)

Country Link
CN (1) CN110324036B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11095296B2 (en) 2018-09-07 2021-08-17 Innophase, Inc. Phase modulator having fractional sample interval timing skew for frequency control input
WO2021178147A1 (en) * 2020-03-03 2021-09-10 Innophase, Inc. Phase modulator having fractional sample interval timing skew for frequency control input
TWI714507B (en) * 2020-05-20 2020-12-21 智原科技股份有限公司 Clock data recovery circuit
US11088818B1 (en) 2020-07-01 2021-08-10 Novatek Microelectronics Corp. Receiver and transmitter for high speed data and low speed command signal transmissions
TWI768690B (en) * 2021-01-29 2022-06-21 瑞昱半導體股份有限公司 Reference-less clock and data recovery (cdr) device and method thereof
CN113285711B (en) * 2021-04-30 2023-03-24 山东英信计算机技术有限公司 Return circuit and chip

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211741B1 (en) * 1998-10-16 2001-04-03 Cypress Semiconductor Corp. Clock and data recovery PLL based on parallel architecture
CN1485986A (en) * 2002-09-24 2004-03-31 联发科技股份有限公司 Method and apparatus for reducing phase jitter in clock recovery system
US6943599B2 (en) * 2003-12-10 2005-09-13 International Business Machines Corporation Methods and arrangements for a low power phase-locked loop
US7983361B2 (en) * 2007-04-26 2011-07-19 Mediatek Inc. Clock data recovery circuit
US8588358B2 (en) * 2011-03-11 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Clock and data recovery using LC voltage controlled oscillator and delay locked loop
KR101593678B1 (en) * 2014-05-26 2016-02-16 고려대학교 산학협력단 Circuit and method for clock and data recovery

Also Published As

Publication number Publication date
CN110324036A (en) 2019-10-11

Similar Documents

Publication Publication Date Title
CN110324036B (en) Clock and data recovery circuit
US7826583B2 (en) Clock data recovery apparatus
US6346861B2 (en) Phase locked loop with high-speed locking characteristic
US8442178B2 (en) Linear phase detector and clock/data recovery circuit thereof
USRE40939E1 (en) Multi-phase locked loop for data recovery
US5734301A (en) Dual phase-locked loop clock synthesizer
KR101020513B1 (en) The lock detector circuit and lock detecting method
US8368439B2 (en) Phase locked loop circuit, method of detecting lock, and system having the circuit
US10615804B2 (en) Clock and data recovery circuit
JP3320353B2 (en) Variable speed phase locked loop system and method
KR100362841B1 (en) High-frequency phase locked loop circuit
EP2359469B1 (en) A phase frequency detector
KR100400043B1 (en) Data recovery circuit and method thereof
US10530563B2 (en) Clock synchronization device
JP3755663B2 (en) Semiconductor integrated circuit
US7570093B1 (en) Delay-locked loop and a delay-locked loop detector
US6987406B1 (en) Wide frequency range phase-locked loop circuit with phase difference
US20070081619A1 (en) Clock generator and clock recovery circuit utilizing the same
US11115033B1 (en) Speed-up charge pump and phase-locked loop and method for operating the same
KR100261294B1 (en) High speed nrz data recovery apparatus
US6259278B1 (en) Phase detector
US7598816B2 (en) Phase lock loop circuit with delaying phase frequency comparson output signals
US7109806B2 (en) Device and method for detecting phase difference and PLL using the same
CN111756370A (en) Semiconductor device with a plurality of semiconductor chips
US20040223574A1 (en) Phase frequency detector used in digital PLL system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20191223

Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China

Applicant after: MEDIATEK Inc.

Address before: 1/2, 4th floor, 26 Taiyuan Street, Zhubei City, Hsinchu County, Taiwan, China

Applicant before: MSTAR SEMICONDUCTOR Inc.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant