CN1485986A - Method and apparatus for reducing phase jitter in clock recovery system - Google Patents
Method and apparatus for reducing phase jitter in clock recovery system Download PDFInfo
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- CN1485986A CN1485986A CNA021323682A CN02132368A CN1485986A CN 1485986 A CN1485986 A CN 1485986A CN A021323682 A CNA021323682 A CN A021323682A CN 02132368 A CN02132368 A CN 02132368A CN 1485986 A CN1485986 A CN 1485986A
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Abstract
The invention provides a method to reduce phase shake in clock recovering system and the equipment. The clock recovering system has a phase detector to detect the phase difference between an input signal and a clock signal output by a voltage controlled oscillator, generates a rising pulse and a descending pulse according to the phase difference, and uses the two pulses to generate a control voltage of the voltage controlled oscillator. It uses a time delay component to make the two pulses overlap in the time field, to eliminate the ripple generated on the control voltage, so as to prevent the clock signal from producing phase shake.
Description
Technical field
The present invention relates to a kind of method and device thereof that reduces phase jitter in the clock recovery system, particularly a kind of by eliminating the ripple on the control voltage of voltage-controlled oscillator, produce the method and the device of phase jitter to avoid voltage controlled oscillator to change too fast.
Background technology
Phase-locked loop (Phase Locked Loop) generally is used as the control of frequency, and it generally can be used as frequency multiplier (Multiplier), demodulator (Demodulator), trajectory track generator (Tracking Generator), clock recovery system application such as (Clock Recovery Circuit).And have the CD media of utilizing the high power regeneration rate recently, as CD-ROM, DVD etc., more utilize clock recovery system that data are done synchronized regeneration (regeneration).As shown in Figure 1, be a typical clock recovery system 1, it comprises phase detectors 11, electric charge drawing device 12, loop filter 13, voltage controlled oscillator 14 and the frequency divider 15 that is connected to form a loop in regular turn.One input signal DATA is produced and clock signal clk behind frequency divider 15 frequency divisions is imported simultaneously in these phase detectors 11 and done bit comparison mutually by voltage controlled oscillator 14 with one, and produces a rising pulse and falling pulse according to both phase difference t and control this electric charge drawing device 12 and produce an electric current I
Cp, this electric current I
CpProduce control voltage V through loop filter 13 integrations
Ct, this control voltage V
CtThe frequency that control voltage controlled oscillator 14 is sent feeds back to phase detectors 11 again through the clock signal clk that frequency divider 15 frequency divisions produce.Thus, clock signal clk and input signal DATA are reached synchronously, to utilize this clock signal clk to the input signal DATA regeneration of taking a sample.Therefore, when the leading input signal IN of the phase place of clock signal clk, the rising pulse UP that phase detectors 11 are can output one width narrower or the falling pulse DN of wider width, control electric charge drawing device 12 produces negative electric current I
Cp, make through loop filter 13 integrations and produce less control voltage V
Ct, control voltage controlled oscillator 14 is slack-off and reduce the frequency of clock signal clk.And when clock signal clk fell behind input signal DATA, the rising pulse UP of a broad or narrower falling pulse DN are promptly produced with control electric charge drawing device 12 produced positive electric current I
Cp, to increase control voltage V
CtControl voltage controlled oscillator 14 pick up speeds also improve the frequency of clock signal clk.
But, as shown in Figure 2, because typical phase detectors 11 output rising earlier pulse UP then exports falling pulse DN again, that is rising pulse UP and falling pulse DN be not output simultaneously, and this phenomenon causes the control voltage V that produces according to rising pulse UP and falling pulse DN
CtThe integration gradually along with the appearance in regular turn of rising pulse UP and falling pulse DN, so that at control voltage V
CtGo up except the voltage Δ V of reality, ripple (ripple) V that is not required also occurred by phase difference t generation
r, and these ripples V
rEven just a very little phase difference also can produce, it not only can order about the phase place that voltage controlled oscillator 14 constantly removes to change clock signal clk, cause the phase jitter (jitter) of clock signal clk, and cause the rising of clock signal clk frequency or descend too fast, when causing adopting clock signal clk to go input signal DATA taken a sample, can cause the data misjudgment because of the sampling point skew, and these phase places of shaking up and down can produce corresponding ripple along with transform strike slip boundary (transitionedge) frequency of occurrences of input signal (data) DATA, so will cause shake associated with the data (datadependent jitter).
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of method and device thereof that reduces phase jitter in the clock recovery system, utilize the phase jitter of eliminating the ripple that on control voltage, produces and reducing voltage controlled oscillator generation in the clock recovery system.
So, the invention provides a kind of method that reduces phase jitter in the clock recovery system, this clock recovery system comprises the phase detectors that are connected to form a loop, the electric charge drawing device, loop filter and voltage controlled oscillator, wherein these phase detectors detect the phase place of the clock signal of an input signal and the output of this voltage controlled oscillator, and export a rising pulse and this electric charge drawing device is controlled in a decline pulse according to both phase differences, make and produce an electric current according to this for this loop filter generation one this voltage controlled oscillator of control voltage control, make output and this input signal clock signal synchronous, this method is: make this rising pulse and falling pulse overlap, make during both overlap, the electric charge drawing device can not flow to this loop filter according to the ascending current and the drop-out current of this rising pulse and falling pulse generation, thus, the ripple that elimination produces on control voltage, and then the phase jitter on the reduction clock signal.
Moreover, the present invention realizes the clock recovery system of said method, comprise the phase detectors, electric charge drawing device, loop filter and the voltage controlled oscillator that are connected to form a loop in regular turn, wherein these phase detectors detect an input signal and a phase place by the clock signal of this voltage controlled oscillator output, and export a rising pulse and a decline pulse according to both phase differences, control this electric charge drawing device and produce an electric current, make to produce a control voltage control this voltage controlled oscillator output and this input signal clock signal synchronous to this loop filter.Particularly, this clock recovery system also comprises the time delay assembly, this time delay assembly is connected between these phase detectors and the electric charge drawing device, overlap on time domain in order to control this rising pulse and falling pulse, make during both overlap, the electric charge drawing device can not flow to this loop filter according to the ascending current and the drop-out current of this rising pulse and falling pulse generation, eliminate the ripple that on control voltage, produces thus, and then reduce the phase jitter on the clock signal because rising pulse and falling pulse do not overlap.
Description of drawings
Further feature of the present invention and advantage, it is clearer to become in below with reference to the accompanying drawing detailed description of preferred embodiments, wherein:
Fig. 1 is the circuit block diagram of a typical clock recovery system;
Fig. 2 is rising pulse and the waveform of falling pulse and the waveform that this loop filter exports control voltage of voltage-controlled oscillator to of the sequential of input signal among Fig. 1 and clock signal and waveform, this phase detectors output, shows wherein that rising pulse and falling pulse are separated from each other and less than overlapping;
Fig. 3 is the circuit block diagram that the present invention reduces a preferred embodiment of the method for phase jitter in the clock recovery system and device thereof; And
Fig. 4 is the waveform that the rising pulse of the sequential of input signal among Fig. 3 and clock signal and waveform, this phase detectors output and falling pulse waveform and this loop filter export control voltage of voltage-controlled oscillator to, shows that wherein this rising pulse UP is delayed a period of time Td and overlaps with falling pulse DN.
Embodiment
At first the reference number in the accompanying drawing is described: 2--clock recovery system, 21--phase detectors, 22--electric charge drawing device, the 23--loop filter, the 24--voltage controlled oscillator, 25--frequency divider, 26--time delay assembly, UP--rising pulse, the DN--falling pulse, DEL_UP--postpones rising pulse, DATA--input signal, the CLK--clock signal, I
CP--electric current, V
Ct--control voltage, Δ t--phase difference, Td--time of delay, Δ v--voltage.
Consult shown in Figure 3, it is the circuit block diagram that the present invention reduces a preferred embodiment of the method for phase jitter in the clock recovery system and device thereof, and this clock recovery system 2, as aforementioned, consist essentially of the phase detectors 21 that are connected to form a closed loop in regular turn, electric charge drawing device 22, loop filter 23, a voltage controlled oscillator (VCO) 24 and a frequency divider 25, and clock recovery system 2 is for input signal DATA input, in order to produce and its clock signal synchronous CLK, to utilize the sampled signal of this clock signal clk as input signal DATA according to this input signal DATA.Therefore, in conjunction with shown in Figure 4, at first input signal DATA is imported in the phase detectors 21, make voltage controlled oscillator 24 produce an initial clock signal clk relatively, this clock signal clk and input signal DATA are not synchronous, so, for clock signal clk and input signal DATA are obtained synchronously, clock signal clk is fed back in the phase detectors 21 and compares with input signal DATA, and obtaining a phase difference t, phase detectors 21 produce a rising pulse UP according to this phase difference t and a decline pulsed D N goes to control electric charge drawing device 22 generation electric current I
Cp(wherein comprising an ascending current that produces by rising pulse UP and a decline electric current that produces by falling pulse DN), make control loop filter 23 produce control voltage V relatively
CtThe output frequency of control voltage controlled oscillator 24.And because the characteristic of typical phase detectors 21, be rising edge or trailing edge this rising pulse of generation earlier UP according to input signal DATA, and then produce this falling pulse DN according to the rising edge of clock signal clk, and falling pulse DN fixes, its pulse duration is the period T of a clock signal clk, and is above-mentioned at control voltage V but this phenomenon but can cause
CtThe situation of last generation ripple (ripple) causes voltage controlled oscillator 14 output frequencies to change, and the situation that causes the phase jitter of clock signal clk and influence input signal DATA sampling correctness takes place.
Therefore, in order to eliminate above-mentioned ripple phenomenon, make not reason ripple and changing of voltage controlled oscillator 14 output frequencies, so that influence the phase change of clock signal clk, the practice of the present invention is: between the rising pulse UP output of the phase detectors 21 of this clock recovery system 2 and electric charge drawing device 22 a time Delay Element 26 is set more, UP postpones a period of time Td backward with the rising pulse, and overlaps on time domain with falling pulse DN.And in the present embodiment, because the pulse duration of falling pulse DN is a clock cycle T, make rising pulse UP just postpone a clock cycle T so this time delay assembly 26 can be set for, be Td=T time of delay, so, have maximum overlapping area between rising pulsed D EL_UP after the delay and the falling pulse DN, and, rising pulsed D EL_UP and the phase difference between the falling pulse DN after the delay also just equal the phase difference t of input signal DATA and clock signal clk, and the reason (nonoverlapping situation between pulse UP and the falling pulse DN promptly rises) that produces ripple is disappeared.Therefore, when rising pulsed D EL_UP after postponing and falling pulse DN input electric charge drawing device 22, because the rising pulsed D EL_UP after postponing and falling pulse DN overlap mutually during the ascending current and the drop-out current that are produced offset, therefore this during one electric charge drawing device 22 do not have electric current and export this loop filter 23 to, and only during the rising pulsed D EL_UP after the delay and falling pulse DN do not overlap, electric charge drawing device 22 just produces electric current I
CpExport loop filter 23 to, suppress the generation of ripple thus, therefore, the control voltage V that loop filter 23 produces
CtUpward a mild voltage Δ V who rises will only can occur, and not have the generation of ripple, and this voltage Δ V is exactly the voltage that is used for controlling voltage controlled oscillator 24 according to the corresponding generation of phase difference t institute of reality.
So, according to said method, rising pulse UP is suitably postponed a period of time to overlap as much as possible with falling pulse DN backward, make electric charge drawing device 22 during both overlap, can not output current to loop filter 23, and can avoid and reduce control voltage V
CtThe generation of last ripple, and then make controlled voltage V
CtThe voltage controlled oscillator 24 of control is reason control voltage V not
CtGo up the ripple that constantly occurs, cause output clock signal clk phase change and produce shake, and can be used to input signal DATA is taken a sample and interpretation accurately.
The above, be the preferred embodiments of the present invention, can not be in order to limiting scope of the invention process, all simple equivalent that claims and description are done according to the present invention change and revise, and all should fall in the scope that claim of the present invention covers.
Claims (24)
1. method that reduces phase jitter in the clock recovery system, this clock recovery system comprises the phase detectors that are connected to form a loop in regular turn, the electric charge drawing device, loop filter and voltage controlled oscillator, wherein these phase detectors detect an input signal and phase place by the clock signal of this voltage controlled oscillator output, and export a rising pulse and a decline pulse according to both phase differences and control this electric charge drawing device and produce an electric current to this loop filter, make to produce control voltage to control this voltage controlled oscillator output and this input signal clock signal synchronous, this method comprises:
Make this rising pulse and falling pulse on time domain, overlap, make this electric charge drawing device during this overlapping, can not export an ascending current corresponding and a decline electric current to this loop filter with this rising pulse and this falling pulse;
Thus, eliminate the ripple that produces because this rising pulse and this falling pulse do not overlap on this control voltage, the feasible unlikely generation phase jitter of this clock signal that produced by voltage-controlled this voltage controlled oscillator of this control.
2. the method for phase jitter in the reduction clock recovery system according to claim 1, wherein should the rising pulse and the area that on time domain, overlaps of this falling pulse reach maximum.
3. the method for phase jitter in the reduction clock recovery system according to claim 1 wherein makes that leading pulse daley a period of time of phase place among this rising pulse and this falling pulse to overlap on time domain with the another one pulse and to have maximum overlapping area.
4. the method for phase jitter in the reduction clock recovery system according to claim 1, wherein these phase detectors are to produce this rising pulse earlier, produce this falling pulse again, therefore, make this rising pulse daley a period of time to overlap with this falling pulse, and should time of delay length be the pulse duration of this falling pulse, make to have maximum overlapping area between this rising pulse and this falling pulse.
5. the method for phase jitter in the reduction clock recovery system according to claim 4, wherein this falling pulse is fixing, and its pulse duration is the one-period of this clock signal.
6. reduce the method for phase jitter in the clock recovery system according to claim 1 or 5, wherein this input signal is a digital signal, and this clock signal produces according to this input signal.
7. method that reduces phase jitter in the clock recovery system, this clock recovery system comprises phase detectors and voltage controlled oscillator, these phase detectors are in order to detect an input signal and phase difference by the clock signal of this voltage controlled oscillator output, an and not rising pulse and a decline pulse of overlapping of generation according to this, and should the rising pulse and falling pulse in order to produce this control voltage of voltage-controlled oscillator of control, this method comprises:
Make this rising pulse and this falling pulse on time domain, overlap, make this electric charge drawing device during this overlapping, can not export an ascending current corresponding and a decline electric current to this loop filter with this rising pulse and this falling pulse;
Eliminate on this control voltage the ripple that does not overlap and produce because of this rising pulse and this falling pulse thus, make the unlikely generation phase jitter of this clock signal that produced by voltage-controlled this voltage controlled oscillator of this control.
8. the method for phase jitter in the reduction clock recovery system according to claim 7, wherein should the rising pulse and the area that on time domain, overlaps of this falling pulse reach maximum.
9. the method for phase jitter in the reduction clock recovery system according to claim 7 wherein makes that leading among this rising pulse and this falling pulse pulse daley a period of time to overlap on time domain with another pulse and to make both overlapping areas reach maximum.
10. the method for phase jitter in the reduction clock recovery system according to claim 7, wherein these phase detectors produce this rising pulse earlier, produce this falling pulse again, therefore, make this rising pulse daley a period of time to overlap with this falling pulse, and should time of delay length be the pulse duration of this falling pulse, make to have maximum overlapping area between this rising pulse and this falling pulse.
11. the method for phase jitter in the reduction clock recovery system according to claim 10, wherein this falling pulse is fixing, and its pulse duration is the one-period of this clock signal.
12. according to the method for phase jitter in claim 7 or the 11 described reduction clock recovery systems, wherein this input signal is a digital signal, and this clock signal produces according to this input signal.
13. device that reduces phase jitter in the clock recovery system, this clock recovery system comprises the phase detectors that are connected to form a loop in regular turn, the electric charge drawing device, loop filter and voltage controlled oscillator, wherein these phase detectors detect an input signal and phase place by the clock signal of this voltage controlled oscillator output, and produce an electric current to this loop filter to control this electric charge drawing device according to a rising pulse and the decline pulse that both phase difference output does not overlap, make to produce a control voltage control this voltage controlled oscillator output and this input signal clock signal synchronous; This device comprises:
The time delay assembly, be connected between these phase detectors and this electric charge drawing device, overlap on time domain in order to control this rising pulse and this falling pulse, make this electric charge drawing device during this overlapping, can not export an ascending current corresponding and a decline electric current to this loop filter with this rising pulse and this falling pulse, thus, eliminate the ripple that on this control voltage, produces because this rising pulse and this falling pulse do not overlap.
14. the device of phase jitter in the reduction clock recovery system according to claim 13, wherein this time delay assembly is controlled the area that this rising pulse and this falling pulse overlap and is reached maximum on time domain.
15. the device of phase jitter in the reduction clock recovery system according to claim 13, that leading pulse daley a period of time overlapped on time domain with another pulse with backwardness among wherein this time delay assembly was controlled this rising pulse and this falling pulse, and made both overlapping areas reach maximum.
16. the device of phase jitter in the reduction clock recovery system according to claim 13, wherein these phase detectors produce this rising pulse earlier, produce this falling pulse again, therefore, this time delay assembly system should rising pulse daley a period of time to overlap with this falling pulse, and should time of delay length be the pulse duration of this falling pulse, make to have maximum overlapping area between this rising pulse and this falling pulse.
17. the device of phase jitter in the reduction clock recovery system according to claim 16, wherein this falling pulse is fixing, and its pulse duration is a clock signal period.
18. according to the device of phase jitter in claim 13 or the 17 described reduction clock recovery systems, wherein this input signal is a digital signal, and this clock signal system produces according to this input signal.
19. clock recovery system, comprise the phase detectors, electric charge drawing device, loop filter and the voltage controlled oscillator that are connected to form a loop in regular turn, wherein these phase detectors detect an input signal and phase place by the clock signal of this voltage controlled oscillator output, and do not produce an electric current to this loop filter to control this electric charge drawing device according to a rising pulse and the decline pulse that both phase difference output overlaps, make to produce a control voltage control this voltage controlled oscillator output and this input signal clock signal synchronous, it is characterized in that:
This clock recovery system also comprises a time Delay Element, this time delay assembly is connected between these phase detectors and the electric charge drawing device, overlap on time domain in order to control this rising pulse and this falling pulse, make this electric charge drawing device during this overlapping, can not export an ascending current corresponding and a decline electric current, eliminate the ripple that on control voltage, produces thus because this rising pulse and this falling pulse do not overlap to this loop filter with this rising pulse and this falling pulse.
20. clock recovery system according to claim 19, wherein this time delay assembly is controlled the area that this rising pulse and this falling pulse overlap and is reached maximum on time domain.
21. clock recovery system according to claim 19, wherein this time delay assembly is controlled that leading among this rising pulse and this falling pulse pulse daley a period of time to overlap on time domain with another pulse that falls behind and to make both overlapping areas reach maximum.
22. clock recovery system according to claim 19, wherein these phase detectors produce this rising pulse earlier and produce this falling pulse again, therefore, this time delay assembly should rising pulse daley a period of time to overlap with this falling pulse, and should time of delay length be the pulse duration of this falling pulse, make to have maximum overlapping area between this rising pulse and this falling pulse.
23. clock recovery system according to claim 22, wherein this falling pulse is fixing, and its pulse duration is the one-period of this clock signal.
24. according to claim 19 or 23 described clock recovery systems, wherein this input signal is a digital signal, and this clock signal produces according to this input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021323682A CN1485986A (en) | 2002-09-24 | 2002-09-24 | Method and apparatus for reducing phase jitter in clock recovery system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021323682A CN1485986A (en) | 2002-09-24 | 2002-09-24 | Method and apparatus for reducing phase jitter in clock recovery system |
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| CN1485986A true CN1485986A (en) | 2004-03-31 |
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| CNA021323682A Pending CN1485986A (en) | 2002-09-24 | 2002-09-24 | Method and apparatus for reducing phase jitter in clock recovery system |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102006062A (en) * | 2010-12-24 | 2011-04-06 | 苏州云芯微电子科技有限公司 | Phase locked loop with zero phase error |
| CN101207472B (en) * | 2006-12-20 | 2012-03-14 | 国际商业机器公司 | Communication system and method used for synchronizing clock channel signal and data channel signal |
| CN104300966A (en) * | 2013-07-16 | 2015-01-21 | 智微科技股份有限公司 | On-chip oscillation method and on-chip oscillation device for correcting own frequency |
| CN108123714A (en) * | 2016-11-28 | 2018-06-05 | 三星电子株式会社 | Mix clock data recovery circuit and receiver |
| CN110324036A (en) * | 2018-03-28 | 2019-10-11 | 晨星半导体股份有限公司 | Clock and data recovery circuit |
| CN110800247A (en) * | 2017-07-03 | 2020-02-14 | 索尼半导体解决方案公司 | Transmitter and transmitting method, and receiver and receiving method |
-
2002
- 2002-09-24 CN CNA021323682A patent/CN1485986A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207472B (en) * | 2006-12-20 | 2012-03-14 | 国际商业机器公司 | Communication system and method used for synchronizing clock channel signal and data channel signal |
| CN102006062A (en) * | 2010-12-24 | 2011-04-06 | 苏州云芯微电子科技有限公司 | Phase locked loop with zero phase error |
| CN102006062B (en) * | 2010-12-24 | 2012-07-04 | 苏州云芯微电子科技有限公司 | Phase locked loop with zero phase error |
| CN104300966A (en) * | 2013-07-16 | 2015-01-21 | 智微科技股份有限公司 | On-chip oscillation method and on-chip oscillation device for correcting own frequency |
| CN108123714A (en) * | 2016-11-28 | 2018-06-05 | 三星电子株式会社 | Mix clock data recovery circuit and receiver |
| CN108123714B (en) * | 2016-11-28 | 2023-02-28 | 三星电子株式会社 | Hybrid clock data recovery circuit and receiver |
| CN110800247A (en) * | 2017-07-03 | 2020-02-14 | 索尼半导体解决方案公司 | Transmitter and transmitting method, and receiver and receiving method |
| CN110324036A (en) * | 2018-03-28 | 2019-10-11 | 晨星半导体股份有限公司 | Clock and data recovery circuit |
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