JPS61184001A - Pll modulator - Google Patents

Abstract

PURPOSE:To quicken the leading time of a PLL modulator by decreasing the frequency division at power onto quicken the loop locking and switching the frequency division after phase locking is obtained. CONSTITUTION:At power on, a signal of an unlock alarm line 13 goes to logical 1, a changeover switch 12 connects to a phase comparator 3 and an output subjected to phase comparison in an FH connects to a low-pass filter 6. When phase locking is reached, the frequency of two signals FH given to the comparator 3 is equal. since the frequency divisions M, Q of frequency dividers 10, 11 are equal, the frequency of the two signals FL given to a phase comparator 9 reaches FH/Q. Then the level of the signal on the signal line 13 goes to logical 0, the switch 12 is thrown to the comparator 9 and the output subjected to phase comparison by the FL connects to the filter 6. Then phase locking is attained at the FL. Thus, the phase comparison frequency is switched from the FH to the FL to quicken the leading time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL modulator C for a wireless communication device.

[Conventional technology]

FIG. 8 shows an example of the configuration of a conventionally known PLL modulator.

In this circuit, the output of voltage controlled oscillator 1 is N
The frequency is divided and applied to one input terminal C2 of the phase comparator 3. The other input terminal C2 of the phase comparator 3 is supplied with a reference signal obtained by dividing the output of the reference oscillator 4 by P by a frequency divider 5. The frequencies of these two signals are the same frequency F
It is H. Two signals gF are output from the output terminal of phase comparator 3.
A signal corresponding to the phase difference of H is output, and the low-pass filter 6
is fed back to the frequency control terminal C of the voltage controlled oscillator 1 via the frequency control terminal C, and the output to the frequency control terminal is changed in the direction that the phase difference is reduced to achieve a phase synchronized state. The modulation signal is applied to the modulation signal input terminal 7C2 of the voltage controlled oscillator 1. Terminal 8 is a terminal for receiving the output of the voltage controlled oscillator. In this type of modulator, in order to perform FM modulation down to low frequencies, the loop band of the PLL loop must be narrowed. In other words, the passband width of the low-pass filter must be narrowed, or the frequency division number must be increased. , it is necessary to reduce the loop gain.In such a configuration, the loop time constant is large, so it takes C2 hours from the time the power is turned on until the phase lock state is achieved.Therefore, until now, the loop time constant has been reduced. In order to perform the switching, the time constant of the low-pass filter is set to a fast time constant when the power is turned on, and the pull-in is performed, and then the time constant is switched to a slow time constant to obtain the required modulation frequency characteristics and to perform the pull-in quickly.
A LL modulator was used. The time constant of the low-pass filter must be chosen as required by the system;
In order to correct variations in sensitivity of the 00 etc. loop element,
Discrete components are generally used and require numerous adjustments. Also, since it is an analog circuit, LSI
This circuit is not suitable for

Does switching between low-pass filters make the circuit complicated, increase the number of adjustment steps, make the circuit smaller, and lower the price? It was hindering me. Furthermore, switching the low-pass filter causes fluctuations in the voltage fed back to the magnetic pressure controlled oscillator 1, which causes the oscillation frequency of the modulator to fluctuate, which has the disadvantage that it takes time to stabilize.

Ru.

[Purpose of the invention]

In order to solve this problem, the present invention reduces the frequency division number when the power is turned on, and increases the loop time constant. Should I make it smaller to make the loop pull in faster, and then switch the frequency division number after the phase is synchronized? It is a feature. Its purpose is to
Modulator rise time? The objective is to make it possible to modulate at high speed and down to a low frequency, to make it possible to use a monolithic IC, to reduce the size of the circuit, and to reduce the cost.

Furthermore, when combined with C2 conventional loop filter switching method,
Further improvement in rise time? The figures that can be measured will be described in detail below.

[Explanation of Examples]

FIG. 1 shows an embodiment of the present invention, in which 9 is a phase comparator, i
o and it are frequency dividers, 12 is a switching switch t, 13 is an unlock alarm signal line, and other symbols are the same as those shown in FIG. 8C-2. The features of this configuration are the phase comparator 9, frequency divider 109, frequency divider 11, and switching switch y-124'.
The purpose is to establish. The frequency division number CM) of the frequency divider 10 and the frequency division number (Q) of the frequency divider 11 are both equal to C2.

The output of the voltage controlled oscillator 1 is frequency-divided by N by a frequency divider 2C2 and applied to one input terminal C2 of the phase comparator 3. The other input terminal of the phase comparator 3 is supplied with the output of the reference oscillator 4, which is frequency-divided by a frequency divider 5 by P. The frequency after dividing by N and the frequency after dividing by P are both approximately the same frequency (FH). The frequency divider 10 further divides the output of the frequency divider 2 by M and supplies it to one input terminal of the phase comparator 9.

The other input terminal C of the phase comparator 9 is supplied with the output obtained by dividing the output of the frequency divider 5 by Q by the frequency divider 11. Since the frequency after dividing by M and the frequency after dividing by Q are Q=M, they are both approximately equal frequencies (FL:FL<FH).The signal on the unlock alarm signal line 16 is , the phase difference between the frequency divided by N and the frequency divided by P is obtained by integrating the corresponding pulses, and becomes 1 in a non-phase synchronized state.In addition, when phase synchronization is achieved, the integration time constant (more than one cycle of FH)
The delay becomes O.

The unlock alarm signal MA13 signal is 1 when the power is turned on.
The changeover switch 12 is connected to the phase comparator 3 side, and the output subjected to the phase comparison at FH is connected to the low-pass filter 6. Below, similar to the configuration example in FIG. 8, the dynamic t'f: L,
The state becomes phase synchronized. When the phase is synchronized, the frequencies of the two signals FH applied to the phase comparator 3 become equal. Also, since Q=M, the 2
One signal FL has a frequency of FH/Q7Z. The signal on the next C near-lock alarm signal line 13 becomes 0, the changeover switch 12 is switched to the phase comparator 9 side, and the output phase-compared by the low-pass filter 6r is connected, similar to Q and below FH (; operates and becomes phase synchronized at FL+2.In this way, the phase comparison frequency -17FH
It is possible to switch from FL to FL.

In the configuration shown in Fig. 1, phase synchronization t is achieved at high-speed FH+2, and the outputs of voltage controlled oscillator 1 and reference oscillator 4 are frequency-divided into 2
Frequency of one signal FL? The feature is to synchronize the phase at FL+2 after making them equal, but in order to obtain the rise characteristic of C2 high, after matching not only the frequencies of the two FLs but also the phases of the two FLs, The FL+
An effective method is to adjust the phase period to 2.

Is there phase synchronization between voltage controlled oscillator 1 and reference oscillator 4fFH, which oscillated in a free-running state when the power was turned on? 2 when I took it
The phase difference φ between the two FLs (the phase difference between the outputs of frequency divider 10 and frequency divider 11) is FH-Q-FL (the phase difference of Q corresponds to one period of FH. The phase shift of FL in the case of -4? In the figure, two FHs indicate the phase synchronized state, and FL 1 (FL '1-1) indicates the state when φ of -2 FLs is 0. When one of the FL2 devices 11 is operated with the counter stopped for one period of FH, the frequency divider 10
The phase difference between the output of the frequency divider 11 and the output of the frequency divider 11 is zero. That is, by stopping either the frequency divider 10 or the frequency divider 11 by the northern cycle of FH, the phase difference φ between the two PLs can be made zero. After that, if the changeover switch 12 is changed and the phase is synchronized by setting FL t:, 2
Since the two FLs are already in phase, the loop operates steadily from the moment of switching, resulting in fast rise characteristics.

FIG. 3 is an example of this method. The operation will be explained below based on the drawings. 9 is a phase comparator, 10.11.14
12 is a frequency divider, 12 is a selector switch, 13 is an unlock 7 alarm signal line, 15 is a switch, 16 is a sub-side of the switch, and the reference numerals for the terminals are the same as those shown in FIG. 8C-2. The features of this configuration are: phase comparator 91 frequency divider 109 frequency divider 11° frequency divider 14. SWIN f15. The purpose is to provide a switch system a16. The output of the voltage controlled oscillator 1 is frequency-divided by N by a frequency divider 2 and applied to a switch 15 and one of the input terminals of a phase comparator 6. The output of the reference oscillator 4 is connected to the curve of the input terminal of the phase comparator 6 and the input of the frequency divider 14.
An output frequency-divided by P is given.

The frequency after dividing by N and the frequency after dividing by P are approximately the same frequency FH. The frequency divider 10 divides the frequency of the output of the input signal f15 by M and supplies it to one input terminal C2 of the phase comparator 9. Frequency divider 14 is applied to one of the output terminals of frequency divider 5. The frequency divider 11 divides the output of the frequency divider 5 by Q and supplies it to the other input terminal of the phase comparator 9. The frequency after frequency division by M (FL2) and the frequency after frequency division by Q (FLl) are approximately the same frequency FL, and M=Q. Phase comparator 9
The signal (■) given to the switch control 16 is a signal that is 1 when FL1 and FL2 are in phase, and 0 when they are out of phase, based on the result of the phase comparison. The signal on the unlock alarm signal line 13 is the same as that in the configuration example shown in FIG. 1, but the integration time constant is longer than one cycle of PL. When the power is turned on, the switch 15 is in the ON state. Since the phases of FL1 and FL2 do not match, the signal on the unlock alarm signal line 13 becomes 1, and the switching switch f12 is connected to the phase comparator 3 side. Thereafter, as in the configuration example shown in FIG. 8, C2 operates, FHr2 becomes phase synchronized, and the phases of the two FHs match. Next I: As described below, the switch control 16 repeatedly turns the switch 15 0FF-ON using the signals ■ and ■, making the phases of FLl and FL2 equal, and the signal on the unlock alarm signal line 13 becomes 0.
Therefore, the changeover switch 12 is connected to the phase comparator 9 side, and the following FLr: Therefore, the phase synchronization state is established.

Fig. 4 shows an example of the operation of the switch control 16 (FH=4・F
L) is shown. Switch control 16 has two HANDGATs
It consists of E and becomes the operation shown in Fig. 5 [:]. FH+: Time point when phase synchronization is achieved ■t: 0 until FL1 and FL2. According to the state transition diagram, the output ■ is H during the period α, and the switch 15 is turned on. ■ is L in the period β
Therefore, the switch 15 is turned off, and when ■ becomes 0, the switch 15 is turned on again. Switch 15 is OFF
When F is between @ and θ and corresponds to one period g2 of FH, the frequency divider 10 stops for one period. Next, immediately after ■, FLl becomes 1, and even though ■ becomes 1 due to the operation of the phase comparator, the switch 15 remains ON. Similarly, after the period C2 from ■ to @, the state changes [1] When the switch 15 is turned OFF for one period of FH and the operation of the frequency divider 10 is stopped, the phase of FL2 is delayed by π and FLl is Since the phase matches FL2 from when it becomes L, ■ remains at 1, and even when ■ becomes 1, the switch 15 remains ON. Figure 4 (= FH
-2, the phase of FLl etc. is delayed in the frequency divider 1.
This is due to the delay C in the operation of the 02 frequency divider 112 frequency divider 14 and phase comparator 9. In this way, FLl and F
The phase difference of ld can be eliminated. Also unlock alarm signal! When the phases of FL1 and FL2 match, the signal 13 is stopped for one cycle of FL due to an integral time constant and becomes 0, and at time point C2 (2), the switch 12 is connected to the phase comparator 9 side.

be done.

An example will be shown in which the phase comparison frequency can be switched by matching the phase relationship between FH and FL, similar to the configuration example of the '1iJs diagram. This configuration is the same as the configuration in Figure 1, but
The signal on the unlock alarm signal line 15 is applied to the reset terminals of the frequency divider 10 and the frequency divider 11. When the frequency divider 10 and the frequency divider 11 are phase synchronized at the FHC2 and the signal on the unlock alarm signal line 13 becomes 0, the frequency division operation tlE starts. The phases of the two FHs match, and the frequency divider 1
Since the frequency division number of the frequency divider 11 is equal to 0, the phases of FL1 and FL2 match.

In this way, f2 and C2 FL1 and F are similar to the configuration example in FIG.
Phase difference of L2? Without this, the phase comparison frequency can be switched. FIG. 7C shows the experimental results based on the configuration of FIG. 3 shown as an embodiment of the present invention.

The frequency of the voltage controlled oscillator is 145 MHz, the frequency of the reference oscillator is 12.8 MHz, and the FH is 100. KHz
, shows the modulation frequency characteristics when FL is 71/25KHz. Based on 1 KHz, the frequency that decreases by 5ttE is 4.5H2. Furthermore, the photographed portion in the figure (the trace section in the right half of the figure) shows the rising characteristic. The horizontal axis shows time, and the vertical axis shows frequency and voltage. P at the time of ■
The power to the LL modulator is turned on. The two waveforms in the upper row f are the frequency of the voltage controlled oscillator, and the vertical axis is 5 KHz/1.
It is a scale. It can be seen that the phase synchronization state due to FH-2 is reached at about 7Qmztc after the power is turned on. When the phase comparison frequency is set to FL (25KHz) only and the power is turned on without changing the frequency division number, approximately 820mJPgC
The state becomes phase synchronized. The waveform shown in the lower row is from FH to PL.
The switching timing is approximately 101001 after the power is turned on.
At the time of nI■, the frequency division number is switched and the circuit operates at FL.

That is, by applying the present invention, 820 meg
The rise characteristic that existed previously can be shortened to 7Qmzgc.

In the description of each embodiment of the present invention described above, the frequency divider 2.
10. The frequency dividers 5 and 11 have been described as separate frequency dividers.

However, in the configuration examples of FIG. 1 and FIG. (Also possible, but not shown). If so, one frequency divider shown at point ml2 will output 42 outputs FH, FL or F.
It is understood that Ll and FL2.

Do you understand the embodiments of this invention? Although the C2 frequency divider is separated to facilitate C2, in the present invention, the general C2, in other words, the output of the voltage controlled oscillator, is divided into I frequency and J frequency divider from C2.
, I, J are integers) output, reference oscillator output? - Frequency divider t: Frequency division and L frequency division (K cut).

K and L are integers).

[Explanation of effects]

A PLL modulator is a technology that modulates a highly stable, high-purity oscillator with signals such as audio to obtain high-quality harmonics. It is well known that the rise time becomes longer.

In the present invention, the PLL modulator performs the rise and short interval C2,
Moreover, since it is capable of modulating up to low frequencies (several Hz or less), it has the advantage of being able to modulate not only audio signals but also various data signals in the lower audio band C2.

In addition, it is possible to form a monolithic IC, resulting in smaller size and lower cost, and furthermore, it has the advantage of lower power consumption. Furthermore, since the stability of the oscillation frequency is high, there is an advantage that the modulator C can be used in conjunction with two modulators in a wireless communication device that requires high frequency stability.

[Brief explanation of the drawing]

FIG. 1 shows a configuration diagram of an embodiment of the present invention. FIG. 2 shows a timing waveform diagram (with Q=4) for explaining the operation of FIG. 1. FIG. 6 shows a block diagram of another embodiment of the present invention. 'i! Figure IJ4 shows a timing waveform diagram for explaining the operation of Figure 5. fi5 diagram shows a state transition diagram. FIG. 6 shows a block diagram of another embodiment of the present invention. device, 5, 9... phase comparator, 4... reference oscillator, 6
...Low pass filter, 7...Modulation signal input terminal, 8.
... Output terminal, 12... Selector switch, 15... Unlock alarm signal line, 15... Switch t, 16...
...Controlling the SWIN Patent applicant Nippon Telegraph and Telephone Public Corporation agent Patent attorney Gobe Tamamushi (2 others) Figure 1 Figure 2 State transition diagram Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. Phase difference between the voltage controlled oscillator, the reference frequency oscillator, the output of the frequency divider that divides the output of the voltage controlled oscillator, and the output of the frequency divider that divides the output of the reference frequency oscillator. A PLL modulator including a low-pass filter provided between a phase comparator that detects the phase difference and outputs a voltage corresponding to this phase difference and an input terminal of the voltage controlled oscillator divides the output of the voltage controlled oscillator. The frequency divider that divides the frequency has two frequency division numbers, I frequency and J frequency (I<J: I and J are integers), and similarly, the frequency divider that frequency divides the output of the reference oscillator is , K division and L division (
K < L, K, L is an integer), and the frequency after dividing by I and the frequency after dividing by K are almost the same frequency (FH), and the frequency after dividing by J is approximately the same frequency (FH). Frequency and L after cycling
The frequencies after frequency division are almost the same frequency (FL) (FH>FL), and at the start point of the loop, phase comparison is performed at FH, and then phase comparison is performed at FL. PLL modulator. 2. In the PLL modulator according to claim 1, phase comparison is performed at the frequency after I frequency division and the frequency (FH) after K frequency division, and the loop is in a phase locked state. After that, the operation of the J frequency divider or the L frequency divider is temporarily stopped so that the phase difference between the output of the J frequency divider and the output of the L frequency divider is eliminated, and then the frequency after the J frequency division and the A PLL modulator characterized in that phase synchronization is performed at a frequency (FL) after frequency division by L. 3. In the PLL modulator according to claim 1, phase comparison is performed at the frequency after I frequency division and the frequency (FH) after K frequency division, and the loop is in a phase locked state. After that, start J frequency division and L frequency division at the same time so that there is no difference between the output of the J frequency divider and the output of the L frequency divider. frequency (F
A PLL modulator characterized in that phase synchronization is performed in L).