JPS60241338A - Encoder and decoder - Google Patents

Abstract

PURPOSE:To reduce the degradation due to leakage by making frequency division ratios of frequency dividers, which the first and the second PLL loops incorporate, different from each other in an encoder and decoder used in the PCM system or the like. CONSTITUTION:The frequency division ratio of a frequency divider 30 is set to, for example, 1/18, and the first synchronizing signal 11 is inputted to a phase comparator 25, and a comparison signal 26 proportional to the phase difference between the signal 11 and a frequency division output signal 31 is outputted, and a loop filter 27 outputs an integral signal 28, and an internal clock signal 9 from a voltage control variable frequency oscillator 29 has the frequency divided by the frequency divider 30 and is inputted to the comparator 25, and therefore, the clock signal 9 synchronized with the synchronizing signa 11 has 144kHz. Meanwhile, the frequency division ratio of a frequency divider 37 is set to, for example, 1/17, and the second synchronizing signal 12 is inputted, and then, an internal clock signal 14 has 136kHz frequency. Consequently, the degradation of S/N due to leakage of internal clock signals is reduced.

Description

TECHNICAL FIELD The present invention relates to a code Φ decoder used in the PC'M system, etc., and particularly relates to improvements for improving the signal-to-noise ratio in the encoder and decoder. .

Prior Art FIG. 1 is a block diagram showing the basic configuration of an encoder/decoder, which is composed of an encoder 23 and a decoder 24. The encoder 23 inputs the audio frequency analog signal 1 and includes a first filter 2 that passes only a predetermined frequency band.
and an encoder 4 that converts and outputs the output signal 3 of the first filter 2 into a digital signal at a constant period, and a frequency of 8K.
Input the first synchronization signal 11 of Hz, and synchronize with the first synchronization signal 11 at a frequency 16 times that of the first synchronization signal 11 (128KHz).
[The first PLL loop that outputs the internal clock signal 9]
0 and an internal clock signal output from the first PLL loop 10 to the first filter 2 and encoder 4;
It is comprised of a control circuit 8 that controls the operation of the first filter 2 and encoder 4 using control signals 6 and 7. The decoder 24 includes a decoder 21 that converts the received digital signal 22 into an analog signal, a second filter 18 that passes only audio band signals from the output signal 20 of the decoder 21, and a signal that is input in synchronization with the received signal. A second PLL loop 13 synchronizes with the second synchronization signal 12 (8KHz) and outputs an internal clock signal 14 with a frequency (128KH2) 16 times that of the second synchronization signal 12 (8KHz); Control signals 18 and 17 are outputted by the clock signal 14, and the decoder 21 and the second
and a control circuit 15 that controls the operation of the filter 18.

The first filter 2 is a switched capacitor filter operated by an internal clock signal of, for example, 128 KHz supplied from the control circuit 8, and removes low frequency components and high frequency components of the analog signal 1 and outputs the output signal 3 to the encoder 4.
The encoder 4 converts the input signal into a sample digital signal in synchronization with the first synchronization signal 11 and outputs it as a digital output signal 5.

The second filter 19 is operated by a control signal 18 supplied from the control circuit 15 and an internal clock signal having a frequency that is, for example, 18 times that of the second synchronization signal 12, and removes high frequency components of the output signal 2o of the decoder 21. This is a switched capacitor filter that outputs an audio frequency analog output signal 18.

In the conventional encoder/decoder, the first
and the second PLL loop are both set to output internal clock signals with the same frequency as the input M@ signal, so the encoder's internal clock signal 9 and the decoder's internal clock signal 14 have the same frequency, for example, 128KH2 (or 258KHz), and when the internal clock signals 9 and 14 overlap, noise such as the internal clock signal leaked from the decoder 24 at the moment the first filter 2 shifts from sample to hold. is mixed into the hold voltage of the first filter 2, and the signal-to-noise ratio (S/N) of the output signal of the encoder 23 is degraded. Similarly, in the decoder 24, noise caused by the internal clock signal 9 on the encoder 23 side mixes into the hold voltage of the second filter 18, deteriorating the signal-to-noise ratio.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a code capable of solving the above-mentioned conventional drawbacks and reducing the deterioration of the signal-to-noise ratio due to the contamination of noise between the internal clock signal of the encoder and the internal clock signal of the decoder. - To provide a decoder.

Structure of the Invention The encoder/decoder of the present invention includes a first PLL loop that synchronizes with a first synchronization signal and outputs an internal clock signal having a frequency that is an integral multiple of the first synchronization signal, and an internal clock signal that outputs an internal clock signal of the first PLL loop. an encoder having a first filter that operates according to a clock signal; an encoder that converts and outputs an output signal of the first filter into a digital signal in synchronization with the first synchronization signal; and an encoder that receives the received digital signal. a decoder that decodes into an analog signal in synchronization with a second synchronization signal inputted in synchronization with the signal; a second filter connected to the output of the decoder; 2
and a second PLL loop that generates and outputs an internal clock signal for operation of the decoder. and a frequency division ratio of a frequency divider built in the second PLL loose are set to different frequency division ratios.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

2 and 3' are block diagrams showing the configurations of the first PLL loop lO1 of the encoder 23 and the second PLL loop 13 of the decoder 24, respectively, used in one embodiment of the present invention. Other parts are the same as the basic configuration shown in FIG. That is, the first PLL loop 10 is composed of a loop circuit including a phase comparator 25, a loop filter 27, a voltage controlled variable frequency oscillator (VCO) 28, and a frequency divider 30, and the division ratio of the divider 30 is set to 1718. The 0-phase comparator 25 to be set receives the first synchronization signal 11 with a frequency of 8 KHz, and outputs a comparison signal 26 proportional to the phase difference between the frequency-divided output signal 31 of the frequency divider 30 and the first synchronization signal 11. The loop filter 27 integrates the comparison signal 26 and outputs a smoothed integral signal 28. Voltage controlled variable frequency oscillator 2
8 oscillates at a frequency corresponding to the voltage of the integral signal 28 and outputs an internal clock signal 9. Internal clock signal 9 is frequency-divided by 1/18 by frequency divider 30 and input to phase comparator 25 . Therefore, the internal clock signal 9 becomes a clock signal with a frequency of 144 KHz synchronized with the first synchronization signal 11. Internal clock signal 9 is supplied to first filter 2 and encoder 4 as an internal clock signal for operation of encoder 23. Of course, the first filter 2 and the encoder 4 have internal constants and the like set so as to operate with a clock signal having a frequency of 144 KHz.

On the other hand, the second PLL loop 13 is composed of a loop circuit including a phase comparator 32, a loop filter 34, a voltage controlled variable frequency oscillator 3B, and a frequency divider 37, as described above.
Set the frequency division ratio to 1717. Then, the second synchronization signal 12 is input to the phase comparator 32, and the phase comparator 32 outputs a comparison signal 33 proportional to the phase difference between the frequency-divided output signal 38 of the frequency divider 37 and the second synchronization signal 12. Loop filter 34
The integrated signal 35 of the loop filter 34 controls the oscillation frequency of the voltage controlled variable frequency oscillator 3B. Since the second synchronization signal 12 is a signal with a frequency of 8 KHz that is input in synchronization with the received signal, the internal clock signal 14 output from the voltage controlled variable frequency oscillator 36 is 1 KHz.
It becomes 38 KHz. Therefore, the second filter 18 and the decoder 21 built in the decoder 24 use the internal clock signal 14 of 136 KHz synchronized with the second synchronization signal 12.
In this embodiment, since the internal clock signal 9 and the internal clock signal 14 have different frequencies and are not in a multiple relationship with each other, the probability that one of the two signals will overlap with each other is low. This has the effect of reducing S/N deterioration due to leakage and the like.

Effects of the Invention As described above, in the present invention, the first PL of the encoder
By making the frequency division ratios of the built-in frequency dividers different in the L loop and the second PLL loop of the decoder, the frequencies of the internal clock signals of the encoder and decoder can be set to different frequencies that are not multiples of each other. Since the configuration is configured to set
This has the effect of reducing the deterioration of /H.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the encoder/decoder, and FIGS. 2 and 3 are block diagrams showing the configurations of #11 and second PLL loose, respectively, used in an embodiment of the present invention. It is. In the figure, l: analog signal, 2: first filter,
3: Output signal, 4: Encoder, 5: Digital output signal, 6, 7, 18.1? : control signal, 8.15: control circuit, 9.14: : internal clock signal, lO: first
PLL loop, l■ = first synchronization signal. 12: Second synchronization signal, 13: Second PLL loop, 1
8: Analog output signal, 18: Second filter, 23:
Encoder, 24: Decoder, 25.32: Phase comparator, 2G
, 33: comparison signal, 27, 34: loop filter, 2
8,357 integral signal, 211.38: Voltage controlled variable frequency oscillator, 30.3? : Frequency divider, 31, 38: Frequency division output signal. Applicant: NEC Corporation Agent: Patent Attorney: Toshimune Sumita

Claims (1)

[Claims] a first PLL loop that synchronizes with the first synchronization signal and outputs an internal clock signal having a frequency that is an integral multiple of the first synchronization signal; and a first PLL loop that receives an analog signal and operates based on the internal clock signal output from the first PLL loop. and the first filter.
an encoder that converts and outputs the output signal of the filter into a digital signal in synchronization with the first synchronization signal, and converts the received digital signal into a second synchronization signal that is input in synchronization with the reception signal. a decoder that synchronously decodes the analog signal; and a second decoder connected to the output of the decoder.
and a decoder having a second PLL loop that receives the second synchronization signal and generates and outputs an internal clock signal for operation of the second filter and decoder, The @ sign indicates that the frequency division ratio of the frequency divider built in the first PLL loop and the frequency division ratio of the frequency divider built in the second PLL loop are set to different frequency division ratios. encoder/decoder.