KR0139827B1 - Clock generating circuit equipped with revised phase locked loop - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit having an improved phase locked loop (PLL) circuit, which compares the phase of an internal comparison pulse generated based on an input external reference pulse and an oscillation clock (VCXO) in the loop. A phase detector 33 for generating a phase difference signal, a low pass filter 34 for generating a DC control voltage corresponding to the phase difference signal, and an oscillation clock VCXO corresponding thereto according to the control voltage signal. The voltage-controlled oscillator 35, the fourth divider 36 which divides the oscillation clock VCXO into two to generate a system clock SYS-CLK, and counts the system clock SYS-CLK. The second counter 39 which generates an internal pulse having the same frequency in synchronization with the pulse, and the internal pulse and the external pulse are inputted using the system clock SYS-CLK as an operation clock to compare both pulses. Pulse and internal pulse A comparator 42 for outputting a delay difference signal OVF indicating a delay difference between the signal and a sine signal SIGN indicating an input order between the two signals, and an enable signal applied to the output of the comparator 42 described above. If the internal pulse and the external pulse come in at the same time, it generates N signal which is the reference value, and if the internal pulse comes in before the external pulse, it generates the NM value obtained by subtracting the variable value (M) from the reference value (N). Is a decoder 40 for generating an N + M value, a first counter 41 for dividing and outputting the oscillation clock VCXO using the output signal of the decoder 40 as a division ratio, and the first counter. And a fifth divider 37 for dividing the output of the one counter 41 at a predetermined division ratio to generate an internal comparison pulse compared with the external reference pulse input to the phase detector 33. Due to clock or external pulse fluctuations Even if the frequency ratio between the internal pulse and the system clock and the synchronization between the internal pulse and the external pulse are broken, the synchronization is automatically restored and maintained continuously.

Description

Clock Generation Circuit with Improved Phase Locked Loop Circuitry

1 is a block diagram of a reference clock generation circuit of a conventional CDMA mobile communication base station.

2 is a block diagram of a clock generation circuit with an improved phase locked loop (PLL) circuit in accordance with the present invention.

3 is a conceptual diagram of supplying an external pulse to each CDMA mobile communication base station using a GPS satellite.

4 is a timing diagram of a clock generation circuit having an improved phase locked loop circuit according to the present invention shown in FIG. 2, (a) in which the division ratio of the first counter is NM, i. (B) shows the case where the division ratio of the first counter is N, that is, the case where the internal pulse and the external pulse enter simultaneously, and (c) shows the case where the division ratio of the first counter is N + M, The external pulse comes in first.

* Explanation of symbols for main parts of the drawings

10, 30: first divider 11, 31: second divider

12, 32: third divider 13, 33: phase detector

14, 34: loop filter 15, 35: voltage controlled oscillator

16, 36: fourth divider 17, 37: fifth divider

18: 6th divider 19: Counter

20: comparator 39: second counter

40: decoder 41: first counter

42: comparator 45 to 48: base station

49: GPS satellites

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit having an improved phase locked loop (PLL) circuit, and more particularly to an external pulse and an internal pulse supplied from a GPS (Global Positioning System) satellite in a plurality of mobile communication base stations of CNMA. A clock generating circuit having an improved phase locked loop circuit capable of continuously maintaining coherence between pulses and between an internal pulse and the system clock.

Code base station multiple access (CDMA) base stations are generating internal pulses of 19.6608 MHz system clock (SYS-CLK) and 1 pulse per second (PPS) required for data transmission and reception.

Also, as shown in FIG. 3, each of the base stations 45 to 48 receives an external reference clock of 10 MHz and an external pulse of 1 PPS from the GPS satellites 49 to synchronize the reference clocks between the base stations. As shown in FIG. 1, a system clock of 19.6608 MHz and an internal pulse were generated by a clock generation circuit. In this case, not only the internal and external pulses are synchronized but also a constant ratio of frequency is maintained between the system clock and the internal pulses. Collectively this is called coherence.

To this end, a system clock (SYS-CLK) is generated using a PLL circuit by receiving an external reference clock of 10 MHz, and an internal pulse of 1 PPS synchronized with an external pulse of 1 PPS is synchronized with this system clock (SYS-CLK). It was the way it happened. In more detail, the reference clock generation circuit according to the related art uses an external reference clock of 10 Mhz as shown in FIG. 1 to match the coherence of the PLL circuit, that is, 1.6 Khz. First to third dividers 10 to 12, phase detector 13, low pass filter (LPF) 14, voltage controlled oscillator (VCO) 15, and fifth and sixth dividers for conversion to frequency. A PLL oscillator composed of (17, 18), a fourth divider 16 which divides the output of the PLL oscillator from the 39.3216 MHz output (VCXO) to the system clock frequency, and the fourth divider 16 described above. Comparator 13 for comparing the coherence synchronization between the internal pulse and the external pulse using the clock as the operation clock, and a counter 19 for generating the internal pulse from the external pulse using the system clock of the fourth divider as the operation clock. It was.

In the conventional clock generation circuit configured as described above, in order to continuously maintain coherence synchronization, first, the third divider 10 to 12 processes the 5 MHz, 625, and 2 divisions of the 10 Mhz external reference clock. The signal is divided into a reference pulse of 1.6 kHz and input to the phase detector 13 of the PLL. On the other hand, the voltage controlled oscillator 15 generates a clock signal VCXO of 39.3216 Mhz in accordance with the output of the low pass filter 14 which generates a control voltage in accordance with the phase difference signal from the phase detector 13.

The VCXO is divided into 1.6 kHz by the fifth and sixth dividers 17 and 18 and fed back to the phase detector 13 to output and phase the third divider 12 of 1.6 kHz. The voltage values corresponding to the difference are compared and applied by the lowpass filter 14 to the voltage controlled oscillator 15, the output of which is repeated in a loop fed back to the phase detector 13 and always the voltage controlled oscillator 15 ) Generates a clock pulse of 39.3216Mhz frequency.

On the other hand, VCXO is again divided into two 19.6608Mhz system clock (SYS-CLK) output and used as the operating clock of the counter 19 to generate an internal pulse of 1PPS from an external pulse of 1PPS, and also the system clock (SYS CLK is input to the operation clock of the comparator 20, and the comparator 20 compares an external pulse with an internal pulse which is an output of the counter 19. That is, the counter 19 which operates SYS-CLK as a clock generates an internal pulse of the same period as the external pulse in synchronization with an external pulse only at an initial stage. This internal pulse is input to the comparator 20 again. At this time, the comparator 20 outputs a delay difference signal OVF indicating a delay difference between the external pulse and the internal pulse and a SIGN signal indicating which of the internal pulse and the external pulse is input first.

Conventional clock generation circuits configured and operated as described above have coherent synchronization at initial startup, but when a change occurs in either the external reference clock or the external pulse, between the external pulse and the internal pulse and between the internal pulse and the system clock. There is a problem that consistency synchronization is lost, and the system has to be restarted to recover it.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-described problems of the clock generation circuit according to the prior art, and includes an improved phase locked loop circuit capable of continuously maintaining coherence synchronization between an internal pulse and an external pulse and an internal pulse and a system clock. One clock generation circuit is provided.

In order to achieve the above object, the present invention corresponds to a phase detector for generating a phase difference signal by comparing a phase of an internal comparison pulse generated based on an input external reference pulse and an oscillation clock (VCXO) in a loop, and corresponding to the phase difference signal. A low pass filter for generating a DC control voltage, a voltage controlled oscillator for generating an oscillation clock (VCXO) corresponding to the control voltage signal according to the control voltage signal, and a system clock (SYS-) by dividing the oscillation clock (VCXO) in two. A fifth divider for generating CLK, a second counter for counting the system clock (SYS-CLK) to generate an internal pulse having the same frequency in synchronization with an external pulse, and the system clock (SYS-CLK) The internal clock and the external pulse are inputted as the operation clock, and the delay difference signal (OVF) indicating the delay difference between the external pulse and the internal pulse and the two pulses are compared to each other. A comparator for outputting a sine signal (SIGN) indicating a signal, and an internal signal and an external pulse are generated when the internal pulse and the external pulse are simultaneously input while the enable signal is applied to the output of the comparator. In the case of a pulse coming in before the pulse is generated by subtracting the variable value M from the reference value N, and vice versa, the decoder generates an N + M value and the output signal of the decoder as the division ratio. A first counter for dividing and outputting the oscillation clock VCXO; and a fifth for dividing the output of the first counter at a predetermined division ratio to generate an internal comparison pulse compared with the external reference pulse input to the phase detector. A clock generating circuit having an improved phase locked loop circuit composed of a divider is provided.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

First, FIG. 2 is a block diagram of a clock generation circuit with an improved phase locked loop circuit according to the present invention, and FIG. 3 is an external reference pulse of 10 MHz and an external pulse of 1 PPS for each CDMA base station using GPS satellites. 4 is a timing diagram of a clock generation circuit having an improved phase locked loop circuit according to the present invention shown in FIG. 2, (a) is a case where the division ratio of the first counter is NM, that is, (B) shows the case where the division ratio of the first counter is N, that is, the case where the internal pulse and the external pulse are input at the same time, and (c) the division ratio of the first counter is N. In the case of + M, that is, the external pulse comes in first.

First, the present invention initially receives an external reference clock of 10 MHz from the GPS satellite 49, divides the frequency into 2 MHz by using the first divider 30, and then divides the frequency into 3.2 MHz by using the second divider 31. After dividing the circuit into 625, it is further divided into 1.6Khz using the third divider 32 and used as an external reference pulse of a phase locked loop (PLL) circuit.

The external reference pulse of 1.6Khz is input to the phase detector 33, while the VCXO of 39.3216Khz output from the voltage controlled oscillator (VCO) 15 is used as the clock of the first counter 41 and the fourth minute. The period 36 divides the system clock (SYS-CLK) at 19.6608 Khz to be used as an operation clock of the second counter 39 and the comparator 42.

The second counter 39 receives an external pulse of 1PPS from the GPS satellite 49 as a 1PPS counter and starts counting SYS-CLK at the time when the external pulse is applied to generate an internal pulse of 1PPS. In this case, the internal pulse is the internal pulse faster than the external pulse if the cycle of SYS-CLK is faster according to the clock speed of SYS-CLK. If is normal, it generates an internal pulse of the same period as an external pulse.

On the other hand, the internal pulse and the external pulse are input to the comparator 42. At this time, the comparator 42 is started by the first pulse of the internal pulse and the external pulse, and outputs a delay difference (OVF) signal between both pulses caused by the delay difference between the first pulse and the later pulse. Outputs a SIGN signal for which one of the pulse and the external pulse was input first. That is, when the internal pulse comes before the external pulse, the delay difference (Δt of (D) shown in Figs. 4A and 4C) from the time when the internal pulse enters to the external pulse comes in. At intervals of), the value of the SIGN signal is from '0' to '1', and when it comes in at the same time, it becomes '1' to '0'. When the external pulse comes before the internal pulse, there is no change at '1'.

The decoder 40 receiving the two signals SIGN and OVF varies the division ratio of the first counter 41 according to the two input signals. That is, the decoder 40 receives an N + M signal when an external pulse comes first based on a SIGN signal and an OVF signal only when an EN signal is applied, and an N signal when an external signal comes in at the same time, and an internal pulse first. When it comes to NM signal is output.

On the other hand, the above enable signal (EN) is controlled by a controller not shown in the figure, the controller confirms that the external pulse of 1PPS and also the internal pulse of 1PPS is input once every 1 second. The EN signal is output as '1' only when the OVF and SIGN signal values are not '0'.

For example, as shown in FIG. 4A, when the internal pulse is input to the decoder 40 before the external pulse, the NM signal obtained by subtracting the delay difference value M = 1 from the normal division ratio N = 32, 31 is input to the counter 41. Accordingly, the first counter 41 divides the output VCXO of the voltage controlled oscillator 35 by 31 and applies the output to the fifth divider 37. This value is then divided by 768 by the fifth divider 37 and input to the phase detector 33. In this case, since the internal comparison pulse applied to the phase detector 33 is divided by 31 at the first counter 41, the internal comparison pulse has a frequency value slightly higher than the frequency of 1.6 kHz in the normal case.

Accordingly, the phase comparator 33 generates a phase difference signal by comparing an external reference pulse of 1.6 kHz with an internal comparison pulse somewhat higher than 1.6 kHz.

This phase difference signal is converted into a DC control voltage in a low pass filter 34 composed of a loop filter and applied to the voltage controlled oscillator VCO 35. As described above, when the frequency of the internal comparison pulse is higher than the frequency of the external reference pulse, the DC control voltage applied to the VCO 35 is lowered. Therefore, the oscillation frequency of the VCO 35 is slightly lower than 39.3216 Mhz.

Thereafter, the output VCXO of the VCO 35 is divided by two by the fourth divider 36 and inputted to the second counter 39 as a clock to reduce the speed of the internal pulse, thereby reducing the speed of the internal pulse. It is applied to the comparator 42 by delaying the time as it came in earlier. The above process continues until the external and internal pulses enter the comparator 42 simultaneously.

If the external pulse and the internal pulse are simultaneously input to the comparator 42 as shown in FIG. 4 (b), the values of the SIGN signal and the OVF signal, which are outputs of the comparator 42, become '0' and the SIGN to the decoder 40. Since the N signal is distributed by 32 division until the signal having the value of the signal and the OVF signal is '1' is applied, the phase detector 33 is no longer corrected. Therefore, the coherence synchronization between the inner pulse and the outer pulse is maintained continuously.

The above process is described in more detail with reference to FIG. 4 as follows.

When the comparator 42 first receives an internal pulse such as (C) shown in FIG. 4 (a), the comparator 42 starts counting and a point in time at which an external pulse such as (B) of FIG. 4 (a) enters. OVF signal as shown in (D) of FIG. 4 (a) which is a delay difference between two pulses, and a SIGN signal as shown in (E) of FIG. 4 (a) which shows the post-input order between both pulses. In FIG. 4, since the internal pulse came in first and there is a difference by Δt shown in (D) of FIG. 4 (a), the SIGN signal and the OVF signal become '1'.

After receiving the OVF signal and the SIGN signal, the decoder 40 outputs a signal as shown in (I) of FIG. 4 (a) when the EN signal as shown in (F) of FIG. 4 (a) becomes '1'. . At this time, the counter 41 receives and counts a new value, that is, 31 (N-M, 32-1) at the time when the work 32 (N) count already in progress ends. In other words, when the internal pulse comes in first, the output of the internal pulse should be slowed down to achieve consistency synchronization with the external pulse. To this end, if the division ratio of the counter 41 is reduced from N 32 to N-M 32-1, 768 is divided by a fifth divider 37 at a frequency higher than 1.6 kHz and input to the phase detector 33.

Therefore, the frequency of the VCXO is lowered, which is again divided by the fourth divider 36 and provided to the clock of the second counter 39 to slow down the output of the internal pulse, and the above process is performed with the internal pulse. The repetition is repeated until there is no delay difference Δt between the external pulses to maintain the coherence synchronization between the external and internal pulses.

On the other hand, when the external pulse comes in first, the decoder 40 outputs an N + M signal (dividing 33) as shown in (G) of FIG. 4 (c), and is the output of the voltage controlled oscillator 35 as described above. Fast output of the VCXO maintains coherence synchronization between external and internal pulses.

The present invention configured and operated as described above automatically maintains and maintains coherency synchronization even if the frequency ratio between the internal pulse and the system clock and the synchronization between the internal pulse and the external pulse are broken due to the variation of the external reference clock or external pulse. It provides the effect.

Therefore, when the conventional coherence synchronization is broken, the inconvenience of receiving the reference signal from the GPS satellites and restarting it again between each base station can be solved, and the reliability of wireless communication can be improved.

Claims (6)

A phase detector 33 for generating a phase difference signal by comparing a phase of an internal comparison pulse generated based on an input external reference pulse and an oscillation clock VCXO in a loop, and generating a DC control voltage corresponding to the phase difference signal. The low-frequency call filter 34, the voltage controlled oscillator 35 for generating an oscillation clock VCXO corresponding thereto according to the control voltage signal, and the oscillation clock VCXO are divided into two and the system clock SYS-CLK. A fourth divider (36) generating a second frequency, a second counter (39) counting the system clock (SYS-CLK) and generating an internal pulse having the same frequency in synchronization with an external pulse, and the system clock. A sine indicating a delay difference signal (OVF) indicating a delay difference between an external pulse and an internal pulse and an input sequence between the two pulses by receiving the above internal pulses and external pulses with (SYS-CLK) as an operation clock. SIGN When the internal pulse and the external pulse are simultaneously input while the enable signal is applied to the comparator 42 outputting the comparator 42 and the output of the comparator 42, an N signal as a reference value is generated, and the internal pulse is external In the case where the pulse comes in earlier than the pulse value, the NM value is obtained by subtracting the variable value M from the reference value N, and vice versa. A first counter 41 which divides the oscillation clock VCXO and outputs the output signal as a division ratio, and divides the output of the first counter 41 at a predetermined division ratio and inputs the phase detector 33 to the phase detector 33. And a fifth divider (37) for generating an internal comparison pulse compared with said external reference pulse. 2. The clock generation circuit as recited in claim 1, wherein said external reference pulse is obtained by dividing an external reference clock received from a GPS satellite. 2. The clock generation circuit of claim 1, wherein the external pulse is a 1PPS signal received from a GPS satellite. 2. The clock generation circuit as recited in claim 1, wherein the enable signal is supplied only when a delay difference signal (OVF) and a SIGN signal are generated. 2. The phase detector (33), low pass filter (34), voltage controlled oscillator (35), fourth and fifth dividers (36, 37), and first and second counters (41, 39). ), The comparator 42 and the decoder 40 form a phase locked loop (PLL) circuit, and are feedback-controlled to maintain synchronization between the internal pulses and the external pulses and a predetermined frequency ratio between the internal pulses and the system clock. And a clock generation circuit with an improved phase locked loop circuit. 6. A clock generation circuit as claimed in any preceding claim, wherein the clock generation circuit is applied to a CDMA mobile communication base station.