JP2000004152A - Time frequency reference signal generator and reference time frequency generating device, and reference time generating device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time frequency reference signal generator which corrects the timing of a periodic pulse signal. SOLUTION: This time frequency reference signal generator measures the deviation in generation timing between the synchronous reference pulse signal outputted from a GPS receiver and the frequency-divided pulse signal, generated by dividing the frequency of the output pulse signal of a high-stability internal pulse signal generator 24, in terms of the number of output pulses of the high- stability internal pulse signal oscillator 24 and increases or decreases the frequency division value based on the measured value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a time-frequency reference signal generator, and more particularly to a time-frequency reference signal generator for correcting the timing of a periodic pulse signal. In addition, the present invention relates to generation of a reference pulse signal generated at a constant cycle and a generator for generating a frequency signal having a fixed number of pulses for each period section of the reference pulse signal. In particular, the generation of a reference pulse signal generated in synchronization with a one-second reference pulse signal generated by receiving a radio wave from an artificial satellite having a built-in atomic frequency standard, and a constant for each period section of the reference pulse signal The present invention relates to a generator for generating a frequency signal of the number of pulses.

[0002]

2. Description of the Related Art First, a prior art relating to a time-frequency reference signal generator will be described.

In recent years, a time information signal transmitted by an artificial satellite equipped with an atomic frequency standard using radio waves has been used as a reference signal for synchronization in mobile communication and other signal transmission technology fields. However, since this time information signal includes an error of time variation due to various causes, the time information signal cannot be used as it is as it is, and usually, the time information signal including this error is not used. Phase-locked loop (PL
L) controls a high-stability oscillator and divides the frequency of the high-stability oscillator to obtain a stable time information signal.

Hereinafter, the above-mentioned commonly used time-frequency reference signal generator will be described in detail with reference to FIG. This is an artificial satellite equipped with an atomic frequency standard.
(Global Positioning System
m) This is an example when a satellite is used. Radio waves transmitted from the GPS satellites and received by the antenna 1 are transmitted by the GPS
The signal is input to the receiver 2 and demodulated here. G
Since the PS receiver 2 is a well-known and conventional one, a detailed description thereof will be omitted. However, the GPS receiver 2 is generated based on time information transmitted by a GPS satellite and coincides with the Coordinated Universal Time (UTC). A one-second period pulse signal having a timing is output and input to the counter 3.

The operation of the counter 3 will be described with reference to the timing chart of FIG. The role of counter 3 is GPS
The purpose is to measure the number of output pulses of the high stability oscillator 24 generated between the rising edge of the output signal of the receiver 2 and the rising edge of the output signal of the frequency divider 4. The output pulse signal of the frequency divider 4 is controlled in a one-second cycle by a process described later. If the timing of the rising edge of the output of the GPS receiver 2 and the timing of the rising edge of the output of the frequency divider 4 match, the measured value of the counter 3 becomes 0.

The measured value of the counter 3 is stored in the register 5 at the timing of the rising edge of the output pulse signal of the frequency divider 4. Until the measured value of the counter 3 is transferred and stored in the register 5, the measured value one second before is stored in the register 5. Therefore, by using the shift register, the measured value one second before the register 5 is transferred from the register 5 to the register 6 at the same timing as the measured value of the counter 3 is stored in the register 5. The same applies to the measured value two seconds before stored in the register 7. Assuming that the total number of registers for storing the measured values of the counter 3 is N,
Register 8 has a value (N
-1) Save the measurement value of the second.

The sum of the N measured values stored in the registers 5 to 8 is calculated in an adder 9 and multiplied by 1 / N in a 1 / N multiplier 10 to obtain N
An average of the measured values is calculated. Here, the average value output from the 1 / N multiplier 10 indicates a timing difference between the pulse signal output from the GPS receiver 2 and the pulse signal output from the frequency divider 4. The output pulse signal of the frequency divider 4 is converted into a 1 / N cycle by the N frequency divider 11. The output pulse signal of the 1 / N multiplier 10 is stored in the register 12 at the timing of the rising edge of the output pulse signal of the N frequency divider 11.

The register 12 stores the output of the 1 / N multiplier 10 N seconds before the rising edge of the output pulse signal of the N frequency divider 11. The data stored in the register 12 is stored in the register 13 at the rising edge of the output pulse signal of the N frequency divider 11. This is because the registers 12 to 15 are constituted by the same shift registers as the registers 5 to 8, and the data is shifted rightward at the rising edge of the output pulse signal of the N frequency divider 11. It is configured to shift. When the total number of the registers 12 to 15 for storing the output of the 1 / N multiplier 10 is (M + 1), the 1 / N multiplier 10 calculated N × M seconds before the register 12 is stored in the register 15. Output data is saved.

The output data of the registers 12 and 13 is input to a subtracter 16 and a value obtained by subtracting the data of the register 13 from the data of the register 12 is output. The output data of the registers 13 and 14 are input to the subtracter 17, and a value obtained by subtracting the data of the register 14 from the data of the register 13 is output. The same calculation is performed for all M subtractors from the subtractor 16 to the subtractor 19.

The output data from the subtractor 16 to the subtractor 19 is summed by an adder 20 to obtain 1/1 /
It is multiplied by 1 / M in the M multiplier 21. 1 / M multiplier 2
The output of 1 is the difference average value of the measured average values every N seconds stored in the registers 12 to 15. Here, the average difference value output from the 1 / M multiplier 21 is 1 / N
The time change of the data output from the multiplier 10 is shown, whereby the frequency shift between the pulse signal output from the GPS receiver 2 and the pulse signal output from the frequency divider 4 can be known.

If the cycle of the one-second pulse signal output from the GPS receiver 2 matches the cycle of the pulse signal output from the frequency divider 4, the output of the 1 / M multiplier 21 is zero. If the period of the pulse signal output from the frequency divider 4 is longer, the output of the 1 / M multiplier 21 has a positive value. When the period of the pulse signal output from the frequency divider 4 is shorter, the output of the 1 / M multiplier 21 becomes a negative value. That is, the shift of the cycle of the output pulse signal of the frequency divider 4 is calculated by the 1 / M multiplier 2
1 can be known from the output. The oscillation frequency of the high stability oscillator 24 serving as the signal source of the frequency divider 4 is controlled by the voltage output from the D / A converter 23. D
A / A data calculation section 22 calculates frequency correction data based on the output of 1 / M multiplier 21 and calculates D / A converter 2
3 to output a control voltage via the GPS receiver 2, a 1-second pulse signal output from the GPS receiver 2, and a frequency divider 4.
Can be made to have the same frequency and cycle.

As described above, the time-frequency reference signal generator shown in FIG. 5 matches the frequency and cycle of the one-second pulse signal output from the GPS receiver 2 with the pulse signal output from the frequency divider 4. Can. Here, the timing at which the output pulse signal of the frequency divider 4 is generated is determined by the count value of the frequency divider 4 when the GPS receiver 2 generates the one-second periodic pulse signal. By the way, since the count value of the frequency divider 4 at the time of the completion of the frequency synchronization of the PLL is undefined, the timing at which the output pulse signal of the frequency divider 4 is generated is also undefined. That is, it is impossible to perform control such that the output pulse signal of the frequency divider 4 is generated at the same timing as the one-second cycle pulse signal of the GPS receiver 2.

To match this timing, the GPS
A method of resetting the counter of the frequency divider 4 when a one-second periodic pulse signal is generated by the receiver 2 is adopted. But GPS
The one-second periodic pulse signal output from the receiver 2 is a GPS signal.
Fluctuations in the delay caused by propagation from the satellite to the ground,
Due to military or other intentional errors,
The timing of its occurrence is usually unstable. For this purpose, 1 at an arbitrary time output from the GPS receiver 2
Even if the output pulse signal of the frequency divider 4 is reset at the same timing as the second-period pulse signal, the timing of the pulse generation does not always match the accurate one-second period timing, and correct timing is corrected. It is not possible.

Second, the prior art related to the reference time frequency generator will be described. The reference time frequency generator and the above-mentioned time frequency reference signal generator are devices that realize the same functions, although their constituent means are different.

Further, the prior art will be described below with reference to FIGS. The configuration of the reference time frequency generator shown in FIG. 12 is a configuration example in the case of receiving satellite radio waves from a GPS (Global Positioning System) as an artificial satellite equipped with an atomic frequency standard. This configuration includes a satellite radio receiver 102, a reference frequency generator 110, a synthesizer 120, frequency dividers 114 and 112, and a phase comparator 107.

The prior art of the satellite radio receiver 102 and the reference frequency generating means 110 is disclosed in JP-A-08-14616.
There is a "reference frequency generator" disclosed in Japanese Patent Application Laid-Open No. 6-295, and as an example of an internal configuration of the reference frequency generator 110 in the reference frequency generator, as shown in FIG. , An adder, a D / A converter, a frequency divider, a voltage-controlled crystal oscillator (VCXO),
It comprises a frequency converter A, a frequency converter B, and a temperature sensor. In some cases, the frequency converter A is omitted.

According to the reference frequency generator having the above configuration,
Long time constant and digital PID by internal estimation calculation unit
By the feedback control corresponding to the control, the GPS time signal UTC1pp, which is a one-second periodic pulse signal based on the universal time, is used.
s generates a highly accurate and stable reference frequency fref in the short and long term by a control algorithm that is not affected by slight fluctuations caused by radio wave propagation or slight disturbances intentionally given in military terms. Output.

The satellite radio receiver 102 receives a GPS satellite radio wave with an antenna, performs demodulation processing, and is a GPS time signal UTC1pps which is a one-second periodic pulse signal whose timing coincides with the Coordinated Universal Time (UTC). Is output.
Since the configuration of the satellite radio receiver 102 is well known, its internal description is omitted.

The synthesizer 120 is a frequency converter, which receives the above-mentioned reference frequency fref and outputs a constant frequency signal f1 in a simple configuration example of a known circuit of a PLL circuit shown in FIG. ×
(L / M). This frequency signal f1 is output to the outside and used.

A frequency divider 114 shown in FIG. 12 is a variable frequency divider, and receives a control condition of a phase control signal 107a, which will be described later, and changes the frequency division ratio of the reference frequency fref from the synthesizer 120 into three frequency division modes. / L, 1 / (L + 1), 1 / (L
-1) and output.

The frequency divider 112 receives the frequency-divided signal from the frequency divider 114, and outputs a 1-second synchronous pulse signal P1pps having a frequency of 1 / K. However, the frequency divider 114
When the frequency dividing condition is 1 / L, the output synchronization pulse signal P1pps has a period of exactly one second.

The phase comparator 107 has a GPS time signal UT
A phase control signal 107a for controlling the synchronization so that the phase of C1pps matches the phase of the synchronization pulse signal P1pps is output. That is, the GPS output from the satellite radio receiver 102
Upon receiving the time signal UTC 1 pps and the 1-second synchronization pulse signal P 1 pps of the frequency divider 112, the phase difference between the two is detected, and the phase control signal 107 a based on this is converted to the frequency divider 11.
Supply to 4.

In the above-mentioned conventional device configuration, during the temporary synchronization control period until the phase of the GPS time signal UTC 1 pps and the phase of the synchronization pulse signal P 1 pps coincide, the phase between the synchronization pulse signal P 1 pps and the constant frequency signal f 1 is changed. The relationship will be broken.

[0024]

First, with respect to the above-mentioned time-frequency reference signal generator, the problem to be solved by the present invention is to divide the output signal of the oscillator into a time signal. Provided is a time-frequency reference signal generator that solves the above-mentioned problem, in which an indefinite timing is accurately matched with a periodic pulse signal having a time variation such as a time signal transmitted from an artificial satellite equipped with an atomic frequency standard. Things.

In the reference time frequency generator according to the second prior art, there is a use form (application) required to have the above-mentioned phase relationship. As described above, in the prior art, in such a usage form, the phase relationship between the output synchronous pulse signal P1pps and the constant frequency signal f1 is temporarily broken, and in this respect, in this point of view, There are difficulties.
Second, the second problem to be solved by the present invention with respect to the above-described reference time frequency generator is that the phase relationship between both the output synchronous pulse signal and the output constant frequency signal is maintained. It is an object of the present invention to provide a reference time frequency generator capable of performing phase synchronization control of a GPS time signal and a synchronization pulse signal in a state. Another object of the present invention is to provide a reference time generator using a highly stable one second signal obtained from the reference time generator.

[0026]

Means for solving the above-mentioned first problem, which is a time-frequency reference signal generator, are as follows. Claim 1: External synchronization reference pulse signal generator (eg, GP
S receiver) and the output pulse of the high-stability internal pulse signal oscillator 24 to determine the difference between the generation timing of the synchronous reference pulse signal output from the high-stability internal pulse signal oscillator 24 and the frequency of the output pulse signal of the high-stability internal pulse signal oscillator 24. A time-frequency reference signal generator configured to measure as a value converted into a number and increase or decrease the frequency division number based on the measured value was configured.

In a preferred embodiment, the time-frequency reference signal generator further comprises a 1 / N multiplier for outputting a shift in the generation timing of the frequency-divided pulse signal compared with the synchronous reference pulse signal. Then, a time frequency reference signal generator including a phase control frequency divider 25 for temporarily increasing the frequency division number by the output data of the 1 / N multiplier 10 is configured.

A third aspect of the present invention relates to the time-frequency reference signal generator according to the second aspect.
A logic circuit for timing-correcting the pulse output based on the output data of the 1 / N multiplier 10, a counter 54 for counting the number of times of timing correction, and a register 52 for storing the output data of the 1 / N multiplier 10. , A time-frequency reference signal generator having a logic circuit for comparing the data stored in the register 52 with the count value of the counter 54 and correcting the timing of the comparison result, and a comparator 53 for supplying the counter 54 with the logic circuit.

Furthermore, an absolute value converter for separating the output data of the 1 / N multiplier 10 into an absolute value 66 and code parts 55 and 56 in the time frequency reference signal generator according to claim 3. 51, a time-frequency reference signal generator configured to store the absolute value 66 in the register 52 and to correct the timing based on the sign portions 55 and 56.

Here, claim 5: In the time-frequency reference signal generator according to any one of claims 1 to 4, the difference averaging based on the output data of the 1 / N multiplier 10 is performed. And a 1 / M multiplier 21 for calculating 1 / M
A time frequency reference signal generator including a frequency control unit for controlling the oscillation frequency of the high stability internal pulse signal oscillator 24 based on the difference average output from the multiplier 21 is configured.

According to a sixth aspect of the present invention, in the time frequency reference signal generator according to the fifth aspect, the frequency control unit may be 1 /
A time / frequency reference signal generator including a D / A data calculation unit 22 for calculating frequency correction data based on the output of the M multiplier 21 and a D / A converter 23 for converting the frequency correction data into a voltage is configured. Claim 7: In the time-frequency reference signal generator according to claim 6, the output data of the 1 / N multiplier 10 is input to the D / A data calculation unit 22, and the frequency offset data for the timing correction is normally output. A time frequency reference signal generator to be superimposed on the output frequency correction data is configured.

The means for solving the second problem, that is, the reference time frequency generator, is as follows. First
In order to solve the second problem, according to the configuration of the present invention, in the reference frequency generator synchronized with the external reference pulse signal, the synchronous pulse signal P1pps having the same cycle synchronized with the phase of the external reference pulse signal is provided. And a means for generating a constant frequency signal f1 having a predetermined fixed pulse number or a fixed frequency during a pulse period of the synchronization pulse signal P1pps. . According to the above invention, the output synchronous pulse signal P1pps and the output constant frequency signal f
While maintaining the phase relationship between the two, the GP
A reference time frequency generator capable of controlling the phase synchronization between the S time signal UTC 1pps and the synchronization pulse signal P1pps can be realized.

Secondly, in order to solve the second problem, in the configuration of the present invention, a high-precision reference signal is slowly followed by an external reference pulse signal (for example, a GPS time signal UTC 1 pps in units of one second). A reference frequency generator for generating and outputting a frequency fref includes means for generating a synchronous pulse signal P1pps having the same cycle synchronized with the phase of an external reference pulse signal. Constant frequency signal f with constant frequency
There is a reference time frequency generating device characterized by comprising means for generating a reference time frequency.

The reference time frequency generator described above is characterized in that the external reference pulse signal is a GPS time signal UTC 1pps in units of one second, which is an absolute time signal output from the satellite radio receiver 102. .

FIG. 7 shows means for solving the second problem. Third, in order to solve the second problem, in the configuration of the present invention, the means for generating a frequency signal f1 having a predetermined fixed pulse number or a fixed frequency during the pulse period of the synchronization pulse signal P1pps includes: A frequency generator 110, a reference phase shifter 130, a frequency converter, a frequency divider 112, and a phase comparator 107;
The reference frequency generating means 110 generates and outputs a predetermined reference frequency fref in synchronization with an external reference pulse signal (for example, a GPS time signal UTC 1 pps in units of one second), and the reference phase shift means 130 Receiving the phase control signal 107a, outputs a phase-shifted frequency signal 130a obtained by phase-shifting the reference frequency fref by a predetermined amount, and outputs the frequency-shifted signal (for example, the synthesizer 120).
Generates and outputs a constant frequency signal f1 having a fixed number of pulses or a constant frequency, which is frequency-converted in a predetermined manner in synchronization with the phase shift frequency signal 130a.
Receives the constant frequency signal f1 and outputs a synchronization pulse signal P1pps obtained by dividing the pulse frequency into the same pulse period as the pulse period of the external reference pulse signal. The phase comparator 107 outputs the synchronization pulse signal P1pps and the external reference pulse signal. The reference time frequency generator described above is characterized in that a phase difference from a pulse signal is detected and a phase control signal 107a for correcting the detected phase difference is supplied to a reference phase shift means 130.

The means for generating the synchronization pulse signal P1pps synchronized with the phase of the reference pulse signal includes a frequency signal f1 having a predetermined fixed pulse number or a predetermined frequency.
The reference time frequency generator described above is characterized in that it receives the constant frequency signal f1 from the means for generating the reference time signal and divides the frequency into the same pulse cycle as the pulse cycle of the external reference pulse signal. The reference phase shift means 130 includes a frequency multiplying means (for example, a multiplier 115 and a bandpass filter 1).
16) and the reference time frequency generator described above, which includes a frequency divider 117.

FIG. 9 shows the means for solving the second problem. Fourth, in order to solve the second problem, in the configuration of the present invention, the means for generating the frequency signal f1 having a predetermined fixed pulse number or a fixed frequency during the pulse period of the synchronization pulse signal P1pps is based on a reference signal. The reference frequency generator 110 includes a frequency generator 110, a frequency converter (eg, a synthesizer 120b) including a variable frequency divider, a frequency divider 112, and a phase comparator 107.
Generates and outputs a predetermined reference frequency fref in synchronization with an external reference pulse signal (for example, a GPS time signal UTC 1 pps in units of one second), and a frequency conversion means (for example, a synthesizer 120b) including the variable frequency dividing means performs phase comparison. Container 107
Receiving the phase control signal 107a from the
frequency dividing means (for example, frequency divider 1
22) to generate and output a constant frequency signal f1 having a fixed pulse number or a fixed frequency which is frequency-converted in a predetermined manner in synchronization with the reference frequency fref. The frequency divider 112 receives the constant frequency signal f1 and receives an external signal. And outputs a synchronous pulse signal P1pps divided into the same pulse period as the pulse period of the reference pulse signal, and the phase comparator 107 detects a phase difference between the synchronous pulse signal P1pps and an external reference pulse signal, and performs detection. Phase control signal 10 for correcting the phase difference
7a is supplied to the frequency dividing means (for example, the frequency divider 122) capable of performing a predetermined phase shift.

The frequency conversion means provided with the variable frequency dividing means includes means for using DDS, receiving the phase control signal 107a from the phase comparator 107, and switching the phase addition data 141 of the phase accumulator. There is a reference time frequency generator described above.

The means for solving the second problem, that is, the reference time generation device using the reference time frequency generation device is as follows. FIG. 14 shows a solution according to the reference time generation device. The reference timing signal UTC 1 ppsA from the satellite radio receiver 102 is supplied to the reference frequency generator 4.
High-precision 1
Upon receiving the output of the second signal UTC1ppsB, the frequency is divided in a predetermined manner to generate time data (for example, hour-minute-second data Td3).
In synchronization with the second signal UTC1ppsB, the time data divided in a predetermined manner or the time data and the one-second signal UTC
There is the reference time generation device described above, which outputs 1 ppsB to the outside.

FIG. 15 shows a solution relating to the reference time generator. Also, the reference timing signal UTC 1 ppsA from the satellite radio receiver 102 is supplied to the reference frequency generator 4.
High-precision 1
Upon receiving the output of the second signal UTC1ppsB, the signal is frequency-divided to generate time data (for example, hour-minute-second data Td3). First, when satellite radio waves are received normally, the satellite radio receiver 10
Second, it outputs the time data Td1 received from the external device to an external device, and secondly outputs the time data (for example, hour-minute-second data Td3) generated by dividing the frequency to a predetermined value when satellite radio waves cannot be received. There is the reference time generation device described above.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention for a time-frequency reference signal generator is as follows. In FIG. 5, the difference between the generation timing of the one-second cycle pulse signal output from the GPS receiver 2 and the generation timing of the pulse signal output from the frequency divider 4 is represented by a value converted into the number of output pulses of the high stability oscillator 24. The output data of the 1 / N multiplier 10 is shown. As described above, the frequency divider 4 shown in FIG. 5 is a variable frequency divider, and the frequency division number is temporarily increased or decreased by the output data of the 1 / N multiplier 10, that is, the necessary timing correction amount. By doing so, it is possible to match the generation timing of the pulse signal output from the GPS receiver 2 with a cycle of 1 second and the pulse signal output from the frequency divider 4 in FIG.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention for a time-frequency reference signal generator is as follows. An embodiment of the present invention will be described with reference to FIGS. FIG. 2 shows the configuration of the phase control frequency divider 25 used in FIG. 1, which is an example in which timing correction is performed by a 4-frequency divider using a binary counter. FIG. 3 shows flip-flops 63 and 64.
5 is an operation timing chart of the binary counter constituted by the following.

The output data of the 1 / N multiplier 10 is converted into an absolute value 66 by an absolute value
To save. In the absolute value converter 51, 1 /
The sign portion is separated from the output data of the N multiplier 10, and the output 56 is set to a high level when the value is a positive value, that is, when the timing is delayed. If the value is a negative value, that is, if the timing is advanced, the output 55 is set to the high level. The outputs 55 and 56 of the absolute value converter 51 are at a low level when timing correction is not performed.

The output 55 is stored in the flip-flop 58 at the rising edge of the output signal of the N frequency divider 11, and the Q output goes high. The output 56 is stored in the flip-flop 57 at the rising edge of the output signal of the N divider 11, and the Q output becomes high level. This means that the output data of the 1 / N multiplier 10 is stored in the register 12 and, at the same time, the timing correction operation is started.
The Q outputs of the flip-flops 57 and 58 are at a low level when no timing correction is performed.

FIG. 3 is an operation timing chart of the binary counter constituted by flip-flops 63 and 64.
Shown in During the timing delay when the Q output of the flip-flop 57 is at the high level, when the value of the binary counter formed by the flip-flops 63 and 64 becomes 3, that is, the output of the AND circuit 65 becomes the high level. When this happens, the J and K inputs of the flip-flop 63 become low level, the value of the binary counter becomes 1 after 3 and the pulse output of the frequency divider 25 corrects the timing shift by one period of the oscillator 24. Is performed. Q of flip-flop 58
During the timing advance in which the output is at the high level, when the value of the binary counter formed by the flip-flops 63 and 64 becomes 0, the J and K inputs of the flip-flop 63 become the low level, and the count value becomes 0 continues for two periods, and the pulse output of the frequency divider 25 is
Is corrected for one cycle.

The number of times the timing correction has been performed is determined by counting the edges of the J and K input signals of the flip-flop 63 to the counter 54.
Can be measured and determined. When the count of the counter 54 matches the value of the register 52,
When the necessary number of timing corrections are completed, the comparator 5
3 outputs a clear signal, and the counter 54 and the flip-flops 57 and 58 return to the initial state and enter the normal operation mode.

Unlike the method of resetting the frequency divider 4 by a one-second pulse signal output from the GPS receiver 2 at an arbitrary time, the synchronization deviation is corrected by the averaged data. The output data of the 1 / N multiplier 10 after the correction becomes substantially 0, and the timing can be accurately adjusted to the one-second cycle. Although the embodiment of FIG. 1 uses a one-second cycle pulse signal output from the GPS receiver 2 as a time reference signal, if the reference signal is a periodic pulse signal, another external synchronization reference pulse signal is generated. A one-second pulse signal generated by the vessel can also be used.

The method of correcting the timing by presetting an initial value corresponding to the timing shift in the N-ary counter used in the frequency divider is such that the continuity of the operation of the N-ary counter is maintained in terms of timing. Although it is difficult, the method shown in FIG. 1 is capable of switching between the operation of performing the timing correction and the operation of not performing the operation while maintaining the continuity of the operation of the N-ary counter, and performing the required amount of timing correction quickly. It is advantageous.

Another embodiment will be described. The time-frequency reference signal generator shown in FIG.
Can be corrected by using the cycle of the pulse signal that generates the minimum resolution as the minimum resolution.
In order to perform timing correction with higher accuracy, a method disclosed in Japanese Patent Application No. 9-221384 is employed. An embodiment using this method is shown in FIG.

The time frequency reference signal generator of FIG.
The output data of the 1 / N multiplier 10, which is the data indicating the difference between the generation timing of the pulse signal of 1 second cycle output from the S receiver 2 and the generation timing of the pulse signal output from the frequency divider 4,
The data is also input to the D / A data calculation unit 22. Japanese Patent Application No. 9
The principle of the reference signal generator shown in -221384 is to shift the phase of the output of the frequency divider 25 by adding an offset to the frequency for a very short time, thereby correcting the timing shift. If the synchronization of the output pulse signal of the frequency divider 25 is advanced, the D / A data calculation unit outputs a control voltage from the D / A converter 23 in which the oscillation frequency of the oscillator 24 decreases for a very short time. Reference numeral 22 superimposes frequency offset data for timing correction on frequency correction data that is normally output. When the synchronization of the output pulse signal of the frequency divider 25 is delayed, the D / A data calculating unit outputs a control voltage from the D / A converter 23 in which the oscillation frequency of the oscillator 24 increases for a very short time. Reference numeral 22 superimposes frequency offset data for timing correction on frequency correction data that is normally output (for details, refer to Japanese Patent Application No. 9-221384).

Although the configuration shown in FIGS. 1 and 4 has been described with a specific example realized by a circuit, it may be realized by an arithmetic processing by an arithmetic program of a CPU if desired. That is, registers 5 to 8, adder 9, 1 / N multiplier 10, N divider 11, registers 11 to 15, subtractors 16 to 19, adder 20, 1 / M multiplier 21, D / A data Calculation unit 22
Are replaced with the arithmetic program of the CPU and the processing is executed. Therefore, the data from the counter 3 is received and processed in a predetermined manner in the same manner as described above.
The same data as that of the N multiplier 10 is supplied, and the D / A converter 2
3 is supplied with the frequency correction data of the calculation result.

The second embodiment, which is an embodiment of the reference time frequency generator, is as follows. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings together with examples.

An embodiment of the present invention will be described below with reference to FIGS. Elements corresponding to the conventional configuration are denoted by the same reference numerals. As shown in FIG. 7, a configuration example of the present invention includes a satellite radio receiver 102, a reference frequency generation unit 110,
A reference phase shift unit 130, a synthesizer 120,
It comprises a frequency divider 112 and a phase comparator 107. In this configuration, except for the reference phase shift means 130, the other components are the same as those of the related art. However, the frequency divider 112 is 1 / (L × K)
And the division of.

The reference phase shift means 130 variably controls the phase of the reference frequency fref. That is, in response to the control condition of the phase control signal 107a from the phase comparator 107, first, when the phase of the GPS time signal UTC 1pps matches the phase of the synchronization pulse signal P1pps, the reference frequency fref is directly used as the phase shift frequency. The signal 130a is supplied to the synthesizer 120 as a signal 130a. Second, when the phase of the synchronization pulse signal P1pps is delayed, the phase shift frequency signal 130 obtained by advancing the output phase of the reference frequency fref by a predetermined phase.
a to the synthesizer 120. Third, when the phase of the synchronization pulse signal P1pps is advanced, the reference frequency fref
Phase shift frequency signal 13 with the output phase of
0a is supplied to the synthesizer 120. As a result, the phase of the synchronization pulse signal P1pps output from the frequency divider 112 eventually coincides with the GPS time signal UTC1pps.

According to the configuration of the present invention described above, the G
A means for synchronizing the phase with the PS time signal UTC 1 pps, and a constant frequency signal f1 output from the synthesizer 120;
Is provided with a means for dividing the frequency by the frequency divider 112 at a fixed frequency division ratio.
A constant phase relationship is maintained between pps and the constant frequency signal f1, and in this state, an advantage is obtained in which phase synchronization control becomes possible.

FIG. 8A shows a first example of a specific configuration of the reference phase shift means 130. This configuration is a multiplier 115
, A band-pass filter 116 and a frequency divider 117. This is a means for equivalently shifting the phase by a very small amount by temporarily changing the frequency of the phase shift frequency signal 130a to be output. The multiplier 115 multiplies the reference frequency fref by N and outputs the same.
Reference numeral 6 denotes a filter that passes and outputs only the frequency component multiplied by N, and a frequency divider 117 is a variable frequency divider, which has three frequency division modes 1 / N and 1/3 depending on the control condition of the phase control signal 107a.
The phase shift frequency signal 130a is divided into one of (N + 1) and 1 / (N-1) to output a small amount of phase shift.

FIG. 8B shows a second example of the specific structure of the reference phase shift means 130. This configuration has a configuration in which the frequency multiplier 115 is replaced by frequency conversion means configured by a PLL circuit instead of the multiplier 115. The operation is the same as that in FIG.

The configuration of the present invention is not limited to the above embodiment. For example, as shown in the internal configuration example of the synthesizer 120b in FIG. 9, the reference phase shift means 130 shown in FIG. 7 is deleted, and one of the frequency dividers 122 is replaced by a variable frequency divider, and the control condition of the phase control signal 107a is changed. In response, the signal is output in the form of three frequency divisions and supplied to the phase comparator 123. This also enables the phase shift of the output constant frequency signal f1.

FIG. 10 shows another example of the internal configuration of the synthesizer 120b shown in FIG. This configuration is a DDS
(Direct Digital Synthesizer), which comprises three phase addition data 141 and a multiplexer (MUX) 142, and switches the phase addition data 141 to be supplied to the phase accumulator in response to the control condition of the phase control signal 107a. Thus, it is possible to shift the phase of the output constant frequency signal f1. In this case, since the constant frequency signal f1 output from the DDS has a frequency that is as low as about several tenths of the input reference frequency fref, a frequency multiplying means may be provided at the output terminal if desired.

An embodiment of an application configuration for generating a reference time, which is the third problem, is as follows. This generates an accurate reference time using the reference frequency generator described above. This will be described. This configuration, as shown in FIG.
A satellite radio receiver 102, a reference frequency generator 400,
Time data generating means 380 and switching means (MUX) 3
82, a real-time clock 385, and a CPU 39
0 and I / F 395. With this configuration, the reference frequency generation unit 400 includes the reference frequency generation unit 110 shown in FIG.
And the frequency converter B in the reference frequency generating means 110
UTC 1 ppsB, which is a high-stable 1 second signal output from the PC, is used.

The time data generating means 380 comprises, for example, two 1/60 frequency dividers and a 1/24 frequency divider. High-accuracy and stable 1-second signal UTC from reference frequency generator 400
Receiving 1 ppsB, it divides by 1/60 and outputs data per second, further divides by 1/60 and outputs data by minute, further divides by 1/24 and outputs data by time I do. The time / minute / second data Td3 is supplied to the MUX 382.

The MUX 382 is a two-input one-output type selector. The data from the time data generating means 380 is received at one input terminal, the time data Td1 from the satellite radio receiver 102 is received by the CPU, and the converted time data Td2 is received at the other input terminal. Is output to the I / F 395. Output selection control
When satellite radio waves cannot be received normally, hour / minute / second data Td3 is output from time data generating means 380.

The I / F 395 converts the signal into a predetermined signal form and outputs it. For example, it outputs parallel time data Td5 buffered as it is in the received data form or time data Td5 converted into a serial data string. The 1-second pulse signal 1 pps to be output is a 1-second high-precision reference pulse signal obtained by buffering the 1-second signal UTC 1 ppsB from the reference frequency generator 400.
When outputting the time data Td5, the time data Td5 may be output at a timing synchronized with the one-second pulse signal 1 pps, so that the timing of the one-second pulse signal 1 pps may be given. The signal output from the I / F 395 has three output forms: the time data Td5 and the 1-second pulse signal 1 pps, only one time data Td5, or only the other 1-second pulse signal 1 pps. Corresponding to the desired output mode.

As another configuration means, there is a configuration example shown in FIG. In this configuration example, the time data generation unit 380 and the circuit function of the MUX 382 in the configuration of FIG. 14 are deleted, and instead, the one-second signal UTC1ppsB from the reference frequency generation unit 400 is received at the interrupt input terminal of the CPU 390, and the CPU 390 Realizes time counting similar to that described above by software processing, and selects either the calculated time data or the time data Td1 from the satellite radio receiver 102 and outputs it to the I / F 395. . This configuration means can also be used.

Incidentally, the real-time clock 385 shown in FIGS. 14 and 15 is a time information generating means used supplementarily, and may be deleted as required.

According to the configuration of the present invention, the stability of the self-running state of the high-stability oscillator inside the reference frequency generation unit 400 is high even after the state in which satellite radio waves cannot be received.
By using a configuration in which the second signal UTC1ppsB can be used, time information or 1 pps of 1-second pulse signal can be continuously output to an external device. As a result, it is possible to supply high-precision time information for a long time. . Further, even when the reception is temporarily disabled, the reference frequency generator 40
Since the 1-second signal UTC 1 ppsB with high accuracy and high stability is generated from 0, there is also obtained an advantage that it can be used without any practical problem.

[0067]

The effects of the invention on the time-frequency reference signal generator, which is the first problem, are as follows. According to the present invention, the difference between the generation timing of the one-second cycle pulse signal output from the external synchronization reference pulse signal generator such as the GPS receiver and the generation timing of the pulse signal output from the frequency divider is improved by the high stability oscillator. The output data of the 1 / N multiplier is shown as a value converted to the number of output pulses of the 1 / N multiplier. Here, the frequency divider is a variable frequency divider, and the frequency of division is temporarily divided by the output data of the 1 / N multiplier. That is, by adopting a configuration that increases or decreases by the necessary timing correction amount, the generation timing of the 1-second cycle pulse signal output from the external synchronization reference pulse signal generator matches the generation timing of the pulse signal output from the frequency divider. Can be done.

The operation for performing the timing correction and the operation for not performing the timing correction while maintaining the continuity of the operation of the N-ary counter can be switched, and the required amount of timing correction can be quickly performed.

The effect of the invention on the reference time frequency generator, which is the second problem, is as follows. As described above, according to the present invention, the frequency divider 112 is provided with a means for phase-synchronizing the GPS time signal UTC 1 pps from the satellite radio wave, and the frequency divider 112 divides the constant frequency signal f1 output from the synthesizer 120 at a fixed frequency division ratio. With this configuration, there is an advantage that the phase synchronization control can be performed while maintaining a constant phase relationship between the output synchronization pulse signal P1pps and the constant frequency signal f1. . Therefore, there is an advantage that the reference time frequency generating device of the present invention can be used in a usage form requiring the above-mentioned phase relationship.

The effect of the present invention on the applied configuration for generating the reference time, which is the third problem, is as follows. As described in the above embodiment, the reference frequency generator of the present invention
Excellent frequency stability was achieved by using a signal source that contains a large amount of short-term phase fluctuations such as satellite radio waves or subordinate synchronous networks but is stable in the long term as a reference time signal. If the reference frequency generator uses a means that can correct the fluctuation of the oscillation frequency due to the temporal change of the free-running oscillation frequency of the crystal oscillator after the state in which the reference time signal cannot be received, a longer time than ever before Since a stable oscillation frequency can be output, there is a great advantage that excellent frequency stability can be maintained for a long time. In addition, the reference time generation device using this also has an advantage that it is possible to supply highly accurate time information for a long time. Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an embodiment of a time-frequency reference signal generator.

FIG. 2 is a diagram illustrating a phase control frequency divider according to the time frequency reference signal generator.

FIG. 3 is an operation timing chart of the phase control frequency divider of FIG. 2 according to the time frequency reference signal generator.

FIG. 4 is a diagram illustrating another embodiment of the time-frequency reference signal generator.

FIG. 5 is a diagram for explaining a timing correction circuit using an artificial satellite equipped with an atomic frequency standard, according to the time frequency reference signal generator.

FIG. 6 is a timing chart illustrating the operation of the counter of FIG. 5 according to the time-frequency reference signal generator.

FIG. 7 is a configuration example of a reference time frequency generator according to the present invention relating to a reference time frequency generator.

FIG. 8 is a configuration example of a reference phase shift means according to the present invention relating to a reference time frequency generator.

FIG. 9 is a configuration example of a synthesizer of the present invention relating to a reference time frequency generator.

FIG. 10 is another configuration example of the synthesizer according to the present invention relating to the reference time frequency generator.

FIG. 11 is a configuration example of a synthesizer according to a reference time frequency generator.

FIG. 12 is a configuration example of a conventional reference time frequency generator related to a reference time frequency generator.

FIG. 13 is an example of an internal configuration of a reference frequency generating means according to the reference time frequency generator.

FIG. 14 is a configuration example of a reference time generation device according to the present invention related to the reference time generation device.

FIG. 15 is another configuration example of the reference time generation device according to the present invention relating to the reference time generation device.

[Explanation of symbols]

 2 GPS Receiver 10 1 / N Multiplier 21 1 / M Multiplier 22 D / A Data Calculator 23 D / A Converter 24 High Stability Internal Pulse Signal Oscillator 25 Phase Control Divider 51 Absolute Value Converter 52 Register 53 comparator 54 counter 102 satellite radio receiver 107, 123 phase comparator 110 reference frequency generating means 112, 114, 117, 122 frequency divider 115 multiplier 116 bandpass filter 120, 120b synthesizer 130 reference phase shift means 141 phase addition Data 142 Multiplexer (MUX) 380 Time data generating means 382 Switching means (MUX) 385 Real-time clock 390 CPU 395 I / F 400 Reference frequency generator

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03L 7/08 H03L 7/06 H 7/26 7/08 N

Claims (17)

[Claims] 1. A high-stability internal pulse signal that is generated by synchronizing a synchronization reference pulse signal output from an external synchronization reference pulse signal generator with a frequency-divided pulse signal output from a high-stability internal pulse signal oscillator. A time-frequency reference signal generator which measures a value converted into the number of output pulses of a pulse signal oscillator and increases / decreases a frequency division number based on the measured value. 2. The time-frequency reference signal generator according to claim 1, further comprising a 1 / N multiplier for outputting a shift in the generation timing of the frequency-divided pulse signal as compared with the synchronous reference pulse signal. A time frequency reference signal generator comprising a phase control frequency divider for temporarily increasing or decreasing the frequency division number by the output data of a / N multiplier. 3. The time-frequency reference signal generator according to claim 2, wherein the phase control frequency divider corrects a pulse output of the 1 / N multiplier based on output data of the 1 / N multiplier. A counter for counting the number of corrections, a register for storing output data of the 1 / N multiplier, a logic circuit for comparing the stored data of the register with the count value of the counter, and a logic circuit for performing timing correction of the comparison result and a comparator for supplying the counter to the counter A time-frequency reference signal generator characterized by having: 4. The time frequency reference signal generator according to claim 3, further comprising: an absolute value converter for separating output data of the 1 / N multiplier into an absolute value and a sign part, wherein the absolute value is stored in a register. A time-frequency reference signal generator that stores and corrects timing based on a code part. 5. The time-frequency reference signal generator according to claim 1, wherein 1 / M multiplication for obtaining an average of the difference based on output data of a 1 / N multiplier. A frequency control unit for controlling an oscillation frequency of a high-stability internal pulse signal oscillator based on a difference average output from a 1 / M multiplier. . 6. The time-frequency reference signal generator according to claim 5, wherein the frequency control unit calculates a frequency correction data based on an output of the 1 / M multiplier, and the frequency correction data. A time / frequency reference signal generator, comprising: a D / A converter for converting a signal into a voltage. 7. The time-frequency reference signal generator according to claim 6, wherein the output data of the 1 / N multiplier is D / A
A time-frequency reference signal generator, which is input to a data calculator and superimposes frequency offset data for timing correction on frequency correction data that is normally output. 8. A reference frequency generator which synchronizes with an external reference pulse signal, comprising: means for generating a synchronous pulse signal of the same cycle synchronized with the phase of the external reference pulse signal; A means for generating a constant frequency signal having a predetermined constant pulse number or constant frequency. 9. A reference frequency generator for generating and outputting a high-precision reference frequency fref in accordance with an external reference pulse signal, wherein a synchronous pulse signal having the same cycle synchronized with the phase of the external reference pulse signal is generated. And a means for generating a constant frequency signal having a constant number of pulses or a constant frequency during a pulse period of the synchronization pulse signal. 10. An external reference pulse signal is a one-second GP signal which is an absolute time signal output from a satellite radio receiver.
10. The reference time frequency generating device according to claim 8, wherein the reference time frequency generating device is an S time signal. 11. A means for generating a frequency signal having a predetermined fixed number of pulses or a fixed frequency during a pulse period of a synchronous pulse signal includes a reference frequency generating means, a reference phase shift means, a frequency converting means, a frequency dividing means, And a phase comparator. The reference frequency generating means generates and outputs a predetermined reference frequency fref in synchronization with an external reference pulse signal, and the reference phase shift means outputs a phase control signal from the phase comparator. Receiving the reference frequency fref and outputting a phase-shifted frequency signal obtained by phase-shifting the reference frequency fref by a predetermined number. The frequency divider generates and outputs a constant frequency signal, and the frequency divider receives the constant frequency signal and divides the frequency into the same pulse cycle as the pulse cycle of the external reference pulse signal. Outputting a pulse signal, the phase comparator detects a phase difference between the synchronization pulse signal and an external reference pulse signal, and supplies a phase control signal for correcting the detected phase difference to the reference phase shift unit. The reference time frequency generator according to claim 8 or 9, wherein: 12. A means for generating a synchronization pulse signal synchronized with the phase of a reference pulse signal, comprising: receiving a constant frequency signal from a means for generating a frequency signal having a predetermined fixed pulse number or a fixed frequency; 10. The reference time frequency generating device according to claim 8, wherein the frequency is divided into the same pulse period as the pulse period of the signal. 13. The reference time frequency generator according to claim 11, wherein the reference phase shift means includes a frequency multiplying means and a frequency divider. 14. A means for generating a frequency signal having a predetermined fixed number of pulses or a fixed frequency during a pulse period of a synchronous pulse signal includes: a reference frequency generating means; a frequency converting means including variable frequency dividing means; And a phase comparator. The reference frequency generation means generates and outputs a predetermined reference frequency fref in synchronization with an external reference pulse signal. The frequency conversion means including the variable frequency dividing means includes a phase comparator. A frequency dividing means for receiving the phase control signal from the base station and shifting the reference frequency fref to a predetermined phase, and synchronizing with the reference frequency fref to convert the frequency into a predetermined pulse number or a fixed frequency signal. The frequency divider receives the constant frequency signal, and outputs a synchronous pulse signal divided into the same pulse cycle as the pulse cycle of the external reference pulse signal. The phase comparator detects a phase difference between the synchronization pulse signal and an external reference pulse signal, and supplies a phase control signal for correcting the detected phase difference to the frequency dividing unit capable of performing a predetermined phase shift. The reference time frequency generator according to claim 8 or 9, wherein: 15. The frequency conversion means provided with a variable frequency dividing means, using DDS, receiving means for receiving a phase control signal from a phase comparator and switching means for switching phase addition data of a phase accumulator. Reference time frequency generator as described. 16. A high-precision one-second signal generated by a reference frequency generation unit receiving a reference timing signal from a satellite radio receiver and gently following the synchronization, and dividing the time into predetermined time data. 2. The reference time generation device according to claim 1, wherein the reference time generation device outputs the time data divided in a predetermined manner to the outside in synchronization with the one-second signal. 17. A high-precision one-second signal generated by a reference frequency generation unit receiving a reference timing signal from a satellite radio receiver and gently following synchronously, and dividing the clock signal to a predetermined frequency to generate time data First, when satellite radio waves are received normally, the time data received from the satellite radio receiver is output to an external device. Secondly, when satellite radio waves cannot be received, frequency division is performed in a predetermined manner. 2. The reference time generation device according to claim 1, wherein the generated time data is output to the outside.