JP2008109589A - Signal generating apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a high-precision frequency-variable rectangular pulse signal while suppressing generation of jitter in a frequency-variable signal generating apparatus using a general-purpose DDS (direct digital synthesizer). <P>SOLUTION: The frequency-variable signal generating apparatus comprises a DDS 1 which outputs an analog signal of a frequency to be changed in accordance with a setting value; a comparator 3 which generates a first rectangular pulse signal of the frequency from the analog signal; a programmable frequency divider 41 which outputs a second rectangular pulse signal frequency-dividing the first rectangular pulse signal in a set frequency dividing ratio; and a control unit 4. When changing the frequency to a higher frequency domain side, the first rectangular pulse signal is defined as an output signal So for the frequency divider. When changing the frequency to a lower frequency domain side, the setting value is changed and controlled to a value of the frequency dividing ratio multiple for the DDS, the first rectangular pulse signal having a frequency of the frequency dividing ratio multiple is generated, and the second rectangular pulse signal of the relevant frequency divided in the relevant frequency dividing ratio in the frequency divider is defined as the output signal So. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a signal generator, and more particularly to a signal generator that uses a signal generator having an external frequency modulation function to suppress the occurrence of jitter in the output and generate a highly accurate frequency variable rectangular pulse signal. Is.

  FIG. 7 shows the principle of generating a rectangular pulse signal (clock signal) of a frequency variable rectangular wave by a sine wave output direct digital synthesizer (hereinafter referred to as DDS).

  As shown in FIG. 7, this type of signal generator includes a DDS1 having a phase increment register 11, a phase accumulator 12, a waveform memory 13, a digital-analog (D / A) converter 14, a low-pass filter (LPF). 2) It is composed of a comparator 3. In this signal generator, the sine wave signal Sa output from the DDS 1 is converted into a rectangular wave clock signal Sd and output.

The phase increment value register 11 stores the phase change amount (hereinafter referred to as FTW) of the output signal per clock cycle. The value of this FTW by storing change to the register, it is possible to change the frequency f _d of the sine wave signal Sa output from DDS1.

  The phase accumulator 12 cumulatively calculates the value stored in the phase increment value register 11, that is, the set FTW value every clock cycle. The result of the cumulative calculation functions as an address pointer for the waveform memory 13. The waveform memory 13 stores sine wave sample data, and outputs the sample data at the address designated by the address pointer to the D / A converter 14. The D / A converter 14 converts the sample data output from the waveform memory 13 into an analog amount of voltage or current.

  The LPF 2 acts to remove unnecessary frequency components included in the output of the D / A converter 14 and increase the spectrum purity of the sine wave signal Sa.

The sine wave signal output from the LPF 2 is compared with a predetermined reference value by the comparator 3 and converted into a rectangular wave clock signal, which becomes an output signal Sd as a frequency variable signal generator. The frequency of the output signal Sd is the same as the frequency _{f d} of the sine wave signal Sa output from DDS1.

  When a rectangular wave clock signal is generated by the frequency variable signal generator according to the method described above, a rectangular wave pulse signal is generated from a sine wave signal using a comparator as shown in FIG. In general, when the frequency of the output rectangular wave signal is changed to the high frequency region side, jitter does not easily appear, so that the problem of jitter generation does not occur. However, as the frequency of the rectangular wave pulse signal is changed to the low frequency region side, jitter increases in the output rectangular wave pulse signal.

  By the way, when the frequency variable signal generator incorporating the above-described DDS is used in, for example, a measuring instrument or the like, the specification for jitter is in the entire frequency range as a request from an application mounted on the measuring instrument or the like. In this case, it is necessary to be several tens of ps rms or less, or 1 / 10,000 or less of the oscillation period. In a frequency variable signal generator incorporating a DDS used in the past, the frequency range satisfying the specifications for jitter varies depending on the circuit configuration, but is, for example, about 100 MHz to 50 MHz, and at a frequency of 50 MHz or less, The required jitter specifications are not met. Therefore, it is necessary to suppress an increase in jitter even when the frequency of the rectangular wave pulse signal is 50 MHz or less.

  Therefore, as a countermeasure against the problem that the jitter increases, a signal generator using a DDS that generates a digital clock signal with low jitter so as to generate a signal with high spectral purity has been proposed (for example, , See Patent Document 1).

  In this proposed signal generator, the clock signal has a variable frequency and is controlled by a program so that an arbitrary waveform signal can be generated. The DDS used in this signal generator generates a sine wave signal using a high resolution, high sampling rate D / A converter, and converts the sine wave signal into a digital clock. The DDS signal generator architecture generates a data stream using a CMOS circuit and supplies it to a high sample rate D / A converter to generate a low jitter clock signal.

JP 2005-195585 A

  However, in the proposed signal generator, in order to generate a low jitter clock signal, a circuit program inside the DDS must be changed to prepare a control program for signal generation. Therefore, when trying to realize a low-jitter clock signal, a specially designed DDS is used, and when an existing and general-purpose DDS is used, a low-jitter clock signal can be generated. Can not.

  Therefore, the present invention is a signal generator that can use a general-purpose DDS and generates a variable-frequency rectangular pulse signal, which suppresses the occurrence of jitter in the output and is a highly accurate variable-frequency rectangular pulse signal. It is an object of the present invention to provide a signal generator that generates the above.

  In order to solve the above problems, in the signal generator according to the present invention, signal generating means for outputting an analog signal having a frequency changed according to a set value, and a first having the frequency based on the analog signal. Pulse signal generating means for generating a rectangular pulse signal; frequency dividing means for outputting a second rectangular pulse signal obtained by dividing the first rectangular pulse signal by a set frequency dividing ratio; and When the frequency is changed, control is performed using the first rectangular pulse signal as an output signal. When the frequency is changed to the low frequency region side, the set value is multiplied by the frequency division ratio with respect to the signal generating means The first rectangular pulse signal having the frequency multiplied by the division ratio is output from the pulse signal generation means by changing the value to the value, and the frequency division means is set to the frequency division ratio and has the frequency. And control means for performing control of the output signal the serial second rectangular pulse signal, comprising a.

  The signal generation means is a direct digital synthesizer having a program register for outputting the analog signal having a frequency according to a set phase increment value and setting the frequency, and the frequency dividing means is a preset A programmable frequency divider composed of a binary counter with frequency, wherein the control means determines a phase increment value corresponding to the frequency and sets the phase increment value in the program register; And a frequency-frequency division ratio conversion means for determining a frequency division ratio of the programmable frequency divider corresponding to the frequency.

  The control means includes time measuring means for measuring a time when the frequency of the second rectangular pulse signal changes from the determined setting of the phase increment value, and based on the measured time, the phase increment by the program register Synchronizing the setting of the value and the setting of the dividing ratio of the programmable dividing means, and controlling the phase synchronization of the second rectangular pulse signal before and after the change of the dividing ratio accompanying the change of the frequency; did.

  Furthermore, the control means includes modulation waveform storage means for storing the frequency for each modulation rate, and causes the frequency-phase increment value conversion means and the frequency-frequency division ratio conversion means to supply the frequency. did.

  In addition, when the frequency is changed to the high frequency region side, the control unit sets the frequency dividing unit to not perform the frequency division, and the first rectangular pulse signal is set to the second frequency of the frequency. Control was performed using a rectangular pulse signal as an output signal.

  Furthermore, it comprises switching means for switching the first rectangular pulse signal and the second rectangular pulse signal to be the output signal, and the control means is configured to change the first frequency when the frequency is changed to the high frequency region side. Switching control of the switching means for outputting a rectangular pulse signal as an output signal is performed, and when the frequency is changed to the low frequency region side, the switching means is controlled to output the second rectangular pulse signal as an output signal. Switching control of the switching means to be performed is performed.

  As described above, according to the signal generator of the present invention, the second rectangular pulse signal obtained by dividing the first rectangular pulse signal having the set value frequency generated based on the analog signal by the set division ratio is output. When the frequency is changed to the high frequency region side, a control is performed to output the first rectangular pulse signal as an output signal, and when the frequency is changed to the low frequency region side, The set value is controlled to be changed to a value of the frequency division ratio with respect to the signal generation means of the analog signal, and a first rectangular pulse signal having a frequency of the frequency division ratio is output from the pulse signal generation means, Since the second rectangular pulse signal having the frequency is set and controlled with respect to the frequency dividing means, and the second rectangular pulse signal having the frequency is output as an output signal, the analog signal signal generating means includes: Conventional technology Signal generating means by, for example, a general purpose of the DDS can be used as it is, even when the frequency of the rectangular pulse signal is changed to the low frequency range side, it is possible to reduce the jitter of the rectangular pulse signal output.

  Further, by providing time measuring means for measuring the time when the frequency of the second rectangular pulse signal changes from the determined setting of the phase increment value, setting of the phase increment value by the program register based on the measured time Programmable frequency dividing means, because it is synchronized with the setting of the frequency dividing ratio of the programmable frequency dividing means and controls the phase synchronization of the second rectangular pulse signal before and after the change of the frequency dividing ratio when the frequency is changed. Even when the division ratio set to 1 is changed with the change of the frequency of the rectangular pulse signal, the phase continuity of the rectangular pulse signal is maintained and a highly accurate frequency variable rectangular pulse signal is generated. Can do.

  Next, first and second embodiments of the signal generating apparatus according to the present invention will be described with reference to FIGS.

  First, in the present invention, in the case of a variable-frequency signal generator using a comparator to generate a rectangular pulse signal from a sine wave signal, the frequency of the output rectangular wave signal is changed to the high frequency region side. If the frequency of the rectangular wave signal is higher than the frequency of the rectangular pulse signal, paying attention to the phenomenon that the jitter increases as the frequency of the rectangular pulse signal is changed to the low frequency region side. When it is on the region side, the generated rectangular pulse signal is output as an output signal as it is, and when the frequency of the rectangular pulse signal is changed to the low frequency region side, the rectangular pulse signal is divided. A pulse signal that is input to the frequency dividing means and divided by a frequency dividing ratio so as to obtain a desired frequency is output as a rectangular pulse signal.

  Here, in order to output the output signal of the frequency dividing means as a rectangular pulse signal having a desired frequency, the set value for the frequency is divided with respect to the frequency of the analog signal generated by the signal generating means for outputting the analog signal. The control is changed to the value of the frequency division ratio multiplied by the frequency division means, and the rectangular pulse signal having the frequency multiplied by the frequency division ratio is outputted from the pulse signal generation means. A pulse signal having a desired frequency is generated by inputting a rectangular pulse signal having a frequency multiplied by the frequency division ratio to the frequency dividing means, and dividing the frequency by the frequency division ratio, and outputting the pulse signal as an output signal. To do.

  When the frequency of the rectangular pulse signal is changed to the low frequency region side, the pulse signal output from the frequency dividing means that divides the rectangular pulse signal is output as the rectangular pulse signal of the signal generator. Even if there is a certain amount of jitter due to the frequency dividing means in the output rectangular pulse signal, the signal generator according to the prior art has no relation to the occurrence of jitter due to signal fluctuations. Compared with this, the occurrence of jitter can be greatly suppressed.

  In the signal generator according to the present invention, it is necessary to switch the frequency dividing ratio of the frequency dividing means in order to output a rectangular pulse signal having a desired frequency. By switching the frequency division ratio, the frequency of the rectangular pulse signal can be changed. However, the phase of the rectangular pulse signal is not continuous before and after the frequency change depending on the timing of frequency division ratio switching of the frequency dividing means. Sometimes.

  Therefore, by measuring the time when the frequency of the rectangular pulse signal changes from the setting of the frequency setting value for the analog signal, the setting of the frequency setting value for the analog signal and the frequency dividing ratio of the frequency dividing means based on the measured time. Thus, the phase synchronization control of the rectangular pulse signal before and after the change of the frequency division ratio at the time of changing the frequency of the rectangular pulse signal is performed. Thereby, even if the frequency of the rectangular pulse signal is changed, the phase continuity of the rectangular pulse signal is maintained, and a highly accurate variable frequency rectangular pulse signal can be generated.

  As described above, in the signal generator according to the prior art, the frequency range satisfying the specification for jitter is, for example, about 100 MHz to 50 MHz, and the required specification for jitter is not satisfied at a frequency of 50 MHz or less. From the above, in the signal generator according to the present invention, the frequency range of 100 MHz to 50 MHz is the high frequency region side that outputs the generated rectangular pulse signal as an output signal as it is, and the frequency range is 50 MHz or less, for example, up to 1 mHz. The low-frequency region side uses the rectangular pulse signal generated by the frequency dividing means as the output signal. As a guideline for switching between the generated rectangular pulse signal as an output signal or the rectangular pulse signal generated by the frequency dividing means as an output signal, it varies depending on the circuit configuration. A case where the frequency of the rectangular pulse signal to be performed is 50 MHz can be employed.

(First embodiment)
As described above, in order to realize the signal generating apparatus according to the present invention, a conventionally known analog signal oscillator or the like can be used as a signal generating means for outputting an analog signal. In the first embodiment, the general-purpose DDS shown in FIG. 7 is used as the analog signal generating means. A first embodiment of the signal generator of the present invention is shown in FIG.

  FIG. 1 shows a circuit configuration of a signal generator according to a first embodiment capable of generating a low jitter frequency variable rectangular pulse signal (clock signal). The first embodiment is a case where the DDS 1 is used as an analog signal generating means, and basically the same clock signal generator as that shown in FIG. 7 is used as the clock signal generator. . A commercially available general-purpose product can be used for DDS1. In the circuit configuration shown in FIG. 1, the same reference numerals are given to the same parts as those in the circuit configuration shown in FIG.

In the signal generator for a frequency variable clock signal according to the first embodiment shown in FIG. 1, a control means 4 (portion surrounded by a broken line) is added to the signal generator shown in FIG. This control means 4 includes a 2 ⁿ programmable frequency divider 41. The programmable divider and control circuit can be generated by an inexpensive general purpose field programmable gate array (FPGA).

In the first embodiment, while maintaining low jitter, in order to realize that generating a clock of a rectangular pulse which can change the frequency in phase-continuous, the frequency f _d is a region of high output signal Sa of DDS1, the comparator 3 Taking advantage of the characteristic that the jitter of the output signal Sd is small and good, the comparator output signal Sd of the output signal Sa of the DDS1 is output as it is when the clock signal in the high frequency region is generated. In the case of a frequency lower than that frequency region, the frequency-divided output by the programmable frequency divider 41 is the rectangular pulse signal So. The frequency-divided output from the programmable frequency divider 41 has a certain jitter due to the frequency divider, but the jitter is relatively small, and generally does not cause a problem with the output clock signal. Therefore, it is possible to obtain a low jitter clock output from a high frequency to a low frequency.

  Here, in addition to the programmable frequency divider 41, the control means 4 includes a modulation waveform memory 42, a frequency-FTW conversion circuit 43, a frequency-frequency division ratio conversion circuit 44, an FTW-weight value (W) conversion circuit 45, and The control circuit 46 is configured.

The modulation waveform memory 42 stores the frequency f _d of the output signal Sa of the DDS 1 for each modulation rate. If this is read according to the modulation rate, a fixed pattern frequency sweep can be performed. Alternatively, FM modulation can be performed by arranging an A / D converter in place of the modulation waveform memory and sequentially taking in external modulation signals at the modulation rate.

DDS1 outputs the signal Sa having the frequency _{f d} in accordance with the phase variation (FTW). The change of the frequency _{f d} to synchronize with an external circuit of DDS1, program register 15 is connected to the DDS1, the external synchronizing signal, FTW from the program register 15 is transferred to the phase increment value register 11.

Frequency - phase variation (FTW) converting circuit 43 determines the FTW corresponding to the frequency _{f o} of the output signal So.. If the operation clock frequency of DDS1 is f _c and the bit width of FTW is N, FTW is
^{FTW = 2 (N + n)} × (f o / f c)
It is expressed.

Frequency - division ratio converting circuit 44 determines the dividing ratio DR of the programmable frequency divider corresponding to the frequency f _o of the output signal So..
log ₂ (f _L / f _o ) <DR ≦ log ₂ (f _H / f _o ).
However, DR is an integer of 0 or more. Here, f _H represents a frequency equal to or lower than the maximum output frequency of DDS1, and is assumed to have a relationship of f _L = f _H / 2.

The programmable frequency divider 41 divides the frequency f _d of the output signal Sa of the DDS ₁ by the frequency division ratio DR obtained from the frequency-frequency division ratio conversion circuit 44. When the frequency division ratio to DR, the frequency _{f o} of the output signal So,
f _o = f _d / 2 ^DR
It becomes. However, the frequency division ratio DR is an integer greater than or equal to 0, and the range of the frequency f _d of the output signal Sa is f _L <f _d ≦ f _H. This is because a clock signal having a frequency multiplied by the frequency division ratio is output, this clock signal is input to a frequency divider, and a pulse signal having a desired frequency is generated by dividing by the frequency division ratio. This means that this pulse signal can be output as an output signal.

  The programmable frequency divider 41 is composed of, for example, a preset binary counter. The counter preset value at the time of phase change is calculated so that the output signal So is continuous before and after the frequency division ratio DR is changed.

Assuming that the current division ratio is DR ₁ and the current counter value is C _DR1 , the next counter value in the current division ratio is C _DR1 +1. Therefore, the phase P _{DR1 at} this time is
P _DR1 = 2π (C _DR1 +1) / 2 ^DR1
It becomes. However, DR1> 0, and the divided output becomes a clock with a duty of 50% if the (DR ₁ −1) bit of the counter is taken out.

If the next division ratio is DR ₂ and the preset value of the next counter is C _DR2 , then the phase P _{DR2 at} this time is
P _DR2 = 2πC _DR2 / 2 ^DR2
It becomes.

Assuming that the phase is continuous before and after the frequency division ratio change, the phase relationship is P _DR1 = P _DR2 . Therefore, the preset value _CDR2 is
C _DR2 = (C _DR1 +1) × 2 ^(DR2-DR1)
If so, phase continuity can be realized.

When the current frequency division ratio is DR ₁ = 0, that is, when the output frequency f _o is equal to or higher than f _L and no frequency division is performed, the phase P _{DR2 at the} next frequency division ratio DR ₂ is always P _DR2 = Begins with π. Therefore, the preset value _CDR2 is
C _DR2 = 2 ^DR2 / 2 = 2 ^(DR2-1)
And it is sufficient. In this case, since the frequency division ratio is DR ₁ = 0, the frequency f _d of the clock signal Sd is on the high frequency region side, and the pulse signal Sd output from the comparator 3 is frequency-divided by the programmable frequency divider 41. Instead, the output signal So is output as it is.

As can be seen from the above preset value C _DR2, the count value of the next dividing ratio DR _2, since it is multiplied by the power of 2 to the count value with the current division ratio DR _1, shift to the processing It only needs a circuit. When DR ₂ -DR ₁ <0, the shift is right, and when DR ₂ -DR ₁ > 0, the shift is left.

Phase change amount (FTW) - weight value (W) converting circuit 45, after setting the FTW in DDS1, indeed, time to frequency _{f d} is changed in the output signal Sa, that is, the weight value W is the frequency _Find the number of clocks of fd.

The control circuit 46 operates in synchronization with the frequency f _d of the output signal Sa of the DDS 1, generates a signal reflecting the FTW change in the phase increment value register 11 at a timing based on the weight value W, and stores it in the program register 15. give. Further, a signal for changing the frequency division ratio of the programmable frequency divider 41 is generated.

In the frequency variable clock generator according to the first embodiment configured as described above, the modulation waveform data corresponding to the frequency f _d stored in the modulation waveform memory 42 is stored in the phase increment value register 11 and the frequency f _d is stored. Is output to the programmable frequency divider 41. Therefore, the frequency division ratio conversion circuit 44 sets the frequency division ratio corresponding to the frequency in the programmable frequency divider 41 in accordance with the frequency of the modulation waveform data read from the modulation waveform memory 42.

Frequency - division ratio converting circuit 44, when it is determined that the frequency f _o of the clock signal So to be output is in a high-frequency region side sets the division ratio 0 to the programmable divider 41. At this time, the clock signal Sd of a frequency f _o is without frequency division, is output as an output signal So., the frequency relationship becomes f o ₌ f _d.

The frequency - dividing ratio converting circuit 44, the frequency f _o of the clock signal to be output when it is determined that the low frequency range side, sets the division ratio DR to the programmable divider 41. At this time, the frequency f _d of the analog signal Sa generated by the DDS 1 is controlled to change the setting value for the frequency to a value of the frequency division ratio (2 ^DR ), and the clock having the frequency f _d of the frequency division ratio multiple to output a signal Sd, by dividing in the divider ratio in the programmable frequency divider 41 to the clock signal Sd, the clock signal having a desired frequency f _o is generated, and outputs the clock signal as an output signal . Its frequency relationship _{is ^{f o = f d / 2 DR}} .

  As described above, according to the signal generator having the circuit configuration of the first embodiment, the frequency variable signal generator using the method of generating the rectangular pulse signal (clock signal) from the sine wave signal using the comparator, For example, even when a general-purpose DDS is used, if the frequency of the desired clock signal is changed to the high frequency region side, the output signal from the DDS is output as it is, and the frequency of the desired clock signal is, for example, When the frequency is changed to the low frequency region side of 50 MHz or less, an output signal having an increased frequency corresponding to the desired frequency is generated, and the output signal is divided by the frequency divider to the desired frequency. Since the clock signal is output, it is not related to the occurrence of jitter due to analog signal fluctuations. Even if certain jitter by the frequency divider itself has not occurred, the jitter generation amount is small, as compared with the prior art signal generating apparatus according to, could be greatly suppressed the occurrence of jitter.

  Further, in the signal generator having the circuit configuration of the first embodiment, it is necessary to switch the frequency division ratio of the frequency divider in order to output a clock signal having a desired frequency. By switching the frequency division ratio, the frequency of the output clock signal can be changed. However, depending on the timing of frequency division switching of the frequency divider, the phase of the clock signal may be continuous before and after the frequency change. It may stop working.

  Therefore, the time at which the frequency of the clock signal changes is measured from the setting of the frequency setting value for the analog signal, and the setting of the frequency setting value for the analog signal and the frequency division ratio of the divider are based on the measured time. Synchronize the settings and control the phase synchronization of the clock signal before and after changing the division ratio when changing the frequency of the clock signal, so it will be output even if the frequency of the clock signal is changed to the desired frequency. The phase continuity of the clock signal is maintained, and a highly accurate variable frequency clock signal can be generated.

  Therefore, in the signal generator having the circuit configuration according to the first embodiment, when the clock signal frequency is changed to a desired frequency, the frequency division ratio of the frequency divider is maintained so that the phase continuity of the clock signal is maintained. Although the switching timing control has been described above, details of the timing control will be described below with reference to FIGS.

  FIG. 2 is a timing diagram for explaining the phase discontinuity that occurs when the frequency of the clock signal is changed when a binary counter with a preset is used for the programmable frequency divider 41 shown in FIG. As an example of this binary counter, a 3-bit counter is used.

  In FIG. 2, (a) shows the waveform of the clock signal (rectangular pulse signal) Sd input to the binary counter (programmable frequency divider 41), and each of (b) to (d) represents each of the binary counters. FIG. 7 shows a waveform related to bits, (e) shows the waveform of the output signal So, which is the output of the binary counter, and (f) shows the count state of the binary counter.

Here, it is assumed that when the count of the binary counter is started at time t ₀ and the count value is 2, the frequency division ratio is changed from 1 to 3. The arrows in FIG. 2 shows that there is a change instruction to the time t _1. However, since the binary counter outputs the value after counting the third bit at time t ₃ delayed by one clock, the output signal of the binary counter has the waveform (e) shown by the solid line. It becomes like this.

As shown in the circled part on the waveform of (e), at time t ₁ , it is indicated by a broken line. If a clock signal rising at the timing of time t ₁ is obtained, the phase of the clock signal is separated. It can be said that it is continuous before and after the change of the circumference ratio. However, in reality, the output signal of the binary counter rises by one clock after the division ratio is changed, so that the phase continuity of the rectangular pulse signal before and after the change of the division ratio cannot be maintained.

  Therefore, FIG. 3 shows a timing chart for realizing phase continuity before and after the change of the frequency division ratio for changing the frequency of the clock signal in the signal generator of the first embodiment. (A) to (f) in FIG. 3 indicate the same as (a) to (f) in FIG. 2, but (e) in FIG. 3 is indicated by a broken line in (e) in FIG. This is the same as the waveform of the output signal based on the waveform.

Also in the timing chart of FIG. 3, as in the case of FIG. 2, when the count of the binary counter starts at time t ₀ and the count value is 2, the frequency division ratio is 1 (DR ₁ ) to 3 (DR Suppose that it was changed to ₂ ). Here, as described above, for the preset value _CDR2 of the binary counter,
C _DR2 = (C _DR1 +1) × 2 ^(DR2-DR1)
If it is set so that, the phase continuity can be realized.

Therefore, in this equation, if C _DR1 = 2, DR ₁ = 1, DR ₂ = 3,
C _DR2 = (2 + 1) × 2 ^(3-1) = 12
Thus, if the binary counter is loaded with 12 as the preset value _CDR2 , the phase continuity can be maintained.

In the example shown in FIG. 3, since the binary counter is a 3-bit counter, the high-order bits are ignored, and 4 & 7 = 4 (& represents a logical product), and 4 is loaded into the binary counter. 3, at the timing of time t _1, a preset value C _DR2 is set to 4, and how the division ratio is changed from 1 to 3 are shown. The waveform of the output signal in (e) of FIG. 3 shows that the waveform of the output signal rises (portion indicated by a circle) at time t ₁ and the phase continuity is maintained.

  As described above, in the signal generator according to the first embodiment shown in FIG. 1, by devising the timing for changing the counter value of the binary counter with preset used in the programmable frequency divider, The phase continuity before and after the change can be maintained. On the other hand, in the signal generator of the first embodiment described above, a rectangular pulse signal having a desired frequency is generated by changing the frequency division ratio of the programmable frequency divider 41. The frequency of the analog signal to be obtained must be increased according to the size of the frequency division ratio.

However, after setting the phase increment value corresponding to the division ratio has been changed, by the changes in frequency f _d of the output signal Sa of DDS1, for internal pipeline delay DDS101, takes time. Therefore, in the signal generator according to the first embodiment, in order to maintain the continuity before and after the change of the frequency division ratio, the time measurement for measuring the time when the frequency of the rectangular pulse signal changes from the determined setting of the phase increment value. A counter as means is provided in the FTW-W conversion circuit 45.

  Based on the time measured by the time measuring means, the control circuit 46 synchronizes the setting of the phase increment value by the program register and the setting of the frequency dividing ratio of the programmable frequency dividing means. When synchronization is achieved, phase synchronization of the rectangular pulse signal before and after the change of the frequency division ratio when the frequency of the output rectangular pulse signal is changed is realized, and the change is made in accordance with the change of the frequency of the rectangular pulse signal. However, the phase continuity of the rectangular pulse signal is maintained, and a highly accurate frequency variable rectangular pulse signal can be generated.

  FIG. 4 is a timing chart for explaining the time relationship when the frequency of the clock signal (rectangular pulse signal) is changed in the signal generator of the first embodiment. The control circuit 46 sets the phase increment value by the program register. And the setting of the frequency division ratio of the programmable frequency divider are synchronized.

  4A shows the waveform of the output signal Sd of the comparator 3, FIG. 4B shows the timing of the synchronization signal for the DDS1 output from the control circuit 46, and FIG. 4C shows the FTW-W conversion. The counter value of the counter in the circuit 45 is shown. (D) shows the timing of the synchronization signal for setting the frequency division ratio for the programmable frequency divider 41 output from the control circuit 46. (E) has shown the setting state of the frequency division ratio with respect to the programmable frequency divider 41. FIG. And (f) has shown the waveform of the output signal So of the programmable frequency divider 41. FIG.

In FIG. 4, the frequency division ratio DR of the programmable frequency divider 41, by being changed from DR ₁ to DR _2, the frequency _{f d} of the output signal Sd of the comparator 3 which is connected to the output of DDS1 _{is, f d1} It is illustrated that the frequency f _o of the output signal So of the rectangular pulse signal is changed from f _o1 to f _o2 by changing from f to f _d2 .

Here, the time relationship shown in FIG. 4 will be described. Now, set the new FTW in DDS1 inside the program register 15, in order to reflect the DDS1 internal logic, as shown in FIG. 4 (c), the synchronizing signal from the control circuit 46 to the DDS1 is sent to the time _{t 01} . In response to this new FTW is output from the frequency -FTW conversion circuit 43, simultaneously with the time _{t 01,} the counter of the FTW-W converting circuit 45, the count value corresponding to the time _{t D} pipeline delay DDS1 That is, the count of the weight value W is started. The relationship between the weight value W, the frequency f _d , and the time t _D is W = t _D × f _d .

The control circuit 46 at the time of the count value W and the resulting time t ₀₂ corresponding to time t _D, as in FIG. 4 (d), the send a synchronization signal to the programmable frequency divider 41, the time t Simultaneously with ₀₂ , the frequency division ratio of the programmable frequency divider 41 is changed from DR ₁ to DR ₂ . The synchronizing signal at the same time, the division ratio of the programmable frequency divider 41 is changed from the DR ₁ to DR _2, the frequency f _o of the output signal So from the programmable divider 41, no transient state, smooth , F _o1 to f _o2 is changed.

In the example shown in FIG. 4, the frequency f _d2 of the output signal Sd of the comparator 3 and the frequency f _o2 of the output signal So of the programmable frequency divider 41 are the same after changing the frequency division ratio. This indicates the case of DR ₂ = 0. After the frequency division ratio is changed, the programmable frequency divider 41 does not perform the frequency dividing operation, and the output signal Sd is output as it is as the output signal So.

(Specific example of the first embodiment)
So far, as shown in FIG. 1, the outline of the circuit configuration in the first embodiment of the signal generator according to the present invention has been described, but FIG. 5 relates to the signal generator of the first embodiment. A specific circuit configuration is shown. The basic circuit configuration of the signal generating device shown in FIG. 5 is the same as that of the signal generating device shown in FIG. 1, but in FIG. Show.

  The components used in the specific example of the signal generator shown in FIG. 5 are for explaining that the signal generator according to the present invention uses a general-purpose DDS and is configured simply and inexpensively. Although used, each component constituting the signal generation circuit of the present invention is not limited to the component shown in FIG. 5, and may be composed of other components having similar functions. This is obvious to those skilled in the art.

  In FIG. 5, a DDS 101 corresponds to the DDS 1 shown in FIG. 1 and has a circuit configuration similar to the circuit configuration in the DDS 1. In this specific example, for example, a general-purpose DDS manufactured by Analog Devices is used. AD9852 can be used. The low-pass filter (LPF) 102 corresponds to the LPF 2 in FIG. 1, for example, a low-pass filter composed of an inductance (L) and a capacitor (C), and the comparator 103 corresponds to the comparator 3 in FIG.

  Further, in the specific example of the signal generator of FIG. 5, as the control means 4 shown in FIG. 1, the programmable frequency divider 401, the modulation waveform memory 402, the frequency-FTW conversion circuit 403, and the frequency-frequency division ratio conversion circuit 404. , An FTW-W conversion circuit 405, a control circuit 406, a data selector 407, an initial set value memory 408, and a clock selector 503.

  A crystal oscillator 501 is connected to the DDS 101, and a crystal oscillator 502 is connected to the control circuit 406, and a reference clock is supplied to each. The two crystal oscillators 501 and 502 can be shared by one. Each circuit included in the control means 4 is a digital circuit formed of an FPGA, for example, an EC 3 that is an FPGA manufactured by Lattice.

The DDS 101 has a built-in program register for holding user settings (corresponding to the program register 15 shown in FIG. 1), and an address bus terminal A, a data bus terminal as an interface for giving a set value to the program register. D, a write permission terminal WE is provided. A synchronization signal for transferring the set value of the program register to the internal logic of the DDS 101 is input to the I / OUD terminal of the DDS 101. Therefore, the DDS 101 and the user circuit can be synchronized by the synchronization signal input to the I / OUD terminal. Output terminal Ta of DDS101 outputs the output signal Sa of the frequency _{f d} in accordance with the user settings.

  Here, the initial set value memory 408 holds data for initializing the DDS 101. If the DDS 101 originally has a circuit configuration that starts operation at the set frequency, the initial set value memory 408 There is no need to provide a set value memory.

Modulation waveform memory 402 holds the frequency data for setting the frequency _{f d} of the output signal Sa of DDS101, read for each modulation rate. In the circuit configuration example of the control means 4 of the signal generator shown in FIG. 5, the data length is exemplified by 48 bits. In FIG. 5, the numbers displayed on each signal line represent the number of bits in the case of this 48-bit configuration.

  The frequency-FTW conversion circuit 403 calculates a value FTW set in the phase increment value register 11 built in the DDS 101 from the given frequency data Freq and the frequency division ratio DR. The data length of the calculation result here is 48 bits.

  The frequency-frequency division ratio conversion circuit 404 calculates the frequency division ratio DR set in the frequency-FTW conversion circuit 403 and the programmable frequency divider 401 from the given frequency data Freq. The data length of the frequency division ratio DR is 6 bits.

  The FTW-weight value (W) conversion circuit calculates a weight value W for generating an I / OUD synchronization signal and a DRUD synchronization signal in order to synchronize the DDS 101 and the programmable frequency divider 401. The data length of the wait value W is 4 bits.

Programmable divider 401, a pulse signal input from the dividing terminal division ratio DR given in TDR clock terminal Tck dividing into ^{1/2 DR,} the output signal So of a frequency _{f o} from the output terminal To Is output. Frequency f _o of the output signal So output from the output terminal To, the phase before and after changing the division ratio is processed so as to be continuous. When the frequency division ratio DR is 0, the programmable frequency divider 401 does not perform frequency division processing, so that the output signal Sd of the comparator 103 input to the clock terminal Tck is output as it is.

  The clock selector 503 selects a clock to be supplied to the inside of the control means 4 by FPGA. The control means 4 operates in synchronization with the output signal Sd from the DDS 101 as a variable clock during normal operation, but has a circuit configuration in which the initial state of the DDS 101 is set to the oscillation stop mode when the system is reset. In this case, a crystal oscillator 502 is provided because it is necessary to supply a clock from other than the DDS 101 until the initialization of the DDS 101 is completed by the control means 4. During normal operation, the clock selector 503 supplies the output signal Sa of the comparator 103 to the clock terminal Tck of the programmable frequency divider 401 and the clock terminal Tck of the control circuit 406.

  The data selector 407 decodes an address signal transmitted from the address bus terminal A of the control circuit 406 and selects data to be output to the data bus terminal D of the DDS 101 according to the generated selection signal.

  The control circuit 406 outputs an address signal to the initial setting value memory 408, the modulation waveform memory 402, the data selector 407, and the DDS 101. In addition, a clock selection signal is output to the clock selector 503. Further, in order to synchronize the DDS 101 and the programmable frequency divider 401, based on the weight value W calculated by the FTW-W conversion circuit 405, a synchronization signal is transmitted from the I / OUD terminal and the DRUD terminal to the DDS 101 and the programmable frequency divider 401. Output to each of.

Here, with the change of the frequency division ratio DR, programmable frequency in order to smoothly change the frequency _{f o} of the output signal So of the divider 401, the frequency _{f d} of the output signal Sa of DDS101 and the programmable frequency divider 401 The change in the division ratio must be simultaneous. Frequency _{f d} is changed in synchronization with the synchronizing signal from I / OUD terminal, from activate the synchronization signal I / OUD terminal, to actually vary the frequency _{f d} of the output signal Sa of DDA101 Requires a time t _D due to a pipeline delay inside the DDS 101.

Therefore, the division ratio of the programmable frequency divider 401 is determined by outputting the synchronization signal from the DRUD terminal to the programmable frequency divider 401 after waiting for time t _D after the output of the synchronization signal from the I / OUD terminal. It is necessary to change the ratio. The waiting time t _D is calculated by counting the frequency f _d of the output signal Sa at the counter. However, the frequency f _d are the variable clock, it must be changed in accordance with the count value W for the counter in the frequency f _d. Here, the relationship between the count amount W, the frequency f _d , and the time t _D is W = t _D × f _d .

The time relationship when changing the frequency of the clock signal in the signal generator according to the specific example of the first embodiment is the same as the timing chart shown in FIG. Set new FTW to DDS101 inside the program register, in order to reflect the DDS internal logic and to activate the I / OUD synchronization signal, delayed by the waiting time _{t D,} changes the frequency _{f a} of the output signal Sa of DDS101 To do. At the same time the control circuit 406 activates the I / OUD synchronization signal output, the counter of the FTW-W converting circuit 405, where starts counting the frequency _{f d} of the output signal Sd, becomes equal to the weight value W, the control The DRUD sync signal from circuit 406 is activated. As this DRUD sync signal is activated, varying the dividing ratio of the programmable divider 401 from the DR ₁ to DR _2, the frequency _{f o} of the output signal So from the programmable frequency divider 401, a transient state The frequency is changed smoothly from f _o1 to f _o2 .

  As described above, the signal generator shown in FIG. 5 operates in the same manner as the signal generator of the first embodiment shown in FIG. 1, and can use a general-purpose DDS. Even when the frequency of the generated rectangular pulse signal is 50 MHz or less, it is possible to realize a signal generator that suppresses the generation of jitter in the output signal and generates a highly accurate variable frequency rectangular pulse signal.

(Second Embodiment)
In the signal generator of the first embodiment described above, when the frequency of the desired clock signal (rectangular pulse signal) is on the high frequency region side, the frequency divider of the programmable frequency divider provided in the signal generator is used. The ratio is set to DR = 0, and the output signal Sd of the comparator that generates the clock signal from the analog signal is output as it is without being divided by the programmable frequency divider. That is, in the signal generator of the first embodiment, the output signal of the programmable frequency divider is output regardless of whether the frequency of the desired rectangular pulse signal is changed to either the high frequency region side or the low frequency region side. It was to be done.

  Therefore, in the second embodiment, only when the frequency of the desired rectangular pulse signal is on the low frequency region side, the frequency division ratio of the programmable frequency divider provided in the signal generator is set, and the output signal Sd from the comparator is set. Is divided by a programmable frequency divider to output an output signal So of a rectangular pulse signal. When the frequency of the desired rectangular pulse signal is on the high frequency region side, the programmable frequency division provided in the signal generator The output signal Sd from the comparator is directly output as the output signal So of the rectangular pulse signal without passing through the device.

  FIG. 6 shows a signal generator according to the second embodiment. The second embodiment is a modification based on the circuit configuration of the signal generator of the first embodiment. In FIG. A part of the circuit configuration related to the above is shown around the output of the programmable frequency divider.

  As shown in FIG. 6, in the control means 4 of the signal generator of the first embodiment shown in FIG. 1, an output selector 61 and a frequency division ratio discriminating circuit 62 are added. The output selector 61 selects the output signal Sd from the comparator 3 and the divided output signal from the programmable frequency divider 41 and outputs the output signal So. The output selector 61 is controlled by a frequency division ratio determination circuit 62.

  Here, the frequency division ratio discriminating circuit 62 monitors the value of the frequency division ratio output from the frequency-frequency division ratio conversion circuit 44, and when this frequency division ratio is DR = 0, the output selector 61. In contrast, control for selecting the output signal Sd from the comparator 3 is performed.

  The circuit configuration as described above can be easily realized by an FPGA, and the signal generator of the second embodiment shown in FIG. 6 operates in the same manner as the signal generator of the first embodiment shown in FIG. Therefore, a general-purpose DDS can be used, and it is possible to realize a signal generating device that suppresses the occurrence of jitter in the output and generates a highly accurate frequency variable rectangular pulse signal.

It is a block diagram explaining the outline of the circuit structure in 1st Embodiment of the signal generator by this invention. It is a timing diagram explaining the discontinuity of the phase which occurs when the frequency of the rectangular pulse signal is changed. It is a timing diagram explaining the continuity of a phase when the frequency of a rectangular pulse signal is changed in the signal generator of the first embodiment. It is a timing diagram explaining the time relationship in the case of changing the frequency of a rectangular pulse signal in the signal generator of 1st Embodiment. It is a figure explaining the specific circuit structure of the signal generator by 1st Embodiment. It is a block diagram explaining the outline of the circuit structure in 2nd Embodiment of the signal generator by this invention. It is a figure explaining the generator of the rectangular pulse signal which uses a direct digital synthesizer (DDS).

Explanation of symbols

1 Direct digital synthesizer (DDS)
11 Phase increment value register 12 Phase accumulator 13 Waveform memory 14 Digital-analog (A / D) converter 15 Program register 2 Low pass filter (LPF)
3 Comparator 4 Control means 41, 401 Programmable frequency divider 42, 402 Modulation waveform memory 43, 403 Frequency-phase change amount (FTW) conversion circuit 44, 404 Frequency-frequency division ratio conversion circuit 45, 405 Phase change amount (FTW) Weight value (W) conversion circuit 46, 406 Control circuit 407 Data selector 408 Initial setting value memory 501, 502 Crystal oscillator 503 Clock selector 61 Output selector 62 Dividing ratio discriminating circuit

Claims (6)

Signal generating means for outputting an analog signal having a frequency changed according to a set value;
Pulse signal generating means for generating a first rectangular pulse signal having the frequency based on the analog signal;
Frequency dividing means for outputting a second rectangular pulse signal obtained by dividing the first rectangular pulse signal by a set dividing ratio;
When the frequency is changed to the high frequency region side, control is performed using the first rectangular pulse signal as an output signal. When the frequency is changed to the low frequency region side, the setting is made to the signal generating means. The value is controlled to be changed to the value of the frequency division ratio, and the first rectangular pulse signal having the frequency of the frequency division ratio is output from the pulse signal generating means, and the frequency dividing means is set to the frequency division ratio. Control means for performing control to output the second rectangular pulse signal having the frequency as an output signal;
A signal generator comprising: The signal generating means is a direct digital synthesizer having a program register for outputting the analog signal having a frequency according to a set phase increment value and setting the frequency,
The frequency dividing means is a programmable frequency divider composed of a binary counter with a preset,
The control means includes
Frequency-phase increment conversion means for determining a phase increment value corresponding to the frequency and setting the phase increment value in the program register;
Frequency-dividing ratio converting means for determining a dividing ratio of the programmable divider corresponding to the frequency;
The signal generator according to claim 1, further comprising:   The control means includes time measuring means for measuring a time when the frequency of the second rectangular pulse signal changes from the determined setting of the phase increment value, and based on the measured time, the phase increment by the program register The setting of the value and the setting of the division ratio of the programmable frequency dividing means are synchronized, and the phase synchronization of the second rectangular pulse signal before and after the change of the division ratio accompanying the change of the frequency is controlled. The signal generator according to claim 2, wherein   The control unit includes a modulation waveform storage unit that stores the frequency for each modulation rate, and causes the frequency-phase increment conversion unit and the frequency-dividing ratio conversion unit to supply the frequency. The signal generator according to claim 2 or 3.   When the frequency is changed to the high frequency region side, the control means sets the frequency dividing means so as not to perform the frequency division, and the first rectangular pulse signal is set to the second rectangular shape having the frequency. The signal generator according to claim 1, wherein control is performed using a pulse signal as an output signal. A switching means for switching the first rectangular pulse signal and the second rectangular pulse signal to the output signal;
The control means performs switching control of the switching means for outputting the first rectangular pulse signal as an output signal when the frequency is changed to the high frequency area side, and the frequency is changed to the low frequency area side. 5. The signal generation according to claim 1, wherein the switching unit is controlled to control the switching unit to output the second rectangular pulse signal as an output signal. 6. apparatus.

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