KR102123901B1 - All digital phase locked loop, semiconductor apparatus, and portable information device - Google Patents

Abstract

The present invention provides a semiconductor device comprising a fully digital phase locked loop circuit capable of achieving fast fastening.
The ADPLL circuit according to the first invention of the present application receives a reference clock from the outside, generates an output clock having an oscillation frequency that oscillates at a frequency higher than the frequency of the reference clock, and fully digital phase that fixes the phase of the output clock In a fixed loop circuit, during a first reference clock period, a phase of a first divided clock generated from the reference clock is compared with a phase of a delayed reference clock delayed by a predetermined time from the reference clock, and a second continuous to the first reference clock Coarse frequency fixing means for increasing or decreasing the frequency of the output clock during a reference clock period; And fine frequency fixing means for starting receiving the reference clock and performing fine frequency fixing on the reference clock to output an output clock when the coarse frequency fixing means ends the coarse frequency fixing operation. When the frequency fixing means ends the fine frequency fixing operation, the phase difference between the reference clock and the first divided clock is maintained.

Description

ALL DIGITAL PHASE LOCKED LOOP, SEMICONDUCTOR APPARATUS, AND PORTABLE INFORMATION DEVICE}

The present invention relates to a semiconductor device used in a portable information device and the like, and more particularly, to a fully digital phase locked loop circuit applied in a semiconductor device.

In general, the clock required to synchronize input/output data of DRAM is input from the outside with a frequency corresponding to half the data rate in the case of DDR (Double Data Rate). In this way, an external input clock signal given a frequency is received by a delay locked loop inside the DRAM to control the delay time, thereby creating a phase necessary for data synchronization. Since DLL generates only phase at a given frequency, it is widely used in DRAM because it has the advantage of being able to fast phase lock within a predetermined clock period using an open loop control method and designing only with digital circuits.

The fast locking operation means that a fast phase can be generated within a predetermined clock when changing from a turn-off state to a turn-on state. This is because it is usefully used in the down) mode and can be very advantageously used to reduce power consumption in the standby state.

However, as the data rate of DRAM is very fast in the gigabit bps (Gb/s) region, it is becoming increasingly difficult to provide an external input signal with a high frequency required for the operation of the DRAM internal DLL. For example, in order to use a DLL in a high-speed DRAM targeting data transfer of 10 Gb/s, a high frequency clock signal of 5 GHz must be input to the DLL, which provides an external clock signal with a high frequency of 5 GHz. It is technically very difficult.

Due to this problem, the need for a phase locked loop (PLL) has emerged that can accept a low input frequency instead of a high input frequency and generate a high frequency required for data synchronization through frequency multiplication internally. However, in implementing the fast phase lock operation required in DRAM, the ADDLL (all digital DLL) is relatively easy to fix the clock quickly if only the phase is detected, whereas the ADPLL (all digital PLL) has an oscillator that is not in the DLL. Since it is necessary to detect the phase and frequency of, it is not easy to fix the clock quickly.

For this reason, little research has been done on ADPLLs that can quickly lock the clock.

US Publication Patent US2011/0099450 Korean Registered Patent No. 10-0955873

The present invention provides a semiconductor device including a fully digital phase locked loop circuit capable of achieving fast phase lock by sequentially performing coarse frequency lock operation and fine frequency lock operation.

The present invention compares the phase of the divided clock and the phase of the delayed reference clock during the first reference clock period, and can update the frequency of the output clock having an oscillation frequency oscillating at a frequency higher than the frequency of the reference clock during the second reference clock period. A fully digital phase locked loop circuit can be provided.

The present invention provides a semiconductor device including a fully digital phase locked loop circuit capable of achieving fast phase lock by fixing the phase difference immediately before the reference clock and the divided clock after the fine frequency lock operation.

The ADPLL circuit according to the first invention of the present application receives a reference clock from the outside, generates an output clock having an oscillation frequency that oscillates at a frequency higher than the frequency of the reference clock, and fully digital phase that fixes the phase of the output clock In a fixed loop circuit, during a first reference clock period, a phase of a first divided clock generated from the reference clock is compared with a phase of a delayed reference clock delayed by a predetermined time from the reference clock, and a second continuous to the first reference clock Coarse frequency fixing means for increasing or decreasing the frequency of the output clock during a reference clock period; And fine frequency fixing means for starting receiving the reference clock and performing fine frequency fixing on the reference clock to output an output clock when the coarse frequency fixing means ends the coarse frequency fixing operation. When the frequency fixing means ends the fine frequency fixing operation, the phase difference between the reference clock and the first divided clock may be maintained.

Preferably, the coarse frequency fixing means comprises: a digital control oscillator driven by a coarse digital control oscillator driving signal output by the binary searcher to generate the output clock; A divider reset signal generator for generating a divider reset signal using the reference clock; A first divider that is reset to the reset signal for the divider and divides the output clock first to output the first divide clock; A first time for converting and outputting an error caused by the reset signal for the divider into a numerical digital error code value from a time when the reset signal for the divider is switched to a first level to a time when the output clock is switched to a second level. /Digital converter; A compensator for delaying the reference clock by a digitized digital error code value output from the first time/digital converter to output the delayed reference clock; A comparator for comparing a phase of the first divided clock and a phase of the delayed reference clock and outputting a digital comparison value for up/down determining a frequency increase or decrease of the reference clock; And a binary searcher generating the coarse digital control oscillator driving signal and the coarse frequency fixed termination signal using the digital comparison value output from the comparator and the reference clock.

Preferably, the fine frequency fixing means includes: a first divider for first dividing the output clock and outputting the first divided clock; A second time/digital converter that receives the reference clock and the first divided clock in response to the coarse frequency fixed end signal, and outputs a phase difference between the reference clock and the first divided clock as a phase difference digital code value; A fine fixing unit for converting and outputting the phase difference digital code value into a frequency difference digital code value; A digital loop filter that integrates the frequency difference digital code value and outputs an integrated frequency difference digital signal; A second divider configured to divide the output clock for a second time to output a second division clock; A modulator for modulating the integrated frequency difference digital signal to generate and output a fine digital control oscillator driving signal; And a digital control oscillator generating an output clock having an oscillation frequency corresponding to the fine digital control oscillator driving signal.

Preferably, the fine digital control oscillator driving signal is a direct pass signal that directly passes a part of the integrated frequency difference digital signal, and the remaining part of the integrated frequency difference digital signal is modulated with the second divided clock. Contains modulated signals.

Preferably, the fine fixing unit converts the current phase difference digital code value to the frequency difference digital code value by subtracting the immediately preceding phase difference digital code value.

Preferably, the fine fixing unit, a subtracter for subtracting the previous phase difference digital code value from the current phase difference digital code value; A frequency change rate adjustment unit that reduces the frequency change rate coefficient of the digital loop filter to a predetermined rate whenever the slope sign of the output change amount of the subtractor changes, and generates the fine frequency fixed termination signal when the frequency change rate coefficient reaches a predetermined value. ; A first flip-flop that receives the output of the subtractor and outputs the digital code value immediately before the phase difference; And a logic unit for outputting a set signal for setting the first flip-flop using the fine frequency fixed end signal and the reference clock when the fine frequency fixed operation ends.

Preferably, when the fine frequency fixed termination signal is output, the first flip-flop maintains the immediately preceding phase difference digital code value as the last phase difference digital code value, and the subtracter is the current phase difference digital code value and the last phase difference digital code. The error of the value is output.

Preferably, in response to the fine frequency fixation termination signal, the fine frequency fixation means performs a phase fixation by fixing the immediately preceding phase difference between the reference clock and the first divided clock as the last phase difference.

Preferably, the digital loop filter, a fixed proportional amplifier for outputting a fixed proportional value to the output of the fine fixing unit; A variable proportional amplifier that outputs a value proportional to the variable to the output of the fine fixing unit; A first adder for adding the current output value and the immediately preceding output value of the variable proportional amplifier; A second flip-flop that receives the current output value of the variable proportional amplifier and provides it as an output value immediately before each reference clock; And a second adder for adding and outputting the output of the fixed proportional amplifier and the output of the variable proportional amplifier.

In addition, the ADPLL circuit according to the second invention of the present application receives a reference clock from the outside, generates an output clock having an oscillation frequency that oscillates at a frequency higher than the frequency of the reference clock, and completely fixes the phase of the output clock. In the digital phase locked loop circuit, during a first reference clock period, a phase of a divided clock generated from the reference clock is compared with a phase of a delayed reference clock delayed by a predetermined time from the reference clock, and a second continuous to the first reference clock During the reference clock period, it includes coarse frequency fixing means for increasing and decreasing the frequency of the output clock, and when the coarse frequency fixing means ends the coarse frequency fixing operation, a phase difference between the reference clock and the divided clock can be maintained. .

Preferably, the coarse frequency fixing means comprises: a divider for dividing the output clock to a predetermined frequency and outputting a divided clock; And a coarse fixed unit that outputs the coarse frequency fixed end signal and coarse digital control oscillator drive signal using the divided clock and the reference clock.

Preferably, the coarse frequency fixing means comprises: a digital control oscillator driven by a coarse digital control oscillator driving signal output by the binary searcher to generate the output clock; A divider reset signal generator for generating a divider reset signal using the reference clock; A first divider that is reset to the reset signal for the divider and divides the output clock first to output the first divide clock; A first time for converting and outputting an error caused by the reset signal for the divider into a numerical digital error code value from a time when the reset signal for the divider is switched to a first level to a time when the output clock is switched to a second level. /Digital converter; A compensator for delaying the reference clock by a digitized digital error code value output from the first time/digital converter to output the delayed reference clock; A comparator for comparing a phase of the first divided clock and a phase of the delayed reference clock and outputting a digital comparison value for up/down determining a frequency increase or decrease of the reference clock; And a binary searcher generating the coarse digital control oscillator driving signal and the coarse frequency fixed termination signal using the digital comparison value output from the comparator and the reference clock.

Further, the semiconductor device according to the present invention has a fully digital phase locked loop circuit illustrated in the detailed description of the present invention.

In addition, the portable information device according to the present invention includes a semiconductor device having a fully digital phase locked loop circuit exemplified in the detailed description of the present invention.

According to the fully digital phase locked loop circuit of the present invention, the phase of the divided clock and the phase of the delayed reference clock are compared during the first reference clock period, and the oscillation frequency oscillates at a frequency higher than that of the reference clock during the second reference clock period. Fast phase lock can be achieved by updating the frequency of the output clock.

In addition, according to the present invention, it is possible to achieve faster phase lock by sequentially performing the coarse frequency lock operation and the fine frequency lock operation, and fixing the phase difference immediately before the reference clock and the divided clock after the fine frequency lock operation.

1 is an overall block diagram of a fully digital phase locked loop according to a first embodiment of the present invention,
2 is an overall block diagram of a fully digital phase locked loop circuit according to a second embodiment of the present invention,
3 is a coarse frequency fixed timing diagram according to an embodiment of the present invention,
4 is a detailed timing diagram of coarse frequency fixation according to an embodiment of the present invention,
5 is a block diagram of a frequency detector among the fine frequency fixing means according to an embodiment of the present invention,
6 is a circuit diagram for phase fixing according to an embodiment of the present invention,
7 is an explanatory diagram of a transition process from a fine frequency fixing operation to a phase fixing operation according to an embodiment of the present invention, and
8 is a block diagram of an electronic system including a semiconductor device according to embodiments of the present invention.

Hereinafter, preferred embodiment(s) of the present invention will be described in detail with reference to the accompanying drawings. First, when adding reference numerals to the components of each drawing, it should be noted that the same components are denoted by the same reference numerals as much as possible even though they are displayed on different drawings. In addition, in the following description, many specific matters are shown, which are provided to help a more comprehensive understanding of the present invention, and those skilled in the art that the present invention may be practiced without these specific matters. It will be obvious to you.

1 is an overall block diagram of a fully digital phase locked loop circuit according to a first embodiment of the present invention, and receives a reference clock CK_ref input from the outside to perform a coarse frequency lock operation to perform a coarse frequency lock end signal (S_eocl) ) In response to the coarse frequency fixing means 100 and the coarse frequency fixing end signal S_eocl, starting to receive the reference clock CK_ref, and performing a fine frequency fixing operation on the reference clock CK_ref to output the clock And a fine frequency fixing means 200 for outputting (CK_out).

The fully digital phase locked loop according to an embodiment of the present invention sequentially performs a coarse frequency lock operation and a fine frequency lock operation on a reference clock input from the outside, and then performs a phase lock operation.

The configuration and operation of the coarse frequency locking means (100) are as follows.

The coarse frequency fixing means 100 includes a digitally controlled oscillator 110, a divider 130, and a coarse locking unit 150.

When the reference clock CK_ref is input, the digital control oscillator 110 generates an output clock CK_out that oscillates at a predetermined frequency. The frequency divider 130 divides the output clock CK_out at a predetermined frequency and outputs a frequency divider clock CK_div. The coarse fixed unit 150 uses the divided clock CK_div and the reference clock CK_ref input from the outside to indicate that the coarse frequency fixed operation is finished, and the coarse frequency fixed end signal S_eocl and the coarse digital control oscillator drive signal S_dcoc. ). Then, the digital control oscillator 110 generates the output clock CK_out of the oscillation frequency corresponding to the coarse digital control oscillator driving signal S_dcoc. The reference clock CK_ref applied to the coarse fixed unit 150 is blocked according to the coarse frequency fixed end signal S_eocl.

The configuration and operation of the fine frequency locking means (200, Fine Frequency Lockiong Means) are as follows.

The fine frequency fixing means 200 includes a frequency detector 210, a digital loop filter 230, a digitally controlled oscillator 110, and a divider 130. .

When the coarse frequency fixed end signal S_eocl is output, the frequency detector 210 receives the reference clock CK_ref and the division clock CK_div, and the frequency difference between the reference clock CK_ref and the division clock CK_div Convert to digital code value and output. The digital loop filter 230 integrates the frequency difference digital code value output from the frequency detector 210 to output a fine digital control oscillator driving signal S_dcof. The digital control oscillator 110 generates an output clock CK_out having an oscillation frequency corresponding to the fine digital control oscillator driving signal S_dcof. Here, the divider 130 divides the output clock CK_out and outputs a division clock CK_div. For example, the divider 130 divides the output clock CK_out by 16, and outputs the divided clock CK_div divided by 16.

When the fine frequency fixed operation ends, the frequency detector 210 outputs the fine frequency fixed end signal S_eofl, and in response to the fine frequency fixed end signal S_eofl, the digital loop filter 230 displays the current reference clock CK_ref. The phase-locking operation is performed by fixing the phase difference between and the division clock (CK_div).

2 is an overall block diagram of a fully digital phase locked loop circuit according to a second embodiment of the present invention, and receives a reference clock CK_ref input from the outside to perform a coarse frequency lock operation to perform a coarse frequency lock end signal (S_eocl) ) In response to the coarse frequency fixing means 100 and the coarse frequency fixing end signal S_eocl, starting to receive the reference clock CK_ref, and performing a fine frequency fixing operation on the reference clock CK_ref to output the clock And a fine frequency fixing means 200 for outputting (CK_out).

The coarse frequency fixing means 100 includes a digitally controlled oscillator (110), a reset signal generator (120, RST_div Generator) for a divider, a first divider (130, DIV1), a first time/digital converter (140, Time-to-Digital Converter 1), a compensator (153, Compensator), a comparator (155, Comparator), and a binary searcher (157, Binary Searcher).

The digital control oscillator 110 is driven by the coarse digital control oscillator driving signal S_dcoc to generate an output clock CK_out that oscillates at a predetermined frequency.

The divider reset signal generator 120 generates a divider reset signal RST_div for resetting the first divider 130 using a reference clock CK_ref input from the outside.

The first divider 130 is reset to the reset signal RST_div for the divider, and outputs the first divided frequency CK_div1 by first dividing the output clock CK_out. For example, the first divider 130 divides the output clock CK_out by 16, and outputs the divided clock CK_div1 divided by 16.

)를 수치화된 디지털 에러 코드값으로 변환하여 출력한다.In the first time/digital converter 140, the reset signal for the divider (RST_div) from the time when the reset signal (RST_div) for the divider is switched to the "L" level to the time when the output clock (CK_out) is switched to the "H" level. Error by resetting (Fig. 4)

) Is converted to a numeric digital error code value and output.

The compensator 153 delays the reference clock CK_ref input from the outside by the digitized digital error code value output from the first time/digital converter 140 to output the delayed reference clock CK_refd.

The comparator 155 compares the phases of the first divided clock CK_div1 and the delayed reference clock CK_refd and outputs an up or down digital comparison value for determining the frequency increase or decrease of the reference clock Ck_ref. do.

The binary searcher 157 generates and outputs the coarse digital control oscillator driving signal S_dcoc and the coarse frequency fixed termination signal S_eocl using the digital comparison value and the reference clock CK_ref output from the comparator 160.

Then, when the binary searcher 157 outputs the coarse frequency fixed end signal S_eocl and turns on the first and second switches SW1 and SW2, the fine frequency fixing means 200 starts to operate, and the third switch By turning off (SW3), the rough frequency fixing means 100 ends the operation. Meanwhile, according to an embodiment of the present invention, the binary searcher 157 may be implemented as a Successive Approximation Resister (SAR).

The fine frequency fixing means 200 includes a second time/digital converter 211, a fine locking unit (213), a digital loop filter (230), and a modulator ( 240, Modulator), second divider 250, DIV2, Digitally Controlled Oscillator 110, and first divider 130, DIV1.

The second time/digital converter 211 receives the reference clock CK_ref and the first division clock CK_div1 in response to the coarse frequency fixed termination signal S_eocl, and the reference clock CK_ref and the first division clock CK_div1 ), and outputs the phase difference digital code value.

The fine frequency fixing unit 213 converts and outputs the phase difference digital code value output from the second time/digital converter 211 to a frequency difference digital code value indicating a frequency difference.

The digital loop filter 230 integrates the frequency difference digital code value output from the fine fixing unit 213, and outputs the integrated frequency difference digital signal.

The second divider 250 divides the output clock CK_out a second time to output a second divided second division clock CK_div2. For example, the second divider 250 divides the output clock CK_out by four, and outputs the divided clock CK_div2 divided by four.

The modulator 240 modulates the integrated frequency difference digital signal output from the digital loop filter 230 to generate and output a fine digital control oscillator driving signal S_dcof. The fine digital control oscillator driving signal (S_dcof) is a direct pass signal that directly passes a part of the integrated frequency difference digital signal, and a modulated signal that modulates the remaining part of the integrated frequency difference digital signal with a second frequency division clock (CK_div2). Includes. For example, the modulator 240 directly passes the upper 7 bits of the 22-bit integrated frequency difference digital signal output from the digital loop filter 230, and modulates the remaining lower 15 bits with the second frequency divider clock (CK_div2) 1 A bit modulation signal is generated, and the upper 7 bits and 1 bit modulation signals that are directly passed are combined and output as a fine digital control oscillator driving signal (S_dcof). Meanwhile, according to an embodiment of the present invention, the modulator 240 may use a first order delta-sigma modulator. The fully digital phase locked loop circuit according to the second embodiment of the present invention may further include a second divider 250 and a modulator 240 to perform a fine frequency fixed operation more quickly.

The digital control oscillator 110 generates an output clock CK_out having an oscillation frequency corresponding to the fine digital control oscillator driving signal S_dcof.

The first divider 130 first divides the output clock CK_out and outputs the first divider clock CK_div1. For example, the first divider 130 and DIV1 divides the output clock CK_out by 16, and outputs the 16 divider clock CK_div1.

When the fine frequency fixed operation ends, the frequency detector 210 outputs the fine frequency fixed end signal S_eofl, and in response to the fine frequency fixed end signal S_eofl, the digital loop filter 230 displays the current reference clock CK_ref. The phase-locking operation is performed by fixing the phase difference between and the division clock (CK_div).

3 is a coarse frequency fixed timing diagram according to an embodiment of the present invention.

The coarse frequency fixing operation is performed by using two consecutive reference clocks as one cycle, and compares the phases of the first divided clock CK_div1 and the delayed reference clock CK_refd to the first reference clock CK_ref ( compare), and updates by increasing or decreasing the frequency of the output clock CK_out to the second reference clock CK_ref.

Since the first divider 130 is used to generate the output clock CK_out by multiplying the frequency of the reference clock CK_ref, the first divider clock CK_div1 should be fixed to the reference clock CK_ref. In order to compare the periods of the reference clock CK_ref and the output clock CK_out, it is necessary to reset the first divider 130 every period of the coarse frequency fixing operation.

4 is a detailed timing diagram of coarse frequency fixation according to an embodiment of the present invention, and is an enlarged view of a dotted line of FIG. 3.

The divider reset signal generator 120 outputs a divider reset signal RST_div that transitions to the "L" level in synchronization with a rising edge of the reference clock CK_ref.

The first divider 130 starts counting the output clock CK_out in response to the reset signal RST_div for the divider transitioning to the “L” level.

After the reset of the first divider 130, a period Δ until the first output clock CK_out is input to the first divider 130 appears as an error added to the phase of the first divider clock CK_div1. Therefore, the size of this period Δ is measured using the first time/digital converter 140, the reference clock CK_ref is delayed by the same period Δ using the compensator 153, and the comparator 155 ) To compare the phases of the first divided clock CK_div1 and the delayed reference clock CK_refd.

As shown in FIG. 4, when the rising edge of the first frequency division clock CK_div1 is ahead of the rising edge of the delayed reference clock CK_refd, the comparator 155 outputs an “L” signal to generate a binary searcher ( 157) is updated to decrease the frequency of the output clock CK_out. Conversely, when the rising edge of the first divided clock CK_div1 is behind the rising edge of the delayed reference clock CK_refd, the comparator 155 outputs an “H” signal to generate a binary searcher 157. Updates to increase the frequency of the output clock CK_out. According to this method, it is possible to fix the frequency very precisely even with a rough frequency fixing operation.

Meanwhile, the binary searcher 157 converts the digital comparison value output from the comparator 160 during a plurality of coarse frequency fixed cycles into a continuous multi-bit code to output a multi-bit coarse digital control oscillator driving signal S_dcoc. For example, when 10 coarse frequency fixed cycles have elapsed, a coarse frequency fixed end signal S_eocl is output.

Specifically, the binary searcher 157 converts the digital comparison value output from the comparator 160 into a code of a continuous multiple bits for a plurality of cycles of the reference clock CK_ref, and a multi-bit coarse digital control oscillator driving signal S_dcoc ). For example, the binary searcher 157 converts the digital comparison value output from the comparator 155 per coarse frequency fixed cycle into a continuous 10-bit code for 10 cycles by 1 bit. To output a coarse digital control oscillator driving signal (S_dcoc) of 10 bits.

5 is a block diagram of a frequency detector among the fine frequency fixing means according to an embodiment of the present invention, FIG. 6 is a circuit diagram for phase fixing according to an embodiment of the present invention, and FIG. 7 is according to an embodiment of the present invention It is an explanatory diagram of the transition process from the fine frequency fixed operation to the phase fixed operation.

The frequency detector 210 may include a second time/digital converter 211 and a fine frequency fixing unit 213.

The second time/digital converter 211 outputs the phase difference between the input reference clock CK_ref and the first division clock CK_div1, and the fine fixing unit 213 has a reference clock CK_ref and a first division clock ( The frequency difference Y(n) is output using the current phase difference X(n) of CK_div1) and the previous phase difference X(n-1).

Specifically, the fine fixing unit 213 is a subtractor 611, the first D flip-flop 613, the logic unit 615, the frequency change rate adjustment unit 617, and the fine frequency fixed termination signal (S_eofl) is turned on Includes 4 switches 619.

During the fine frequency fixed operation, the logic unit 615 outputs a “1” signal in synchronization with the reference clock CK_ref before the fine frequency fixed end signal S_eofl is output, so the first D flip-flop 613 is in the phase difference immediately before. (X(n-1)) is output.

The subtractor 611 subtracts the previous phase difference X(n-1) from the current phase difference X(n), and the current phase difference X(n) and the previous phase difference X(n-1) ).

Y[n] = X[n]-X[n-1]

)를 소정 비율로 감소시키고, 주파수 변화율 계수(

)가 소정치에 이르게 되면, 미세 주파수 고정 종료 신호(S_eofl)를 발생시킨다. 예컨대, 주파수 변화율 조정부(617)는 주파수 검출기(210)의 출력 변화량의 기울기 부호가 (+)에서 (-)으로 변하거나, (-)에서 (+)으로 변할 때마다, 디지털 루프 필터(230)의 주파수 변화율 계수(

)를, 예컨대, 절반으로 감소시킨다. 이러한 방법으로 주파수 변화율(

)을 감소시킴으로써 주파수 변화를 미세하게 조정한다. 예컨대, 주파수 검출기(210)의 출력 변화량의 기울기 부호가 변경될 때마다, 주파수 변화율을 2^-4에서 2^-5으로, 다시 2^{- 5} 에서 2^-6으로 변경하여 줄이고, 2^-7 에 이르면 미세 주파수 고정 종료 신호(S_eofl)를 발생함으로써 미세 주파수 고정 동작을 종료한다.The frequency change rate adjustment unit 617 changes the frequency change rate coefficient 633 of the digital loop filter 230 whenever the slope sign of the output change amount of the subtractor 611 changes.

) To a certain ratio, and the frequency change factor (

) Reaches a predetermined value, a fine frequency fixed termination signal S_eofl is generated. For example, the frequency change rate adjusting unit 617 whenever the slope sign of the output change amount of the frequency detector 210 changes from (+) to (-) or (-) to (+), the digital loop filter 230 Frequency change rate coefficient of

), for example, by half. In this way, the rate of frequency change (

) To fine tune the frequency change. For example, each time the slope sign of the output change amount of the frequency detector 210 changes, the frequency rate of change in the ^2-4 to ^2-5, two ^back-to reduce changes from ⁵ to ^2-6, micro reaches ^2-7 The fine frequency fixing operation is terminated by generating the frequency fixed termination signal S_eofl.

The logic unit 615 outputs a set signal for setting the first D flip-flop 613 when the fine frequency fixed operation is finished using the fine frequency fixed end signal S_eofl and the reference clock CK_ref. That is, when the fine frequency fixed termination signal S_eofl is output, since the logic unit 815 outputs "0", the first D flip-flop 613 maintains the last phase difference (X(n-1)) , Subtractor 611 outputs an error between the current phase difference and the last phase difference.

Here, according to the prior art, while having to control the divided clock to match the phase of the reference clock, due to the first D flip-flop 613, the subtractor 611 can subtract the last phase difference from the current phase difference. Therefore, in the present invention, the phase lock can be quickly performed by maintaining the difference between the phase of the divided clock and the phase of the reference clock as the last phase difference in the fine frequency fixing operation.

)한 값을 출력하는 고정 비례 증폭기(631), 미세 고정 유닛(213)의 출력에 변동 비례(

)한 값을 출력하는 변동 비례 증폭기(633), 변동 비례 증폭기(633)의 현재 출력 값과 직전 출력 값을 가산하는 제1 가산기(635), 변동 비례 증폭기(633)의 현재 출력 값을 입력받아 기준 클럭(CK_ref)마다 직전 출력 값으로 제공하는 제2 D 플립플롭(637), 및 고정 비례 증폭기(631)의 출력과 변동 비례 증폭기(633)의 출력을 가산하여 출력하는 제2 가산기(639)를 포함한다.The digital loop filter 230 is fixed proportional to the output of the fine fixing unit 213 (

) The proportional proportional to the output of the fixed proportional amplifier (631), the fine fixed unit 213 outputting a value (

) Receives the current output value of the variable proportional amplifier 633 for outputting a value, the first adder 635 for adding the current output value of the variable proportional amplifier 633 and the previous output value, and the variable proportional amplifier 633 The second D flip-flop 637 provided as the immediately preceding output value for each reference clock CK_ref, and the second adder 639 for adding and outputting the output of the fixed proportional amplifier 631 and the variable proportional amplifier 633 It includes.

)한 값을 디지털 제어 오실레이터(110)의 입력에 반영함으로써 위상 고정 동작을 수행한다.
When the fourth switch 619 is turned on in response to the fine frequency fixed termination signal S_eofl, the second adder 639 is proportional to the output of the fine frequency fixed unit 213 (

) Is applied to the input of the digital control oscillator 110 to perform a phase lock operation.

According to the present invention, a semiconductor device characterized by having an ADPLL circuit disclosed in any one of the embodiments, and an electronic system including the semiconductor device are also included.

8 is a block diagram of an electronic system including a semiconductor device according to embodiments of the present invention. Referring to FIG. 8, the electronic system 800 according to an embodiment of the present invention may include a controller 810, an input/output device 820, a memory device 830, an interface 840, and a bus 850. . The controller 810, the input/output device 820, the storage device 830, and/or the interface 840 may be coupled to each other through the bus 850. The bus 850 corresponds to a passage through which data is moved. The controller 810 according to the present invention may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing similar functions. The input/output device 820 according to the present invention may include a keypad keyboard and a display device. The memory device 830 according to the present invention may store data and/or instructions. The memory device 830 according to the present invention may include at least one of the semiconductor devices disclosed in the above-described embodiments. In addition, the memory device according to the present invention may further include other types of semiconductor memory elements (ex, Flash Memory, DRAM or SRAM, etc.). The interface according to the present invention may perform a function of transmitting data to a communication network or receiving data from the communication network. The interface according to the present invention may be wired or wireless. For example, the interface according to the present invention may include an antenna or a wired/wireless transceiver. Although not illustrated, the electronic system according to the present invention may further include a high-speed DRAM or SRAM as an operation memory for improving the operation of the controller.

Embodiments of the present invention are applicable to uplink and downlink. Embodiments of the present invention can be applied to all modulation strategies such as OFDMA, CDMA, SC-OFDMA. Embodiments of the present invention are applicable to mobile devices and desktop devices. Embodiments of the present invention can be implemented in a digital signal processor (DSP) or an application specific integrated circuit (ASIC).

The electronic system according to the present invention is a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player (digital music player), memory card (memory card) or information can be implemented in any electronic product that can transmit and/or receive information in a wireless environment.

As described above, although specific embodiment(s) have been described in the detailed description of the present invention, various modifications are possible without departing from the scope of the present invention. The present invention is applicable to all scheduling communication systems that perform power control. Therefore, the scope of the present invention should not be determined by being limited to the described embodiment(s), and should be defined not only by the following claims, but also by the claims and equivalents.

100: coarse frequency fixing means 110: digitally controlled oscillator
120: reset signal generator for divider 130: first divider
140: first time / digital converter 153: compensator
155: comparator 157: binary searcher
200: fine frequency fixing means 211: second time / digital converter
213: fine fixing unit 230: digital loop filter
240: modulator 250: second divider

Claims (15)

In an all-digital phase locked loop circuit for generating an output clock having an oscillation frequency oscillating at a frequency higher than the frequency of a reference clock input from the outside, and fixing the phase of the output clock,
During the first reference clock period, the phase of the first divided clock generated from the first reference clock is compared with the phase of the delayed reference clock delayed by a predetermined time from the first reference clock, and during the second reference clock period subsequent to the first reference clock , Coarse frequency fixing means for updating by increasing or decreasing the frequency of the output clock, and blocking the input of the reference clock input from the outside when the coarse frequency fixing operation is finished; And
When the coarse frequency fixing means ends the coarse frequency fixing operation, the micro-frequency starts to directly receive the reference clock input from the outside and performs fine frequency fixing on the reference clock input from the outside to output the output clock. It includes a fixing means,
When the fine frequency fixing means ends the fine frequency fixing operation, a fully digital phase locked loop circuit that maintains a phase difference between the reference clock input from the outside and the first divided clock.
According to claim 1, The coarse frequency fixing means,
A digital control oscillator that is driven by a coarse digital control oscillator driving signal output by the following binary searcher to generate the output clock;
A divider reset signal generator for generating a divider reset signal using the reference clock;
A first divider that is reset to the reset signal for the divider and divides the output clock first to output the first divide clock;
A first time for converting and outputting an error caused by the reset signal for the divider into a numerical digital error code value from a time when the reset signal for the divider is switched to a first level to a time when the output clock is switched to a second level. /Digital converter;
A compensator for delaying the reference clock by a digitized digital error code value output from the first time/digital converter to output the delayed reference clock;
A comparator for comparing a phase of the first divided clock and a phase of the delayed reference clock and outputting a digital comparison value for up/down determining a frequency increase or decrease of the reference clock; And
A binary searcher that generates the coarse digital control oscillator driving signal and the coarse frequency fixed termination signal by using the digital comparison value output from the comparator and the reference clock.
Fully digital phase locked loop circuit comprising a.
The method of claim 1, wherein the fine frequency fixing means,
A first divider for dividing the output clock first and outputting the first divided clock;
A second time/digital converter that receives the reference clock and the first divided clock in response to the coarse frequency fixed end signal, and outputs a phase difference between the reference clock and the first divided clock as a phase difference digital code value;
A fine fixing unit for converting and outputting the phase difference digital code value into a frequency difference digital code value;
A digital loop filter that integrates the frequency difference digital code value and outputs an integrated frequency difference digital signal;
A second divider configured to divide the output clock for a second time to output a second division clock;
A modulator for modulating the integrated frequency difference digital signal to generate and output a fine digital control oscillator driving signal; And
A digital control oscillator generating an output clock having an oscillation frequency corresponding to the fine digital control oscillator driving signal.
Fully digital phase locked loop circuit comprising a.
According to claim 3, The fine digital control oscillator driving signal,
A fully digital phase locked loop circuit comprising a direct pass signal that directly passes a portion of the integrated frequency difference digital signal and a modulated signal that modulates the remaining part of the integrated frequency difference digital signal with the second divided clock.
According to claim 3,
The modulator is a first order delta-sigma modulator, a fully digital phase locked loop circuit.
The method of claim 5,
The fine-fixing unit is a fully digital phase locked loop circuit that converts the current phase difference digital code value to the frequency difference digital code value by subtracting the immediately preceding phase difference digital code value.
According to claim 6, The fine fixing unit,
A subtracter subtracting the immediately preceding phase difference digital code value from the current phase difference digital code value;
A frequency change rate adjustment unit that reduces the frequency change rate coefficient of the digital loop filter to a predetermined rate whenever the slope sign of the output change amount of the subtractor changes, and generates the fine frequency fixed termination signal when the frequency change rate coefficient reaches a predetermined value. ;
A first flip-flop that receives the output of the subtractor and outputs the digital code value immediately before the phase difference;
When the fine frequency fixing operation ends, a logic unit outputting a set signal for setting the first flip-flop using the fine frequency fixed termination signal and the reference clock
Fully digital phase locked loop circuit comprising a.
The method of claim 7,
When the fine frequency fixed end signal is output, the first flip-flop maintains the previous phase difference digital code value as the last phase difference digital code value, and the subtractor compensates for an error between the current phase difference digital code value and the last phase difference digital code value. Full digital phase locked loop circuit output.
According to claim 1,
In response to the fine frequency fixing end signal, the fine frequency fixing means performs a phase lock by fixing the phase difference immediately before the reference clock and the first divided clock as the last phase difference to perform phase lock.
The method of claim 7, wherein the digital loop filter,
A fixed proportional amplifier outputting a fixed proportional value to the output of the fine fixed unit;
A variable proportional amplifier that outputs a value proportional to the variable to the output of the fine fixing unit;
A first adder for adding the current output value and the immediately preceding output value of the variable proportional amplifier;
A second flip-flop that receives a current output value of the variable proportional amplifier and provides it as an output value immediately before each reference clock; And
A second adder for adding and outputting the output of the fixed proportional amplifier and the output of the variable proportional amplifier.
Fully digital phase locked loop circuit comprising a.
In an all-digital phase locked loop circuit for generating an output clock having an oscillation frequency oscillating at a frequency higher than the frequency of a reference clock input from the outside, and fixing the phase of the output clock,
During the first reference clock period, the phase of the divided clock generated from the first reference clock is compared with the phase of the delayed reference clock delayed by a predetermined time from the first reference clock, and during the second reference clock period subsequent to the first reference clock, the And increasing or decreasing the frequency of the output clock, and stopping the input of the reference clock input from the outside when the coarse frequency fixing operation is terminated.
When the coarse frequency fixing means ends the coarse frequency fixing operation, a fully digital phase locked loop circuit maintaining a phase difference between the reference clock and the divided clock input from the outside.
The method of claim 11, wherein the coarse frequency fixing means,
A divider for dividing the output clock at a predetermined frequency to output a divided clock; And
A coarse fixed unit that outputs the coarse frequency fixed end signal and coarse digital control oscillator drive signal using the divided clock and the reference clock.
Fully digital phase locked loop circuit comprising a.
The method of claim 11, wherein the coarse frequency fixing means,
A digital control oscillator that is driven by a coarse digital control oscillator driving signal output by the following binary searcher to generate the output clock;
A divider reset signal generator for generating a divider reset signal using the reference clock;
A first divider that is reset to the reset signal for the divider, and outputs a first division clock by first dividing the output clock;
A first time for converting and outputting an error caused by the reset signal for the divider into a numerical digital error code value from a time when the reset signal for the divider is switched to a first level to a time when the output clock is switched to a second level. /Digital converter;
A compensator for delaying the reference clock by a digitized digital error code value output from the first time/digital converter to output the delayed reference clock;
A comparator for comparing a phase of the first divided clock and a phase of the delayed reference clock and outputting a digital comparison value for up/down determining a frequency increase or decrease of the reference clock; And
A binary searcher that generates the coarse digital control oscillator driving signal and the coarse frequency fixed termination signal using the digital comparison value output from the comparator and the reference clock.
Fully digital phase locked loop circuit comprising a.
A semiconductor device comprising the fully digital phase locked loop circuit according to any one of claims 1 to 13.
A portable information device comprising the semiconductor device of claim 14.

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