JP5347534B2 - Phase comparator, PLL circuit, and phase comparator control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase comparator, a PLL circuit, and a method of controlling the phase comparator, capable of accurately detecting phase difference between an output signal of a voltage controlled oscillator VCO and a reference signal as a digital signal. <P>SOLUTION: The comparator includes delay circuits in which a plurality of stages are respectively cascade-connected, and the reference signal and an object signal are input, a holding circuit for output of phase difference between the reference signal and the object signal by difference of delay times in respective stages, and a logic circuit for changing time difference and magnitude of each delay element based on its output results. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a phase comparator and a control method thereof.

  IEEE802.11a / g WLAN (Wireless Local Area Network) and other high-speed wireless communication systems use 16QAM (Quadrature Amplitude Modulation: Quadrature Amplitude Modulation) to efficiently transmit large volumes of signals within a limited frequency band. Modulation), 64QAM and other advanced modulation are introduced. In these wireless chips used for wireless communication, since the power consumption of the digital signal processing unit is large, the wireless chip is not built into a terminal such as a mobile phone except for a relatively low-speed IEEE802.11b WLAN.

In recent years, for the purpose of performing such signal processing with low power consumption, the application to the baseband of fine CMOS (Complementary Metal-Oxide Semiconductor) devices has been promoted. The power supply voltage of the band is low. In the future, in order to reduce costs, so-called system on chip (SoC), in which the digital part and the RF part are integrated, is accelerating. In this case, since it is necessary to make an RF part with a fine device, the RF circuit also needs to operate at a low voltage.
However, in an RF (Radio Frequency: radio frequency) circuit based on an analog system related to the present invention, it is difficult to further reduce the voltage in consideration of variations in element characteristics due to miniaturization. One of the RF blocks that are greatly affected by the low voltage is a PLL (Phase Locked Loop) circuit.

FIG. 10 is an example of an analog PLL circuit related to the present invention.
In FIG. 10, 1 is a phase comparator, 2 is a charge pump, 3 is a loop filter, 4 is a voltage controlled oscillator (VCO: Voltage Controlled Oscillator), and 5 is a frequency divider.

The operation of the PLL circuit shown in FIG. 10 will be described below.
The phase comparator 1 generates output signals S1 and S2 based on the result of comparing the reference signal FREF and the signal CKV obtained by dividing the output signal of the voltage controlled oscillator VCO. The signal S1 is a signal indicating the phase advance amount of the reference signal FREF with respect to the signal CKV, and the signal S2 is a signal indicating the phase advance amount of the signal CKV with respect to the reference signal FREF. These signals S1 and S2 are input to the charge pump 2. The output signal S3 of the charge pump 2 is input to the loop filter 3 where high frequency components are removed and then input as the control voltage S4 of the voltage controlled oscillator VCO4.
This PLL circuit is locked when it operates so that the frequencies and phases of the reference signal FREF and the signal CKV coincide with each other, and the frequency (fVCO) obtained from the voltage controlled oscillator VCO4 becomes a frequency division multiple of the reference signal FREF.

  The frequency of the voltage controlled oscillator VCO4 is determined, for example, by changing the control voltage of the MOS varactor in the case of a type that uses the resonance frequency of a resonance circuit composed of an inductor and a MOS varactor capacitor. However, when the modulation sensitivity, which is the amount of change in the frequency with respect to the change in the control DC potential, is increased, there is a problem that the frequency of the voltage controlled oscillator VCO4 varies due to the influence of power supply noise and induction noise. In order to solve the problem of frequency fluctuation, a method of switching a plurality of resonance circuits while setting modulation sensitivity low has been proposed.

  On the other hand, since the control range of the capacitance is limited to the linear region of the varactor, if the power supply voltage decreases, the modulation sensitivity of the voltage controlled oscillator VCO must be increased, resulting in noise outside and inside the chip. There was a problem that the frequency of the local oscillator fluctuated due to such factors.

As a means for avoiding this frequency fluctuation problem, a circuit for digitally controlling the voltage controlled oscillator VCO has been disclosed (for example, see Patent Document 1 and Non-Patent Document 1).
In the technology related to the present invention, the control of the varactor of the voltage controlled oscillator VCO is a method in which the DC potential is not applied, but is repeatedly turned on and off in time and the time ratio is changed. When the time ratio is made to be constant, a large spurious (unnecessary radiation) is generated. Therefore, in Patent Document 1 and Non-Patent Document 1 described above, a signal is obtained by using a sigma delta (ΣΔ modulation) modulator. Randomized.

How the PLL circuit detects and controls the frequency of the digital voltage controlled oscillator VCO will be described with reference to FIG.
FIG. 11 is a block diagram of a digital PLL related to the present invention.
In the figure, the phase of the reference signal FREF, which is an output from the reference crystal oscillator, is obtained by accumulating the frequency control word FCW in the latch 132 at the rising edge of the reference signal FREF in the phase detector 51 (this). The frequency control word FCW corresponds to the frequency ratio of the output signal CKV of the voltage controlled oscillator VCO 135 to the reference signal FREF, that is, the multiplication number). The phase of the output signal CKV of the reference crystal oscillator is obtained by counting the number of clock transitions at the rising edge in the phase detector 52 by the latch 118, and this output is accumulated by the reference signal FREF in the latch 119. It is gained by.

The relationship between the phases calculated by each phase detector will be specifically described with reference to FIGS.
FIG. 12A is a circuit that detects the phase of the output signal CKV of the voltage controlled oscillator VCO, and has the same configuration as the phase detector 52 in FIG. In FIG. 12A, a 4-bit adder and a latch circuit are used.
As shown in FIG. 12B, the output of the voltage controlled oscillator VCO accumulates the numerical value of the adder at every rising edge of the output signal CKV, and the value is increased at every rising edge of the reference signal FREF. Latched. In this example, it is assumed that the initial value of the adder is 0, the count of the output signal CKV is started, and the frequency ratio between the signal CKV and the reference signal FREF is 10.

  On the other hand, since the adder has a 4-bit configuration, a numerical value of 16 or more that causes an overflow is counted as 0. Accordingly, the latch outputs at the timing of the reference signal FREF are 0, 10, 4, 14, 8.

On the other hand, the phase of the reference signal FREF is performed by the circuit of FIG. 12C. This circuit is also the same configuration as the phase detector 51 in FIG. As described above, “10” is input to the frequency control word (FCW) indicating the target multiplication number, and the phase signal is incremented by 10 every time the reference frequency FREF rises.
FIG. 12D is a diagram for explaining this operation, and shows a case where the initial value of the adder is 3. Since the initial value is 3 and is incremented by 10 every time, the output of the circuit for each reference signal FREF is 3, 13, 7, 1, 11. In the example of this figure, the frequency of the voltage controlled oscillator VCO matches the target, but the phase is shifted by three pulses of the voltage controlled oscillator VCO.

  The detected means for detecting the phase difference signal of the voltage controlled oscillator VCO and the reference signal FREF will be described again with reference to FIG. The phase error of these signals is performed in a phase comparator 81 including phase detectors 51 and 52 and an adder / subtractor 122. That is, the phase error is obtained by simply arithmetically subtracting the above-mentioned two digital numerical values in the adder / subtractor 122. The obtained phase error signal is fed back to the oscillator via the interface circuit 107 that performs processing such as gain adjustment to the oscillator after the high-speed component is removed by the digital loop filter 133.

  However, since the resolution below the oscillation period of the voltage controlled oscillator VCO cannot be realized only by the above-described phase detection method by accumulating the number of transitions for each rising edge of the signal CKV, in the example of Patent Document 1, the small phase comparator is used. 82, and a minute phase error is detected using a time digital converter (TDC) 83. In the time-to-digital converter (TDC), as shown in FIGS. 13 and 14, the detected transition position of the signal CKV from “1” to “0” is determined based on the sampling edge of the reference signal FREF110 and the signal CKV. The position of the detected transition of “0” to “1” of the signal CKV indicated by the delay time Δtr between the rising edges 302 is determined by the sampling edge of the reference signal FREF (110) and the falling edge of the signal CKV114. A delay time Δtf between 400 is indicated. The delay times Δtr and Δtf are quantized and indicated by a multiple of the circuit time resolution Δtres.

FIG. 13 is an example of a timing diagram illustrating the principle of small phase comparison in the digital PLL circuit shown in FIG. FIG. 14 is another example of a timing diagram for explaining the principle of small phase comparison in the digital PLL circuit shown in FIG.
Here, the small phase error ΦF is given by −Δtr / 2 (Δtf−Δtr) when Δtf> Δtr, and 1−Δtr / 2 (Δtr−Δtf) when Δtr> Δtf. Given in.

FIG. 15 is a block diagram of a phase comparator in the digital PLL circuit shown in FIG.
This phase comparator is a circuit example of a time digital converter (TDC) 83 for detecting a phase error equal to or less than the period of the signal CKV.
A time digital converter 500 shown in FIG. 15 includes a delay element 502 and a latch / register 504 formed of a plurality of inverters. The signal CKV (114) is sequentially delayed by a plurality of inverters, and the delayed vectors are latched in the latch / register 504 at the rising edge of the reference clock FREF (110) from a reference crystal oscillator (not shown). As long as the total delay of the inverter array sufficiently covers the clock period of the signal CKV (114), it is possible to detect the phase error up to the resolution Δtres of the delay time of the inverter.

FIG. 16 is a timing chart for explaining the operation of the phase comparator in the circuit shown in FIG.
At the positive transition 602 of the signal FREF (110) from the reference crystal oscillator, a plurality of latch / registers 504 are accessed and the signal CKV (114) is referenced to the rising edge of the signal FREF (110) from the reference crystal oscillator. A plurality of instantaneous values 604 indicative of the delay of. This instantaneous value 604 can be regarded as indicating a time difference as a digital value.
This digital value is added / subtracted with the output of the phase detector 51 by the adder / subtractor 123. The minute phase error signal calculated by the adder / subtractor 123 is subjected to high-speed component removal by the digital loop filter 134 and modulated by the ΣΔ modulator 108, and then the frequency of the voltage controlled oscillator VCO 135 is controlled with high accuracy.

FIG. 17 is a block circuit diagram schematically showing the invention disclosed in Patent Document 2 as another digital phase detector related to the present invention.
In FIG. 15, 101_1 to 101_n are first delay elements, 102_1 to 102_n are second delay elements, 103_1 to 103_n are data holding circuits, 104 is a logic circuit, REF is a reference signal, and CKV is a target signal. .

  This digital phase detector generates FB_1 to FB_n sequentially delayed by the delay time of each of the first delay elements 101_1 to 101_n by passing the target signal CKV through the plurality of first delay elements 101_1 to 101_n. Further, the reference signal FREF is also passed through the plurality of second delay elements 102_1 to 102_n, thereby generating signals REF_1 to REF_n that are sequentially delayed by the delay time of each of the second delay elements 102_1 to 102_n. .

The data holding circuit 103_1 uses the signal FB_1 in which the target signal CKV is delayed by the first stage 101_1 of the first delay elements 101_1 to 101_n, and the reference signal FREF is the first stage of the second delay elements 102_1 to 102_n. Latched at the rising edge of the signal REF_1 delayed by 102_1.
In addition, the data holding circuit 103_n has FB_n in which the target signal CKV is delayed by 101_1 to 101_n corresponding to the first delay element n stages, and the reference signal FREF is delayed by 102_1 to 102_n corresponding to the second delay element n stages. Latch on the edge of REF_n. That is, the data holding circuits 103_1 to 103_n in the digital phase detector of this example have FB_1 to FB_n in which the target signal CKV is sequentially delayed by the first delay elements 101_1 to 101_n, and the reference signal FREF is the second delay element 102_1. Is latched at the edges of the target signals REF_1 to REF_n which are sequentially delayed by 102_n, and the phase advance / delay information of FB_1 to FB_n and REF_1 to REF_n is output to the logic circuit 104 as digital signals Q_1 to Q_n, respectively. To do.

  FIG. 18 is a timing chart for explaining an example of the operation of the digital phase detector shown in FIG. Note that FIG. 18 shows processing by the five data holding circuits 103_1 to 103_5 for convenience.

  As shown in FIG. 18, the target signal CKV sequentially passes through the plurality of first delay elements 101_1 to 101_5, thereby sequentially adding delay times for each stage of the first delay elements 101 (101_1 to 101_5). The signals FB_1 to FB_5 are input to the data terminals D of the data holding circuits 103_1 to 103_5, respectively.

  Further, the reference signal FREF sequentially passes through the plurality of second delay elements 102_1 to 102_5, whereby signals REF_1 to REF_5 obtained by sequentially adding the delay times for each stage of the second delay elements 102 (102_1 to 102_5). Are respectively input to the clock terminals of the data holding circuits 103_1 to 103_5.

  The data holding circuits 103_1 to 103_5 latch the corresponding target signals FB_1 to FB_5 at the rising timing of the signals 103_1 to 103_5, and output the outputs Q_1 to Q_5 to the logic circuit 104.

Furthermore, in the digital phase detector of the present embodiment, the delay time of the first delay element 101 (101_1 to 101_n) is configured to be different from the delay time of the second delay element 102 (102_1 to 102_n). Therefore, the resolution of the digital phase detector is defined according to the difference ΔD between the delay time of the first delay element 101 and the delay time of the second delay element 102.
Here, the resolution of the digital phase detector increases as the difference ΔD between the delay time of the first delay element 101 and the delay time of the second delay element 102 decreases, and the delay time of the first delay element 101 The larger the difference ΔD from the delay time of the second delay element 102, the lower the value.

  As described above, the phase detection resolution can be controlled by controlling the delay time of the first delay element 101 and the second delay element 102. However, the phase detection resolution and the first delay element 101 and the second delay element 102 can be controlled. The product of the delay element 102 and the number of stages of the delay element 102 is a phase difference range that can be detected.

Here, examples of techniques related to the phase comparator are described in Patent Documents 3 to 5.
The digital phase-locked loop circuit disclosed in Patent Document 3 has “first and second loops that match the input frequency and the output frequency by performing phase feedback, and the clock source to be synchronized is lost. In a digital phase locked loop circuit that stores a synchronized clock frequency and holds the frequency for a long period of time, a predetermined frequency is compared with the output frequency, and the comparison result is compared with the first and second loops. It has a third loop used for feedback in “and operates as follows.

  According to this digital phase-locked loop circuit, the calculation means in the third loop calculates the difference between the frequency of the signal output from the fixed frequency oscillator and the output frequency, and the calculated difference is stored in the storage means. In the comparison means, the difference between the frequency of the signal output from the fixed frequency oscillator and the current output frequency is compared with the difference stored in the storage means, and the signal having the frequency based on the comparison result is voltage-controlled. The difference between the frequency of the signal output from the oscillator and the signal output from the fixed frequency oscillator and the current output frequency is controlled to be equal to the difference stored in the storage means. Thus, it is said that the long-term stability of the HOLD OVER operation can be improved by newly providing a third loop that operates during the HOLD OVER transition.

  The digital PLL circuit of Patent Document 4 is “a first n-bit register (n is an integer equal to or greater than 2) that operates with a reference clock, an output bus value of this first n-bit register, and an input value that determines an oscillation frequency. And the output bus value of the n-bit adder as an input to the first n-bit register, and the MSBs of two consecutive output bus values of the first n-bit register And comparing absolute values of two consecutive output bus values of the first n-bit register, comparing the MSB of the two consecutive output bus values of the first n-bit register, and the first The MSB delay amount of the output bus value of the first n-bit register is optimally controlled based on the comparison result of the absolute values of two consecutive output bus values of the n-bit register, and the output of the first n-bit register Variable bus value MSB delay signal Using a digital variable frequency oscillator as a wave number oscillator output, the phase comparison output consisting of the average value of two consecutive output bus values output from the first n-bit register at the phase comparison timing is sent to the n-bit adder as the oscillation frequency. It is input as the input value to be determined, and operates as follows.

  According to this digital PLL circuit, high frequency resolution can be obtained with a low frequency reference clock, phase comparison can be performed accurately, and the phase accuracy of the variable frequency oscillator output can be increased to 0.5 reference clock, that is, 0. A digital PLL circuit with 5 reference clocks or less can be realized.

  The phase adjustment circuit disclosed in Patent Document 5 is “a phase adjustment circuit that discretely adjusts the phase of a data signal and a clock signal, a delay line that delays the clock signal to generate a delayed clock signal, a data signal, A phase comparator that compares the phase of the delayed clock signal, a first delay control unit that outputs a first delay control signal based on the comparison result of the phase comparator, and a first delay control unit that outputs a first delay control signal based on the frequency of the clock signal. And a delay line that determines a delay amount of the delayed clock signal relative to the clock signal based on the first and second delay control signals ”. Yes, it works as follows.

  According to this phase adjustment circuit, regarding the phase adjustment circuit in data transmission having a transmission path such as a cable, it is possible to optimally set the relationship between the data rate and the delay line gain even if a digital delay line is used. The advantages of the digital delay line such as area, power saving, ease of process porting, and ease of design are compatible with data reception performance.

JP 2002-76886 A JP 2007-110370 A JP 2000-315945 A JP 2001-244810 A JP 2007-110323 A

Journal of Solid-State Circuit, Vol39, No.12, 2004, pp.2278-2291

  As described above, by controlling the voltage controlled oscillator VCO digitally, a stable and highly accurate oscillation signal can be realized even in the low voltage operation of a fine CMOS device. However, the oscillation of the voltage controlled oscillator VCO It is expected that the demand for time resolution will become stricter as the frequency increases.

Since the time resolution described in Patent Document 1 described above is determined by the delay time of the inverter, a delay time below a certain level in the semiconductor manufacturing technology cannot be realized. For example, at 8 GHz, one period is 125 ps, but with a 90 nm process, the resolution is about 20 ps. In the technique described in Patent Document 2, in order to improve the resolution, the difference ΔD between the delay time of the first delay element 101 and the delay time of the second delay element 102 is simply set small. There is a need. In order to secure a certain amount of phase difference range that can be detected, it is necessary to significantly increase the number of stages of delay elements.
For example, in order to set the resolution to 1 ps, the number of stages of delay elements is 20 times that in the case of the technique described in Patent Document 1.

  Further, with the technique described in Patent Document 2, it is possible to reduce the required number of stages by setting the delay time of each delay element to be different at each stage without making the delay time constant. There is a problem that the phase difference cannot be determined. The techniques described in Patent Documents 3 to 5 have the same problem.

  An object of the present invention is to solve the above-mentioned problems of the prior art, and the purpose thereof is a phase comparator capable of detecting a phase difference between an output signal of a voltage controlled oscillator VCO and a reference signal as a digital signal with high accuracy. And a method of controlling a PLL circuit and a phase comparator.

  The phase comparator of the present invention includes a delay circuit that is connected in a plurality of stages, each of which is connected to a reference signal and a target signal, and a phase difference between the reference signal and the target signal based on a difference in delay time of each stage. A holding circuit for outputting, and a logic circuit for changing a time difference and a magnitude of the delay element based on the output result are provided.

  The PLL circuit of the present invention is characterized by using the phase comparator configured as described above.

  According to the control method of the present invention, a reference signal and a target signal are input to delay elements connected in a plurality of stages, and a phase difference between the reference signal and the target signal is digitally output based on a difference in delay time of each stage. Then, based on the output result, the time difference and the size of the delay element are changed.

  According to the present invention, it is possible to provide a phase comparator, a PLL circuit, and a control method for the phase comparator that can detect the phase difference between the output signal of the voltage controlled oscillator VCO and the reference signal as a digital signal with high accuracy. it can.

It is an example of the block diagram which shows the digital phase comparator for demonstrating the 1st Embodiment of this invention. It is an example of the timing diagram for demonstrating operation | movement of the digital phase detector shown in FIG. It is an example of the block diagram of the phase comparator for demonstrating the 2nd Embodiment of this invention. It is an example of the block diagram of the phase comparator for demonstrating the 3rd Embodiment of this invention. It is an example of the timing diagram of the 3rd Embodiment of this invention. It is an example of the timing diagram of the 3rd Embodiment of this invention. It is an example of the block diagram of the phase comparator for demonstrating the 4th Embodiment of this invention. It is an example of the timing diagram of the 4th Embodiment of this invention. It is an example of the block diagram of the phase comparator for demonstrating the 5th Embodiment of this invention. It is an example of the block diagram of the analog type PLL circuit relevant to this invention. It is a block diagram of a digital type PLL circuit related to the present invention. FIG. 12 is a timing chart for explaining the operation of the phase detection unit in the digital PLL circuit shown in FIG. 11. FIG. 12 is an example of a timing diagram illustrating the principle of small phase comparison in the digital PLL circuit shown in FIG. 11. FIG. 12 is another example of a timing diagram illustrating the principle of small phase comparison in the digital PLL circuit shown in FIG. 11. FIG. 12 is a block diagram of a phase comparator in the digital PLL circuit shown in FIG. 11. FIG. 16 is a timing chart for explaining the operation of the phase comparator in the circuit shown in FIG. 15. FIG. 10 is a block circuit diagram schematically showing the invention disclosed in Patent Document 2 as another digital phase detector related to the present invention. FIG. 18 is a timing chart for explaining an example of the operation of the digital phase detector shown in FIG. 17.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
FIG. 1 is an example of a block diagram showing a digital phase comparator for explaining the first embodiment of the present invention.
In the following embodiments, the same members are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate.
In FIG. 1, 101_1 to 01_n are first delay elements, 102_1 to 102_n are second delay elements, 103_0 to 103_n are data holding circuits, 104 is a logic circuit, FREF is a reference signal obtained from a reference crystal oscillator, CKV Is a signal to be compared.

  The digital phase detector generates FB_1 to FB_n sequentially delayed by the delay time of each of the first delay elements 101_1 to 101_n by passing the target signal CKV through the plurality of first delay elements 101_1 to 101_n. To do. Further, the reference signal FREF is also passed through a plurality of second delay elements 102_1 to 102_n, thereby generating signals REF_1 to REF_n that are sequentially delayed by the delay times of the second delay elements 102_1 to 102_n.

  The data holding circuit 103_1 uses the signal FB_1 in which the target signal CKV is delayed by the first stage 101_1 of the first delay elements 101_1 to 101_n, and the reference signal FREF is the first stage of the second delay elements 102_1 to 102_n. Latched at the rising edge of the signal REF_1 delayed by 102_1.

  The data holding circuit 103_n also delays the signal FB_n in which the target signal CKV is delayed by 101_1 to 101_n corresponding to the first delay element n stages, and the reference signal FREF is delayed by 102_1 to 102_n corresponding to the second delay element n stages. Latch at the edge of the signal REF_n. That is, the data holding circuits 103_1 to 103_n in the digital phase detector of this example provide the logic circuit 104 with the information on the phase advance / lag of the signals FB_1 to FB_n and the signals REF_1 to REF_n, respectively, as digital signals Q_1 to Q_n. Output.

  In the digital phase detector of the present embodiment, the delay time of the first delay element 101 (101_1 to 101_n) is configured to be different from the delay time of the second delay element 102 (102_1 to 102_n), The resolution of the digital phase detector is defined according to the difference ΔD between the delay time of the first delay element 101 and the delay time of the second delay element 102.

  Here, the resolution of the digital phase detector increases as the difference ΔD between the delay time of the first delay element 101 and the delay time of the second delay element 102 decreases, and the delay time of the first delay element 101 The larger the difference ΔD from the delay time of the second delay element 102, the lower the value.

  In addition, each delay element in the present embodiment includes one buffer circuit, a switch connected to each output terminal of the buffer circuit, and a plurality of capacitive elements of the same size connected via each switch. Has been. The delay time is controlled by changing the number of capacitors connected to the output terminal.

The operation of this embodiment will be described with reference to FIG.
FIG. 2 is an example of a timing diagram for explaining the operation of the digital phase detector shown in FIG.
Here, it is assumed that the target signal CKV is advanced by ΔT with respect to the reference signal FREF at the start of phase comparison.
In the present embodiment, first, the phase difference ΔD between the first delay element 101 and the second delay element 102 is set to the maximum. That is, all n capacitive elements C 1 to Cn are connected to the output terminal of the first delay element 101.

  On the other hand, the capacitive elements C 1 to Cn are not connected to the output terminal of the second delay element 102. In this case, the delay amount of the first delay element 101 is td0 + nδ, where td0 is the delay time of the buffer circuit, and δ is the increase in delay time every time one capacitive element is connected. The delay amount of the delay element 102 is td0, and the time difference is nδ. The output of the data holding circuit 103_0 at the stage before passing through the first-stage delay circuit becomes “1”, and the phase difference gradually decreases by nδ every time it passes through the delay elements. When the phase relationship between the target signal CKV delayed by several stages of each delay circuit and the reference signal FREF is reversed, the output of the data holding circuit 103 is inverted. If the inverted data holding circuit 103 is fourth from the first stage, it can be seen that the initial phase difference is between 3nδ and 4nδ.

At the input terminal of the fourth-stage data holding circuit 103_4, the target signal CKV is advanced with respect to the reference signal FREF. Therefore, the output of the data holding circuit 103 is “0”. The target signal CKV is delayed by a phase difference of − (n / 2) δ every time it sequentially passes through the delay element. When the phase relationship between the target signal CKV delayed by several stages of each delay circuit and the reference signal FREF is reversed, the output of the data holding circuit 103 is reversed again.
If the inverted data holding circuit 103 is the sixth from the first stage, it can be seen that the initial phase difference is between 4nδ-2 (n / 2) δ and 4nδ- (n / 2) δ.

  Next, the magnitude relationship between the delay amounts of the first delay element 101 and the second delay element 102 is inverted again, and the difference is set again smaller than before. For example, the buffer output of the first delay element 101 connects all n capacitive elements.

  On the other hand, (3n / 4) capacitor elements are connected to the buffer output of the second delay element 102. At this time, the delay amount of the first delay element 101 is td0 + nδ, the delay amount of the second delay element 102 is td0 + (3n / 4) δ, and the time difference is + (n / 4) δ. At the input terminal of the sixth stage data holding circuit 103_6, the target signal CKV is delayed with respect to the reference signal FREF, and therefore the output of the data holding circuit 103 is “1”. Each time the signal passes through the delay element, the target signal CKV is delayed by a phase difference of + (n / 4) δ.

  When the phase relationship between the target signal delayed by several stages of each delay circuit and the reference signal is reversed, the output of the data holding circuit 103 is reversed again. If the inverted data holding circuit 103 is the seventh from the first stage, the initial phase difference is 4nδ-2 (n / 2) δ + (n / 4) δ and 4nδ-2 (n / 2) δ. I understand that it is in between. By repeating this sequentially, a high-resolution phase comparator can be realized efficiently. In addition, as in the technique related to the present invention, the phase detection resolution is not directly connected to the range of the phase difference that can be detected, so the degree of freedom in design is widened.

[Second Embodiment]
FIG. 3 is an example of a block diagram of a phase comparator for explaining the second embodiment of the present invention.
The target signal CKR is a signal obtained by retiming the reference signal FREF at the rising edge of the comparison target signal CKV using a flip-flop. In this embodiment, unlike the first embodiment, instead of directly comparing the comparison target signal CKV and the reference signal FREF, the retimed reference signal is compared with the original reference signal FREF. Yes. Since the retimed reference signal holds the phase difference information between the comparison target signal CKV and the reference signal, it is not necessary to use a high-speed comparison target signal, and as a result, the power consumption of the phase comparator can be reduced. Is possible.

  The digital phase detector generates signals REF_1 to REF_n that are sequentially delayed by the delay times of the first delay elements 101_1 to 101_n by passing the reference signal FREF through the plurality of first delay elements 101_1 to 101_n. To do. Further, with respect to the re-timed signal CKR, the signal CKR is passed through the plurality of second delay elements 102_1 to 102_n, thereby sequentially delaying the signals CKR_1 to CKR_n by the delay times of the second delay elements 102_1 to 102_n. Is generated.

  In the data holding circuit 103_1, the reference signal FREF is the signal REF_1 delayed by the first stage 101_1 of the first delay elements 101_1 to 101_n, and the retimed signal CKR is the first of the second delay elements 102_1 to 102_n. Latching is performed at the rising edge of the signal CKR_1 delayed at the stage 102_1. In addition, the data holding circuit 103_n includes the signal REF_n obtained by delaying the reference signal FREF by 101_1 to 101_n corresponding to the first delay element n stages, and the retimed signal CKR corresponding to the second delay element n stages 102_1 to 102_n. Latch on the delayed CKR_n edge. That is, the data holding circuits 103_1 to 103_n in the digital phase detector according to the present embodiment send the phase advance / delay information of the REF_1 to REF_n and CKR_1 to CKR_n to the logic circuit 104 as digital signals Q_1 to Q_n, respectively. Output.

  Also in the digital phase detector of this embodiment, the delay time of the first delay element 101 (101_1 to 101_n) is configured to be different from the delay time of the second delay element 102 (102_1 to 102_n). As in the first embodiment, each delay element in the present embodiment includes one buffer circuit, a plurality of switches connected to the output terminal of the buffer circuit, and a plurality of switches connected through the switches. The delay time is controlled by changing the number of capacitors connected to the output terminal.

  In the present embodiment, the phase difference between the comparison target signal and the reference signal in the first embodiment is detected by using a signal obtained by retiming the reference signal with the target signal. Only. Since the operation for detecting the phase difference between the retimed signal CKR and the reference signal FREF is the same as that in the first embodiment, the description thereof is omitted.

[Third Embodiment]
FIG. 4 is an example of a block diagram of a phase comparator for explaining the third embodiment of the present invention.
In this embodiment, the signal CKR is a flip-flop, the reference signal FREF is a retimed signal at the rising edge of the comparison target signal CKV, and the CKRB is a flip-flop, and the reference signal FREF is the falling edge of the comparison target signal CKV. The signal is retimed at the edge.

  The retimed reference signal CKR holds the phase difference information between the original reference signal FREF and the comparison target signal CKV, and the signal CKRB is a phase difference of 1/2 cycle of the comparison target signal CKV in addition to the phase difference. Holding. By comparing the phase difference between the two retimed signals and the reference signal CKR, a phase difference in which the phase difference is normalized by the period of the comparison target signal CKV can be obtained. Also in this embodiment, it is not necessary to use a high-speed comparison target signal, and as a result, the power consumption of the phase comparator can be reduced.

  In FIG. 4, 105_1 to 105_n are third delay elements, and 106_0 to 106_n are second data holding circuits. In this digital phase detector, the reference signal FREF is passed through the plurality of first delay elements 101_1 to 101_n, thereby generating REF_1 to REF_n sequentially delayed by the delay time of each of the first delay elements 101_1 to 101_n. . Further, the re-timed signal CKR is passed through the plurality of second delay elements 102_1 to 102_n, so that the signals CKR_1 to CKR_n sequentially delayed by the delay time of the second delay elements 102_1 to 102_n are transmitted. Generate. Further, the re-timed signal CKRB is passed through a plurality of third delay elements 105_1 to 105_n, thereby sequentially delaying the signals CKRB_1 to CKRB_1 to 105_n by delay times of the third delay elements 105_1 to 105_n. CKRB_n is generated.

  In the data holding circuit 106_1, the reference signal FREF is the signal REF_1 delayed by the first stage 101_1 of the first delay elements 101_1 to 101_n, and the retimed signal CKRB is the first of the third delay elements 105_1 to 105_n. Latching is performed at the rising edge of the signal CKRB_1 delayed at the stage 105_1.

In addition, the data holding circuit 106_n includes the signal REF_n obtained by delaying the reference signal FREF by 101_1 to 101_n corresponding to the first delay element n stages, and the retimed signal CKRB corresponding to the third delay element n stages 105_1 to 105_n. Latch at the rising edge of the delayed signal CKRB_n.
That is, the data holding circuits 106_1 to 106_n in the digital phase detector of this example provide the logic circuit 104 with the information on the phase advance / lag of the signals REF_1 to REF_n and the signals CKRB_1 to CKRB_n, respectively, as digital signals Q_1B to Q_nB. Output.

  Also in the digital phase detector of the present embodiment, the delay time of the first delay element 101 (101_1 to 101_n), the second delay element 102 (102_1 to 102_n), and the third delay element 105 (105_1 to 105_n). ) Is configured to be different from the delay time.

  Here, each delay element in the present embodiment is connected to one buffer circuit and a plurality of switches connected to the output terminal of the buffer circuit via the switches, as in the first embodiment. The delay time is controlled by changing the number of capacitors connected to the output terminal.

The operation of this embodiment will be described with reference to FIGS.
5 and 6 are examples of timing diagrams for explaining the operation of the digital phase detector shown in FIG.
Here, consider a case where the target signal CKR is advanced by ΔT with respect to the reference signal FREF at the start of the phase comparison. In the present embodiment, first, the phase difference ΔD between the first delay element 101 (101_1 to 101_n) and the second delay element 102 (102_1 to 102_n) is set to the maximum. That is, n / 2 capacitors are connected to the output terminals of the first delay elements 101 (101_1 to 101_n).
On the other hand, no capacitor is connected to the output terminals of the second delay element 102 (102_1 to 102_n) and the third delay element 105 (105_1 to 105_n).

  In this case, the delay amount of the first delay element 101 (101_1 to 101_n) is td0 + (td0, where td0 is the delay time of the buffer circuit, and δ is the increase in delay time every time one capacitive element is connected. n / 2) δ, the delays of the second delay element 102 (102_1 to 102_n) and the third delay element 105 (105_1 to 105_n) are td0, and the time difference is (n / 2) δ.

  As shown in FIG. 5, the output of the data holding circuit 103_0 and the output of the data holding circuit 106_0 at the stage before passing through the first-stage delay circuit are both “1”. The phase difference is successively reduced by (n / 2) δ. When the phase relationship between the target signal delayed by several stages of each delay circuit and the reference signal is reversed, the output of the data holding circuit is inverted. In this example, since the fourth data holding circuit 103_4 from the first stage is inverted, the initial phase difference is between (3n / 2) δ and (4n / 2) δ.

  On the other hand, since the clock input of the data holding circuit 106_4 is delayed by a half period of the target signal, its output remains “1”.

Next, the magnitude relationship between the delay amounts of the first delay element 101 (101_1 to 101_n) and the second delay element 102 (102_1 to 102_n) is reversed, and the difference is set smaller than before. For example, the buffer output of the first delay element 101 (101_1 to 101_n) is not changed, and n / 2 capacitors are connected, and the buffer output of the second delay element 102 (102_1 to 102_n) is 3n / Connect four capacitors.
At this time, the delay amount of the first delay element 101 (101_1 to 101_n) is td0 + (n / 2) δ, and the delay amount of the second delay element 102 (102_1 to 102_n) is (td0 + 3n / 4) δ. Thus, the time difference is − (n / 4) δ. Since no capacitive element is connected to the third delay element 105 (105_1 to 105_n), the time difference remains (n / 2) δ.

  At the input terminal of the data holding circuit 103_4, the target signal CKR is advanced with respect to the reference signal FREF. Therefore, the output of the data holding circuit 103_4 is “0”. The target signal CKR is delayed by a phase difference of − (n / 4) δ every time it passes through. When the phase relationship between the target signal CKR delayed by several stages of each delay circuit and the reference signal FREF is reversed, the output of the data holding circuit 103 is reversed again. If the inverted data holding circuit 103 is the sixth from the first stage, the initial phase difference is 4 (n / 2) δ-2 (n / 4) δ and 4 (n / 2) δ− (n / 4) It can be seen that it is between δ. Even at this timing, since the clock input of the data holding circuit 106_4 is delayed by a half period of the target signal, the output remains “1”.

Next, the magnitude relationship between the delay amounts of the first delay element 101 (101_1 to 101_n) and the second delay element 102 (102_1 to 102_n) is reversed again, and the difference is set again smaller than before. For example, (n / 2) capacitive elements are connected without changing the buffer output of the first delay element 101 (101_1 to 101_n), and the buffer output of the second delay element 102 (102_1 to 102_n) is ( Connect 3n / 8) capacitors.
At this time, the delay amount of the first delay element 101 (101_1 to 101_n) is td0 + (n / 2) δ, the delay of the second delay element 102 (102_1 to 102_n) is td0 + (3n / 8) δ, The time difference is + (n / 8) δ. At the input terminal of the sixth-stage data holding circuit 103_6, the target signal CKR is delayed with respect to the reference signal FREF. Therefore, the output of the data holding circuit 103_6 is “1”, but the seventh and subsequent stages. Each time the signal passes through the delay element 101, the target signal CKR advances by the phase difference + (n / 8) δ. When the phase relationship between the target signal CKR and the reference signal FREF delayed by several stages of each delay circuit is reversed, the output of the data holding circuit 103 is inverted again.

  If the inverted data holding circuit 103 is the seventh from the first stage, the initial phase difference is 4 (n / 2) δ-2 (n / 4) δ + (n / 8) δ and 4 (n / 2). ) δ-2 (n / 4) δ. By repeating this sequentially, a high-resolution phase comparator can be realized efficiently. Similarly, the data holding circuit 106 can detect an accurate phase difference by changing the time of the third delay element 105 (105_1 to 105_n) after the delay time of 1/2 cycle has passed. .

  As shown in FIG. 6, in this example, since the data is inverted at the 10th, 12th, and 13th stages of the data holding circuit 106, the initial phase difference between the reference signal FREF and the comparison target signal CKRB. Is between 10 (n / 2) δ-2 (n / 4) δ + (n / 8) δ and 10 (n / 2) δ-2 (n / 4) δ. Since this difference corresponds to ½ period of the target signal CKR, the delay difference corresponding to ½ period is found to be 6 (n / 2) δ. When the result of the data holding circuit 103 is normalized using this delay difference, the delay time difference between the target signal CKR and the reference signal FREF is {4 (n / 2) δ with respect to the 1/2 cycle of the target signal CKR. -2 (n / 4) δ + (n / 8) δ} / 6 (n / 2) δ = 13/24 and 12/24 = 1/2. Since this result does not include the delay amount δ due to the capacitive element, element variations such as center value fluctuations occur, and even if the delay amount δ changes, it is normalized to the period of the target signal CKR. The phase difference can be calculated accurately.

  In addition, as in the technique related to the present invention, the phase detection resolution is not directly connected to the range of the phase difference that can be detected, so the degree of freedom in design is widened.

[Fourth Embodiment]
FIG. 7 is an example of a block diagram of a phase comparator for explaining the fourth embodiment of the present invention.
In this embodiment, the signal CKR indicates a signal obtained by retiming the reference signal FREF at both the rising edge and the falling edge of the comparison target signal CKV using a flip-flop.

  The signal CKR holds the phase difference information between the original reference signal FREF and the comparison target signal CKV at the retiming time of the rising edge of the reference signal FREF, and further, at the retiming time at the falling edge, In addition to the phase difference, a half-cycle phase difference of the comparison target signal CKV is held. By comparing the phase difference between the reference signals FREF and CKR at these two retiming points, the phase difference obtained by normalizing the phase difference with the period of the comparison target signal CKV can be obtained. Also in this embodiment, it is not necessary to use a high-speed comparison target signal, and as a result, the power consumption of the phase comparator can be reduced.

  In FIG. 7, reference numeral 109 denotes a selector that switches between the comparison target signal CKV and its inverted signal CKVB according to the state of the reference signal. In this digital phase detector, the reference signal FREF is passed through the plurality of first delay elements 101_1 to 101_n, thereby generating REF_1 to REF_n sequentially delayed by the delay time of each of the first delay elements 101_1 to 101_n. . Further, the re-timed signal CKR is passed through the plurality of second delay elements 102_1 to 102_n, so that the signals CKR_1 to CKR_n sequentially delayed by the delay time of the second delay elements 102_1 to 102_n are transmitted. Generate. The selector 109 selects the comparison target signal so that it is retimed with the comparison target signal CKV at the rising edge of the reference signal and retimed with the inverted signal CKVB of the comparison target signal at the falling edge.

  In the data holding circuit 103_1, the reference signal FREF is the signal REF_1 delayed by the first stage 101_1 of the first delay elements 101_1 to 101_n, and the retimed signal CKR is the first of the second delay elements 102_1 to 102_n. Latching is performed at the rising edge of the signal CKR_1 delayed at the stage 102_1.

In addition, the data holding circuit 103_n includes the signal REF_n obtained by delaying the reference signal FREF by 101_1 to 101_n corresponding to the first delay element n stages, and the re-timed signal CKR corresponding to the second delay element n stages 102_1 to 102_n. Latch at the rising edge of the delayed signal CKR_n.
That is, the data holding circuits 103_1 to 103_n in the digital phase detector of this example provide the logic circuit 104 with the phase advance / lag information of the signals REF_1 to REF_n and the signals CKR_1 to CKR_n, respectively, as digital signals Q_1B to Q_nB. Output.

  The digital phase detector of the present embodiment is also configured so that the delay time of the first delay element 101 (101_1 to 101_n) and the delay time of the second delay element 102 (102_1 to 102_n) are different. .

  Here, each delay element in the present embodiment is connected to one buffer circuit and a plurality of switches connected to the output terminal of the buffer circuit via the switches, as in the first embodiment. The delay time is controlled by changing the number of capacitors connected to the output terminal.

The operation of this embodiment will be described with reference to FIG.
FIG. 8 is an example of a timing diagram for explaining the operation of the digital phase detector shown in FIG.
Here, consider a case where the target signal CKR is advanced by ΔT with respect to the reference signal FREF at the start of the phase comparison. In the present embodiment, first, the phase difference ΔD between the first delay element 101 (101_1 to 101_n) and the second delay element 102 (102_1 to 102_n) is set to the maximum. That is, n / 2 capacitors are connected to the output terminals of the first delay elements 101 (101_1 to 101_n).
On the other hand, no capacitive element is connected to the output terminal of the second delay element 102 (102_1 to 102_n).

  In this case, the delay amount of the first delay element 101 (101_1 to 101_n) is td0 + (td0, where td0 is the delay time of the buffer circuit, and δ is the increase in delay time every time one capacitive element is connected. n / 2) δ, the delay of the second delay element 102 (102_1 to 102_n) is td0, and the time difference is (n / 2) δ.

  As shown in FIG. 8, both the output of the data holding circuit 103_0 and the output of the data holding circuit 106_0 at the stage before passing through the first delay circuit are “1”, and each time sequentially passing through the delay elements. The phase difference is successively reduced by (n / 2) δ. When the phase relationship between the target signal delayed by several stages of each delay circuit and the reference signal is reversed, the output of the data holding circuit is inverted. In this example, since the fourth data holding circuit 103_4 from the first stage is inverted, the initial phase difference is between (3n / 2) δ and (4n / 2) δ.

Next, the magnitude relationship between the delay amounts of the first delay element 101 (101_1 to 101_n) and the second delay element 102 (102_1 to 102_n) is reversed, and the difference is set smaller than before. For example, the buffer output of the first delay element 101 (101_1 to 101_n) is not changed, and n / 2 capacitors are connected, and the buffer output of the second delay element 102 (102_1 to 102_n) is 3n / Connect four capacitors.
At this time, the delay amount of the first delay element 101 (101_1 to 101_n) is td0 + (n / 2) δ, and the delay amount of the second delay element 102 (102_1 to 102_n) is (td0 + 3n / 4) δ. Thus, the time difference is − (n / 4) δ.

  At the input terminal of the data holding circuit 103_4, the target signal CKR is advanced with respect to the reference signal FREF. Therefore, the output of the data holding circuit 103_4 is “0”. The target signal CKR is delayed by a phase difference of − (n / 4) δ every time it passes through. When the phase relationship between the target signal CKR delayed by several stages of each delay circuit and the reference signal FREF is reversed, the output of the data holding circuit 103 is reversed again. If the inverted data holding circuit 103 is the sixth from the first stage, the initial phase difference is 4 (n / 2) δ-2 (n / 4) δ and 4 (n / 2) δ− (n / 4) It can be seen that it is between δ.

Next, the magnitude relationship between the delay amounts of the first delay element 101 (101_1 to 101_n) and the second delay element 102 (102_1 to 102_n) is reversed again, and the difference is set again smaller than before. For example, (n / 2) capacitive elements are connected without changing the buffer output of the first delay element 101 (101_1 to 101_n), and the buffer output of the second delay element 102 (102_1 to 102_n) is ( Connect 3n / 8) capacitors.
At this time, the delay amount of the first delay element 101 (101_1 to 101_n) is td0 + (n / 2) δ, the delay of the second delay element 102 (102_1 to 102_n) is td0 + (3n / 8) δ, The time difference is + (n / 8) δ. At the input terminal of the sixth-stage data holding circuit 103_6, the target signal CKR is delayed with respect to the reference signal FREF. Therefore, the output of the data holding circuit 103_6 is “1”, but the seventh and subsequent stages. Each time the signal passes through the delay element 101, the target signal CKR advances by the phase difference + (n / 8) δ. When the phase relationship between the target signal CKR delayed by several stages of each delay circuit and the reference signal FREF is reversed, the output of the data holding circuit 103 is reversed again.

  If the inverted data holding circuit 103 is the seventh from the first stage, the initial phase difference is 4 (n / 2) δ-2 (n / 4) δ + (n / 8) δ and 4 (n / 2). ) δ-2 (n / 4) δ. By repeating this sequentially, an efficient and high-resolution phase comparator can be realized.

  On the other hand, the same processing is performed on the signal CKR retimed at the falling edge of the reference signal FREF to compare the phase difference with the reference signal. The retiming signal CKR at this time is further delayed by the half period of the target signal with respect to the reference signal FREF as compared with the signal retimed at the rising edge. As shown in FIG. 8, the holding circuits are provided at the 10th and subsequent stages. For example, when the data is inverted at the 10th, 12th, and 13th stages, the initial phase difference between the reference signal FREF and the comparison target signal CKR is 10 (n / 2) δ-2 (n / 4) δ + (n / 8) δ and 10 (n / 2) δ-2 (n / 4) δ. Since this difference corresponds to ½ period of the target signal CKR, the delay difference corresponding to ½ period is found to be 6 (n / 2) δ. When this delay difference 6 (n / 2) δ is used to normalize the result of the data holding circuit 103, the delay time difference between the target signal CKR and the reference signal FREF is { 4 (n / 2) δ-2 (n / 4) δ + (n / 8) δ} / 6 (n / 2) δ = 13/24 and 12/24 = 1/2 . Since this result does not include the delay amount δ due to the capacitive element, element variations such as center value fluctuations occur, and even if the delay amount δ changes, it is normalized to the period of the target signal CKR. The phase difference can be calculated accurately.

  In addition, as in the technique related to the present invention, the phase detection resolution is not directly connected to the range of the phase difference that can be detected, so the degree of freedom in design is widened.

[Fifth Embodiment]
FIG. 9 is an example of a block diagram of a phase comparator for explaining the fifth embodiment of the present invention.
In this embodiment, in the third embodiment, the latch circuit 103/106 for determining the delay / advance of the phase of the reference signal and the target signal, and an element having a fixed delay time for correcting the delay time of the logic circuit 104 141-146 are connected to each delay circuit stage. As a result, the error of the delay time of the logic circuit can be reduced, so that more accurate phase comparison can be performed. Since the basic operation is the same as that of the third embodiment, the description thereof is omitted.

<Effect>
According to the present embodiment, the reference signal and the target signal are input to the delay elements connected in a plurality of stages, respectively, and the phase difference between the reference signal and the target signal is digitally output by the difference in delay time of each stage, Based on the output result, by changing the time difference and the size of the delay element, a highly accurate phase comparison can be performed without increasing the circuit scale. As a result, even a digital synthesizer that operates at low voltage and operates at ultra-high speed, it is possible to realize a synthesizer with high precision phase control and low phase noise with low power consumption. It is possible to provide a phase comparator suitable for an advanced wireless system and a PLL circuit using the phase comparator.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there. For example, in the embodiment, the difference in delay time is changed by 1/2, but the present invention is not limited to this, and 1 / (2n +, such as 1/3 or 1/5, etc. 1) may be used (where n is a natural number).

  The present invention can be used for a phase comparator, a PLL circuit, a receiver using the PLL circuit, a transmitter, a repeater, a standard signal generator, a measuring instrument, and the like.

1 Phase comparator 2 Charge pump 3 Loop filter 4, 135 Voltage controlled oscillator VCO
5 Divider 51, 52, 53, 54, 55, 57 Phase detector 61, 62, 63, 64 Delay element 81 Phase comparator 82 Small phase comparator 83 Time digital converter 86, 87 Dividers 132, 118, 119 Latch 133, 134 Digital loop filter 107 Interface circuit 108 ΣΔ modulator 109 Selector 122, 123 Adder / subtracter

Claims (6)

A first delay circuit in which a plurality of delay elements are connected in cascade to delay the first signal;
  A second delay circuit in which a plurality of delay elements are connected in cascade to delay a second signal generated by retiming the first signal according to a third signal;
  By taking in the first signal sequentially delayed by the delay element of the first delay circuit according to the second signal sequentially delayed by the delay element of the second delay circuit, the first signal A plurality of holding circuits holding digital values representing a relative phase relationship between the second signal and the second signal;
  The delay time difference and magnitude relationship between the delay element of the first delay circuit and the delay element of the second delay circuit is expressed as a relative value between the first signal and the second signal. And a logic circuit that changes in accordance with the advance / delay of the phase. A first delay circuit in which a plurality of delay elements are connected in cascade to delay the first signal;
  A second delay circuit in which a plurality of delay elements are connected in cascade to delay a second signal generated by retiming the first signal according to a fourth signal;
  A third delay in which a plurality of delay elements are cascaded to delay a third signal generated by retiming the first signal according to a fourth signal at a timing different from that of the second signal Circuit,
  The first signal and the second signal are acquired by taking in the first signal sequentially delayed by the first delay circuit according to the second signal sequentially delayed by the second delay circuit. A plurality of first holding circuits holding digital values representing a relative phase relationship between
  The first signal and the third signal are acquired by taking in the first signal sequentially delayed by the first delay circuit according to the third signal sequentially delayed by the third delay circuit. A plurality of second holding circuits holding digital values representing a relative phase relationship between
  The difference and magnitude relationship between the delay times of the first delay circuit and the second delay circuit are changed according to the relative phase advance / delay between the first signal and the second signal. In addition, the difference and magnitude relationship between the delay times of the first delay circuit and the third delay circuit are set to the relative phase advance / delay between the first signal and the third signal. And a logic circuit that changes in accordance with the phase comparator. A first delay circuit that delays the first signal and in which a plurality of delay elements are connected in cascade;
  A second delay circuit in which a plurality of delay elements are connected in cascade to delay the second signal generated by retiming the first signal at both rising and falling edges of the third signal; ,
  By taking in the first signal sequentially delayed by the delay element of the first delay circuit according to the second signal sequentially delayed by the delay element of the second delay circuit, the first signal A plurality of holding circuits holding digital values representing a relative phase relationship between the second signal and the second signal;
  The delay time difference and magnitude relationship between the delay element of the first delay circuit and the delay element of the second delay circuit is expressed as a relative value between the first signal and the second signal. And a logic circuit that changes in accordance with the advance / delay of the phase. Each of the delay circuits has one buffer circuit, one end connected to the output terminal of the buffer circuit, a plurality of switches turned on and off by the logic circuit, and one end connected to the other end of the switch. The phase comparator according to any one of claims 1 to 3, wherein the phase comparator includes a plurality of capacitive elements of the same size and grounded at the other end. A PLL circuit using the phase comparator according to claim 1. The first signal is delayed by a first delay circuit in which a plurality of delay elements are connected in cascade,
  Generating a second signal by retiming the first signal according to a third signal;
  Delaying the second signal by a second delay circuit in which a plurality of delay elements are connected in cascade;
  A digital value representing a relative phase relationship between the first signal and the second signal by capturing the delayed first signal according to the delayed second signal. Hold and
  The delay time difference and magnitude relationship between the delay element of the first delay circuit and the delay element of the second delay circuit is expressed as a relative value between the first signal and the second signal. A method for controlling a phase comparator, characterized in that the phase comparator is changed according to phase advance / delay.

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